mirror of
https://github.com/DreamSourceLab/DSView.git
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196 lines
8.7 KiB
Python
196 lines
8.7 KiB
Python
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##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2017 Kevin Redon <kingkevin@cuvoodoo.info>
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## Copyright (C) 2019 DreamSourceLab <support@dreamsourcelab.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sigrokdecode as srd
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from collections import namedtuple
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'''
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OUTPUT_PYTHON format:
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Packet:
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[namedtuple('ss': bit start sample number,
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'es': bit end sample number,
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'si': SI bit,
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'so': SO bit,
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), ...]
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Since address and word size are variable, a list of all bits in each packet
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need to be output. Since Microwire is a synchronous protocol with separate
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input and output lines (SI and SO) they are provided together, but because
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Microwire is half-duplex only the SI or SO bits will be considered at once.
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To be able to annotate correctly the instructions formed by the bit, the start
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and end sample number of each bit (pair of SI/SO bit) are provided.
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'''
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PyPacket = namedtuple('PyPacket', 'ss es si so')
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Packet = namedtuple('Packet', 'samplenum matched cs sk si so')
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'microwire'
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name = 'Microwire'
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longname = 'Microwire'
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desc = '3-wire, half-duplex, synchronous serial bus.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = ['microwire']
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tags = ['Embedded/industrial']
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channels = (
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{'id': 'cs', 'name': 'CS', 'desc': 'Chip select'},
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{'id': 'sk', 'name': 'SK', 'desc': 'Clock'},
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{'id': 'si', 'name': 'SI', 'desc': 'Slave in'},
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{'id': 'so', 'name': 'SO', 'desc': 'Slave out'},
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)
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annotations = (
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('start-bit', 'Start bit'),
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('si-bit', 'SI bit'),
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('so-bit', 'SO bit'),
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('status-check-ready', 'Status check ready'),
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('status-check-busy', 'Status check busy'),
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('warning', 'Warning'),
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)
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annotation_rows = (
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('si-bits', 'SI bits', (0, 1)),
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('so-bits', 'SO bits', (2,)),
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('status', 'Status', (3, 4)),
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('warnings', 'Warnings', (5,)),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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pass
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def start(self):
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self.out_python = self.register(srd.OUTPUT_PYTHON)
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def decode(self):
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while True:
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# Wait for slave to be selected on rising CS.
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(cs, sk, si, so) = self.wait({0: 'r'})
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if sk:
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self.put(self.samplenum, self.samplenum, self.out_ann,
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[5, ['Clock should be low on start',
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'Clock high on start', 'Clock high', 'SK high']])
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sk = 0 # Enforce correct state for correct clock handling.
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# Because we don't know if this is bit communication or a
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# status check we have to collect the SI and SO values on SK
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# edges while the chip is selected and figure out afterwards.
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packet = []
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while cs:
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# Save change.
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packet.append(Packet(self.samplenum, self.matched, cs, sk, si, so))
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edge = 'r' if sk == 0 else 'f'
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(cs, sk, si, so) = self.wait([{0: 'l'}, {1: edge}, {3: 'e'}])
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# Save last change.
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packet.append(Packet(self.samplenum, self.matched, cs, sk, si, so))
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# Figure out if this is a status check.
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# Either there is no clock or no start bit (on first rising edge).
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status_check = True
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for change in packet:
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# Get first clock rising edge.
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if (change.matched & (0b1 << 1)) and change.sk:
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if change.si:
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status_check = False
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break
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# The packet is for a status check.
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# SO low = busy, SO high = ready.
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# The SO signal might be noisy in the beginning because it starts
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# in high impedance.
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if status_check:
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start_samplenum = packet[0].samplenum
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bit_so = packet[0].so
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# Check for SO edges.
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for change in packet:
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if (change.matched & (0b1 << 2)):
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if bit_so == 0 and change.so:
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# Rising edge Busy -> Ready.
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self.put(start_samplenum, change.samplenum,
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self.out_ann, [4, ['Busy', 'B']])
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start_samplenum = change.samplenum
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bit_so = change.so
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# Put last state.
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if bit_so == 0:
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self.put(start_samplenum, packet[-1].samplenum,
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self.out_ann, [4, ['Busy', 'B']])
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else:
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self.put(start_samplenum, packet[-1].samplenum,
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self.out_ann, [3, ['Ready', 'R']])
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else:
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# Bit communication.
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# Since the slave samples SI on clock rising edge we do the
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# same. Because the slave changes SO on clock rising edge we
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# sample on the falling edge.
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bit_start = 0 # Rising clock sample of bit start.
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bit_si = 0 # SI value at rising clock edge.
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bit_so = 0 # SO value at falling clock edge.
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start_bit = True # Start bit incoming (first bit).
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pydata = [] # Python output data.
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for change in packet:
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if (change.matched & (0b1 << 1)):
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# Clock edge.
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if change.sk: # Rising clock edge.
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if bit_start > 0: # Bit completed.
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if start_bit:
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if bit_si == 0: # Start bit missing.
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self.put(bit_start, change.samplenum,
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self.out_ann,
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[5, ['Start bit not high',
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'Start bit low']])
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else:
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self.put(bit_start, change.samplenum,
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self.out_ann,
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[0, ['Start bit', 'S']])
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start_bit = False
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else:
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self.put(bit_start, change.samplenum,
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self.out_ann,
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[1, ['SI bit: %d' % bit_si,
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'SI: %d' % bit_si,
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'%d' % bit_si]])
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self.put(bit_start, change.samplenum,
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self.out_ann,
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[2, ['SO bit: %d' % bit_so,
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'SO: %d' % bit_so,
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'%d' % bit_so]])
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pydata.append(PyPacket(bit_start,
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change.samplenum, bit_si, bit_so))
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bit_start = change.samplenum
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bit_si = change.si
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else: # Falling clock edge.
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bit_so = change.so
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elif (change.matched & (0b1 << 0)) and \
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change.cs == 0 and change.sk == 0:
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# End of packet.
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self.put(bit_start, change.samplenum, self.out_ann,
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[1, ['SI bit: %d' % bit_si,
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'SI: %d' % bit_si, '%d' % bit_si]])
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self.put(bit_start, change.samplenum, self.out_ann,
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[2, ['SO bit: %d' % bit_so,
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'SO: %d' % bit_so, '%d' % bit_so]])
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pydata.append(PyPacket(bit_start, change.samplenum,
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bit_si, bit_so))
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self.put(packet[0].samplenum, packet[len(packet) - 1].samplenum,
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self.out_python, pydata)
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