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575 lines
28 KiB
Python
575 lines
28 KiB
Python
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##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2020 Raptor Engineering, LLC <support@raptorengineering.com>
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##
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## This program is free software: you can redistribute it and/or modify
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## it under the terms of the GNU Affero General Public License as
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## published by the Free Software Foundation, either version 3 of the
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## License, or (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU Affero General Public License for more details.
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##
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## You should have received a copy of the GNU Affero General Public License
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## along with this program. If not, see <https://www.gnu.org/licenses/>.
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##
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import sigrokdecode as srd
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# ...
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fields = {
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# START field (indicates the start of a transaction)
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'START': {
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0b1: 'Start of FSI cycle',
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},
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}
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'fsi'
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name = 'FSI'
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longname = 'Flexible Service Interface'
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desc = 'Protocol for FSI devices on Raptor OpenPOWER systems.'
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license = 'agplv3'
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inputs = ['logic']
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outputs = []
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tags = ['PC']
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channels = (
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{'id': 'data', 'name': 'DATA', 'desc': 'Frame'},
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{'id': 'clock', 'name': 'CLOCK', 'desc': 'Clock'},
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)
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annotations = (
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('warnings', 'Warnings'),
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('start', 'Start'),
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('cycle-type', 'Cycle type'),
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('direction', 'Direction'),
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('addr', 'Address'),
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('data', 'Data'),
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('commands', 'Commands'),
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('crc', 'CRC'),
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('turn-around', 'TAR'),
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)
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annotation_rows = (
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('data', 'Data', (1, 2, 3, 4, 5, 6, 7, 8,)),
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('warnings', 'Warnings', (0,)),
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)
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def __init__(self):
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self.tar_cycles = 3
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self.reset()
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def reset(self):
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self.state = 'IDLE'
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self.break_start_sample_number = 0
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self.break_counter = 0
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self.samplenum = 0
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self.samplenum_prev = 0
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self.fsi_data_prev = 0
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self.fsi_data_break_prev = 0
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self.crc_internal = 0
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self.response_received = 0
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self.crc_calculating = 0
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self.busy_seq_count = 0
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self.valid_response = 0
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self.prev_address = {}
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self.prev_address_valid = {0: False, 1: False, 2: False, 3: False}
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self.ss_block = None
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self.es_block = None
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def putb(self, data):
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self.put(self.ss_block, self.es_block, self.out_ann, data)
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def decode(self):
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while True:
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# FSI is clocked out on the falling edge and latched in on the rising edge of the clock...according to the specification.
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# That said, the specification is not clear on what this actually means (and it doesn't follow industry convention).
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# Real IBM POWER9 hardware is verified to work in the following mode:
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# FSI data being sent to the master is latched by the master logic at the falling edge of the FSI clock
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# FSI data being from to the master is strobed by the master logic at the falling edge of the FSI clock
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# FSI data being sent to the slave is latched by the slave logic at the rising edge of the FSI clock
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# FSI data being from to the slave is strobed by the slave logic at the rising edge of the FSI clock
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#
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# The above means that we have to be able to make a reasonable guess as to who is transmitting (the master or the slave)
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# in order to know which edge to sample on
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# Wait for either clock edge
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(data, clk) = self.wait({1: 'e'})
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# FSI data is electrically inverted
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fsi_data = not data
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fsi_clk = clk
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current_sample_number = self.samplenum
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# Detect BREAK commands
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# Note these can only be sent by the master, so sample on the rising clock edge only
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if (fsi_clk):
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if (self.fsi_data_break_prev == 1):
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self.break_counter = self.break_counter + 1
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if (self.break_counter == 256):
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self.ss_block = self.break_start_sample_number
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self.es_block = current_sample_number
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self.putb([6, ['BREAK']])
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self.state = 'BREAK_TAR_QUEUED'
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self.busy_seq_count = 0
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self.valid_response = 0
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self.prev_address = {}
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self.prev_address_valid = {0: False, 1: False, 2: False, 3: False}
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self.ss_block = current_sample_number
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else:
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if (self.break_counter > 256):
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self.es_block = current_sample_number
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self.putb([0, ['BREAK asserted in excess of specification cycles']])
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self.break_start_sample_number = current_sample_number
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self.break_counter = 0
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self.fsi_data_break_prev = fsi_data
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if ((self.state == 'TAR') or (self.state == 'RX_SLAVE_ID') or (self.state == 'RESPONSE') or (self.state == 'RX_DATA')
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or (self.state == 'RX_IPOLL_INTERRUPT_FIELD') or (self.state == 'RX_IPOLL_DMA_CONTROL_FIELD') or (self.state == 'RX_IPOLL_DMA_CONTROL_FIELD')
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or ((self.state == 'CRC') and (self.valid_response))):
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# Slave is / should be transmitting, sample on falling clock edge only
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if (fsi_clk):
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continue
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else:
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# Master is / should be transmitting, sample on rising clock edge only
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if (not fsi_clk):
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continue
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# Transfer state machine
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if (self.state == 'IDLE'):
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self.crc_internal = 0
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self.response_received = 0
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if (self.fsi_data_prev == 1):
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self.tx_slave_id = 0
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self.data_count = 2
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self.ss_block = self.samplenum_prev
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self.es_block = current_sample_number
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self.putb([1, ['START']])
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self.ss_block = current_sample_number
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self.crc_calculating = 1
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self.state = 'TX_SLAVE_ID'
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elif (self.state == 'TX_SLAVE_ID'):
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self.crc_calculating = 1
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if (self.data_count > 0):
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self.tx_slave_id = (self.tx_slave_id >> 1) | (self.fsi_data_prev << 1)
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self.data_count = self.data_count - 1
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if (self.data_count == 0):
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self.es_block = current_sample_number
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self.putb([5, ['Slave ID: 0x%01x' % self.tx_slave_id]])
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self.ss_block = current_sample_number
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self.command_count = 0
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self.command_code = 0
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self.command = None
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self.valid_command = False
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self.state = 'COMMAND'
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elif (self.state == 'COMMAND'):
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self.crc_calculating = 1
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self.command_code = (self.command_code << 1) | self.fsi_data_prev
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self.command_count = self.command_count + 1
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if ((self.command_count == 3) and (self.command_code == 0b100)):
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self.command = 'ABS_ADR'
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self.valid_command = True
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elif ((self.command_count == 3) and (self.command_code == 0b101)):
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self.command = 'REL_ADR'
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self.valid_command = True
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elif ((self.command_count == 2) and (self.command_code == 0b11)):
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self.command = 'SAME_ADR'
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self.valid_command = True
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elif ((self.command_count == 3) and (self.command_code == 0b010)):
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self.command = 'D_POLL'
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self.valid_command = True
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elif ((self.command_count == 3) and (self.command_code == 0b011)):
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self.command = 'E_POLL'
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self.valid_command = True
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elif ((self.command_count == 3) and (self.command_code == 0b001)):
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self.command = 'I_POLL'
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self.valid_command = True
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if ((self.command_count > 7) or (self.valid_command == True)):
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if (self.command_count == 8):
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self.es_block = current_sample_number
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self.putb([6, ['Invalid command code: 0x%02x/%d' % (self.command_code, self.command_count)]])
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self.putb([0, ['%s' % 'Invalid command code']])
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self.ss_block = current_sample_number
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self.state = 'IDLE'
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else:
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self.es_block = current_sample_number
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self.putb([6, ['Command: %s (0x%02x/%d)' % (self.command, self.command_code, self.command_count)]])
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self.ss_block = current_sample_number
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if (self.command == 'ABS_ADR'):
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self.address_length = 21
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self.address_count = 0
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self.address = 0
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self.state = 'DIRECTION'
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elif (self.command == 'REL_ADR'):
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self.address_length = 8
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self.address_count = 0
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self.address = 0
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self.state = 'DIRECTION'
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elif (self.command == 'SAME_ADR'):
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self.address_length = 2
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self.address_count = 0
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self.address = 0
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self.state = 'DIRECTION'
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elif (self.command == 'D_POLL'):
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self.crc = 0
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self.crc_count = 0
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self.state = 'CRC'
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elif (self.command == 'E_POLL'):
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self.crc = 0
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self.crc_count = 0
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self.state = 'CRC'
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elif (self.command == 'I_POLL'):
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self.crc = 0
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self.crc_count = 0
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self.state = 'CRC'
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else:
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self.state = 'IDLE'
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elif (self.state == 'DIRECTION'):
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self.crc_calculating = 1
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self.direction = self.fsi_data_prev
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self.es_block = current_sample_number
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if (self.direction == 1):
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self.putb([3, ['Direction: %s' % 'Read']])
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else:
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self.putb([3, ['Direction: %s' % 'Write']])
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self.ss_block = current_sample_number
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if (self.command == 'REL_ADR'):
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self.state = 'REL_ADDRESS_SIGN'
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else:
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self.state = 'ADDRESS'
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elif (self.state == 'REL_ADDRESS_SIGN'):
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self.crc_calculating = 1
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self.relative_address_negative = self.fsi_data_prev
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self.es_block = current_sample_number
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if (self.relative_address_negative == 1):
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self.putb([5, ['Relative address sign: %s' % '(-)']])
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else:
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self.putb([5, ['Relative address sign: %s' % '(+)']])
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self.ss_block = current_sample_number
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self.state = 'ADDRESS'
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elif (self.state == 'ADDRESS'):
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self.crc_calculating = 1
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self.address = (self.address << 1) | self.fsi_data_prev
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self.address_count = self.address_count + 1
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if (self.address_count >= self.address_length):
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self.address_raw = self.address
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if (self.prev_address_valid[self.tx_slave_id]):
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if (self.command == 'SAME_ADR'):
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self.address = (self.prev_address[self.tx_slave_id] & ~0b11) | (self.address_raw & 0b11)
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elif (self.command == 'REL_ADR'):
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if (self.relative_address_negative):
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self.address = self.prev_address[self.tx_slave_id] - (0x100 - self.address_raw)
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else:
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self.address = self.prev_address[self.tx_slave_id] + self.address_raw
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self.es_block = current_sample_number
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if (((self.command == 'SAME_ADR') or (self.command == 'REL_ADR'))):
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self.putb([5, ['Address: 0x%06x (0x%03x)' % (self.address, self.address_raw)]])
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if (not self.prev_address_valid[self.tx_slave_id]):
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self.putb([0, ['%s' % 'Base address for relative address not captured']])
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else:
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self.putb([5, ['Address: 0x%06x' % self.address]])
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self.ss_block = current_sample_number
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self.state = 'DATA_SIZE'
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elif (self.state == 'DATA_SIZE'):
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self.crc_calculating = 1
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if (self.direction and ((self.address_raw & 3) == 3) and self.fsi_data_prev):
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# OpenFSI suffers from an unfortunate conflict between the SAME_ADR command
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# and the TERM command. Both start with 2'b11 and since both are variable
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# length it is impossible to determine if a TERM command was sent until this
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# point in the receiver process!
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#
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# Set correct command code for further processing
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self.command_code = 0b111111
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self.command_count = 6
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self.command = 'TERM'
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self.es_block = current_sample_number
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self.putb([6, ['Command: %s (0x%02x/%d)' % (self.command, self.command_code, self.command_count)]])
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self.ss_block = current_sample_number
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self.direction = 0
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self.busy_seq_count = 0
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self.crc = 0
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self.crc_count = 0
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self.state = 'CRC'
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else:
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if (self.fsi_data_prev == 0):
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self.data_size = 'BYTE'
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else:
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if ((self.address_raw & 3) == 1):
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self.data_size = 'WORD'
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# Force lowest address bits to specification-mandated values if required
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self.address = (self.address & ~3) | 1
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elif ((self.address_raw & 1) == 0):
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self.data_size = 'HALF_WORD'
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# Force lowest address bits to specification-mandated values if required
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self.address = self.address & ~1
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else:
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self.data_size = 'UNKNOWN'
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self.es_block = current_sample_number
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if (self.data_size == 'UNKNOWN'):
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self.putb([0, ['Data Size: %s' % 'UNKNOWN']])
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self.state = 'IDLE'
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else:
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self.putb([3, ['Data Size: %s' % self.data_size]])
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if (self.direction == 1):
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self.crc = 0
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self.crc_count = 0
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self.state = 'CRC'
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else:
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self.data = 0
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self.data_count = 0
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if (self.data_size == 'BYTE'):
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self.data_length = 8
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elif (self.data_size == 'HALF_WORD'):
|
||
|
|
self.data_length = 16
|
||
|
|
elif (self.data_size == 'WORD'):
|
||
|
|
self.data_length = 32
|
||
|
|
else:
|
||
|
|
self.data_size = None
|
||
|
|
self.state = 'TX_DATA'
|
||
|
|
self.ss_block = current_sample_number
|
||
|
|
|
||
|
|
elif (self.state == 'TX_DATA'):
|
||
|
|
self.crc_calculating = 1
|
||
|
|
self.data = (self.data << 1) | self.fsi_data_prev
|
||
|
|
self.data_count = self.data_count + 1
|
||
|
|
if (self.data_count >= self.data_length):
|
||
|
|
self.es_block = current_sample_number
|
||
|
|
if (self.data_size == 'BYTE'):
|
||
|
|
self.putb([5, ['Data: 0x%02x' % self.data]])
|
||
|
|
elif (self.data_size == 'HALF_WORD'):
|
||
|
|
self.putb([5, ['Data: 0x%04x' % self.data]])
|
||
|
|
else:
|
||
|
|
self.putb([5, ['Data: 0x%08x' % self.data]])
|
||
|
|
self.ss_block = current_sample_number
|
||
|
|
self.crc = 0
|
||
|
|
self.crc_count = 0
|
||
|
|
self.state = 'CRC'
|
||
|
|
|
||
|
|
elif (self.state == 'CRC'):
|
||
|
|
if (self.crc_count == 0):
|
||
|
|
self.computed_crc_tx_end = self.crc_internal
|
||
|
|
self.crc_calculating = 1
|
||
|
|
self.crc = (self.crc << 1) | self.fsi_data_prev
|
||
|
|
self.crc_count = self.crc_count + 1
|
||
|
|
if (self.crc_count >= 4):
|
||
|
|
self.es_block = current_sample_number
|
||
|
|
if (self.crc == self.computed_crc_tx_end):
|
||
|
|
self.putb([7, ['CRC: 0x%01x (GOOD)' % self.crc]])
|
||
|
|
if (self.response_received):
|
||
|
|
if (((self.command == 'ABS_ADR') or (self.command == 'REL_ADR') or (self.command == 'SAME_ADR'))
|
||
|
|
and ((self.response == 'ACK_D') or (self.response == 'ACK'))):
|
||
|
|
self.prev_address[self.tx_slave_id] = self.address
|
||
|
|
self.prev_address_valid[self.tx_slave_id] = True
|
||
|
|
else:
|
||
|
|
self.putb([7, ['CRC: 0x%01x (BAD)' % self.crc]])
|
||
|
|
self.putb([0, ['%s' % 'Bad CRC']])
|
||
|
|
self.ss_block = current_sample_number
|
||
|
|
self.tar_timer = 0
|
||
|
|
self.state = 'TAR'
|
||
|
|
self.timeout_counter = 0
|
||
|
|
|
||
|
|
elif (self.state == 'BREAK_TAR_QUEUED'):
|
||
|
|
# Special case, since break operates outside of the main state machine
|
||
|
|
# This state is a safe entry point into the main state machine
|
||
|
|
self.tar_timer = 0
|
||
|
|
self.state = 'BREAK_TAR'
|
||
|
|
|
||
|
|
elif (self.state == 'BREAK_TAR'):
|
||
|
|
self.tar_timer = self.tar_timer + 1
|
||
|
|
if (self.tar_timer > self.tar_cycles):
|
||
|
|
self.crc_calculating = 0
|
||
|
|
self.crc_internal = 0
|
||
|
|
self.es_block = current_sample_number
|
||
|
|
self.putb([8, ['%s' % 'TAR']])
|
||
|
|
self.ss_block = current_sample_number
|
||
|
|
self.state = 'IDLE'
|
||
|
|
|
||
|
|
elif (self.state == 'TAR'):
|
||
|
|
self.crc_calculating = 0
|
||
|
|
self.crc_internal = 0
|
||
|
|
self.tar_timer = self.tar_timer + 1
|
||
|
|
if (self.tar_timer > self.tar_cycles):
|
||
|
|
if (self.response_received == 1):
|
||
|
|
self.response_received = 0
|
||
|
|
if (self.rx_slave_id == self.tx_slave_id):
|
||
|
|
if (self.response == 'BUSY'):
|
||
|
|
self.busy_seq_count = self.busy_seq_count + 1
|
||
|
|
else:
|
||
|
|
self.busy_seq_count = 0
|
||
|
|
# Sequence complete
|
||
|
|
self.state = 'IDLE'
|
||
|
|
if (self.timeout_counter == 0):
|
||
|
|
self.es_block = self.samplenum_prev
|
||
|
|
self.putb([8, ['%s' % 'TAR']])
|
||
|
|
self.ss_block = current_sample_number
|
||
|
|
if (self.fsi_data_prev == 1):
|
||
|
|
self.crc_calculating = 1
|
||
|
|
self.rx_slave_id = 0
|
||
|
|
self.data_count = 2
|
||
|
|
if (self.state == 'IDLE'):
|
||
|
|
# Already processed response message, was going to IDLE state
|
||
|
|
self.state = 'TX_SLAVE_ID'
|
||
|
|
else:
|
||
|
|
self.state = 'RX_SLAVE_ID'
|
||
|
|
self.ss_block = self.samplenum_prev
|
||
|
|
self.es_block = current_sample_number
|
||
|
|
self.putb([1, ['START']])
|
||
|
|
self.ss_block = current_sample_number
|
||
|
|
else:
|
||
|
|
self.timeout_counter = self.timeout_counter + 1
|
||
|
|
if (self.timeout_counter >= 256):
|
||
|
|
self.es_block = current_sample_number
|
||
|
|
self.putb([8, ['%s' % 'Response timeout']])
|
||
|
|
self.putb([0, ['%s' % 'Response timeout']])
|
||
|
|
self.state = 'IDLE'
|
||
|
|
|
||
|
|
elif (self.state == 'RX_SLAVE_ID'):
|
||
|
|
self.crc_calculating = 1
|
||
|
|
self.response_received = 1
|
||
|
|
if (self.data_count > 0):
|
||
|
|
self.rx_slave_id = (self.rx_slave_id >> 1) | (self.fsi_data_prev << 1)
|
||
|
|
self.data_count = self.data_count - 1
|
||
|
|
if (self.data_count == 0):
|
||
|
|
self.es_block = current_sample_number
|
||
|
|
self.putb([5, ['Slave ID: 0x%01x' % self.rx_slave_id]])
|
||
|
|
if (self.rx_slave_id != self.tx_slave_id):
|
||
|
|
self.putb([0, ['%s' % 'Slave ID does not match active transaction']])
|
||
|
|
self.ss_block = current_sample_number
|
||
|
|
self.response_count = 0
|
||
|
|
self.response_code = 0
|
||
|
|
self.response = None
|
||
|
|
self.valid_response = False
|
||
|
|
self.state = 'RESPONSE'
|
||
|
|
|
||
|
|
elif (self.state == 'RESPONSE'):
|
||
|
|
self.crc_calculating = 1
|
||
|
|
self.response_code = (self.response_code << 1) | self.fsi_data_prev
|
||
|
|
self.response_count = self.response_count + 1
|
||
|
|
if ((self.command == 'I_POLL') and (self.rx_slave_id == self.tx_slave_id) and (self.response_count == 1) and (self.response_code == 0b0)):
|
||
|
|
self.response = 'I_POLL_RSP'
|
||
|
|
self.valid_response = True
|
||
|
|
elif ((self.response_count == 2) and (self.response_code == 0b00)):
|
||
|
|
if (self.direction == 1):
|
||
|
|
self.response = 'ACK_D'
|
||
|
|
else:
|
||
|
|
self.response = 'ACK'
|
||
|
|
self.valid_response = True
|
||
|
|
elif ((self.response_count == 2) and (self.response_code == 0b01)):
|
||
|
|
self.response = 'BUSY'
|
||
|
|
self.valid_response = True
|
||
|
|
elif ((self.response_count == 2) and (self.response_code == 0b10)):
|
||
|
|
self.response = 'ERR_A'
|
||
|
|
self.valid_response = True
|
||
|
|
elif ((self.response_count == 2) and (self.response_code == 0b11)):
|
||
|
|
self.response = 'ERR_C'
|
||
|
|
self.valid_response = True
|
||
|
|
if ((self.response_count > 2) or (self.valid_response == True)):
|
||
|
|
if (self.response_count == 8):
|
||
|
|
self.es_block = current_sample_number
|
||
|
|
self.putb([6, ['Invalid response code: 0x%02x/%d' % (self.response_code, self.response_count)]])
|
||
|
|
self.putb([0, ['%s' % 'Invalid response code']])
|
||
|
|
self.ss_block = current_sample_number
|
||
|
|
self.state = 'IDLE'
|
||
|
|
else:
|
||
|
|
self.es_block = current_sample_number
|
||
|
|
self.putb([6, ['Response: %s (0x%02x/%d)' % (self.response, self.response_code, self.response_count)]])
|
||
|
|
self.ss_block = current_sample_number
|
||
|
|
if (self.response == 'ACK_D'):
|
||
|
|
self.data = 0
|
||
|
|
self.data_count = 0
|
||
|
|
if (self.data_size == 'BYTE'):
|
||
|
|
self.data_length = 8
|
||
|
|
elif (self.data_size == 'HALF_WORD'):
|
||
|
|
self.data_length = 16
|
||
|
|
elif (self.data_size == 'WORD'):
|
||
|
|
self.data_length = 32
|
||
|
|
else:
|
||
|
|
self.data_size = None
|
||
|
|
#self.state = 'DIRECTION'
|
||
|
|
self.state = 'RX_DATA'
|
||
|
|
elif (self.response == 'ACK'):
|
||
|
|
self.crc = 0
|
||
|
|
self.crc_count = 0
|
||
|
|
self.state = 'CRC'
|
||
|
|
elif (self.response == 'BUSY'):
|
||
|
|
self.crc = 0
|
||
|
|
self.crc_count = 0
|
||
|
|
self.state = 'CRC'
|
||
|
|
elif (self.response == 'ERR_A'):
|
||
|
|
self.crc = 0
|
||
|
|
self.crc_count = 0
|
||
|
|
self.state = 'CRC'
|
||
|
|
elif (self.response == 'ERR_C'):
|
||
|
|
self.crc = 0
|
||
|
|
self.crc_count = 0
|
||
|
|
self.state = 'CRC'
|
||
|
|
elif (self.response == 'I_POLL_RSP'):
|
||
|
|
self.data = 0
|
||
|
|
self.data_count = 0
|
||
|
|
self.data_length = 2
|
||
|
|
self.state = 'RX_IPOLL_INTERRUPT_FIELD'
|
||
|
|
else:
|
||
|
|
self.state = 'IDLE'
|
||
|
|
|
||
|
|
elif (self.state == 'RX_DATA'):
|
||
|
|
self.crc_calculating = 1
|
||
|
|
self.data = (self.data << 1) | self.fsi_data_prev
|
||
|
|
self.data_count = self.data_count + 1
|
||
|
|
if (self.data_count >= self.data_length):
|
||
|
|
self.es_block = current_sample_number
|
||
|
|
self.putb([5, ['Data: 0x%08x' % self.data]])
|
||
|
|
self.ss_block = current_sample_number
|
||
|
|
self.crc = 0
|
||
|
|
self.crc_count = 0
|
||
|
|
self.state = 'CRC'
|
||
|
|
|
||
|
|
elif (self.state == 'RX_IPOLL_INTERRUPT_FIELD'):
|
||
|
|
self.crc_calculating = 1
|
||
|
|
self.data = (self.data << 1) | self.fsi_data_prev
|
||
|
|
self.data_count = self.data_count + 1
|
||
|
|
if (self.data_count >= self.data_length):
|
||
|
|
self.es_block = current_sample_number
|
||
|
|
self.putb([5, ['Interrupt Field: 0x%01x' % self.data]])
|
||
|
|
self.ss_block = current_sample_number
|
||
|
|
self.data = 0
|
||
|
|
self.data_count = 0
|
||
|
|
self.data_length = 3
|
||
|
|
self.state = 'RX_IPOLL_DMA_CONTROL_FIELD'
|
||
|
|
|
||
|
|
elif (self.state == 'RX_IPOLL_DMA_CONTROL_FIELD'):
|
||
|
|
self.crc_calculating = 1
|
||
|
|
self.data = (self.data << 1) | self.fsi_data_prev
|
||
|
|
self.data_count = self.data_count + 1
|
||
|
|
if (self.data_count >= self.data_length):
|
||
|
|
self.es_block = current_sample_number
|
||
|
|
self.putb([5, ['DMA Control Field: 0x%01x' % self.data]])
|
||
|
|
self.ss_block = current_sample_number
|
||
|
|
self.crc = 0
|
||
|
|
self.crc_count = 0
|
||
|
|
self.state = 'CRC'
|
||
|
|
|
||
|
|
# CRC calculation
|
||
|
|
# Implement Galios-type LFSR for polynomial 0x7 (MSB first)
|
||
|
|
crc_prev = self.crc_internal
|
||
|
|
if (self.crc_calculating):
|
||
|
|
crc_feedback = (((crc_prev >> 3) & 1) ^ self.fsi_data_prev) & 1
|
||
|
|
if (self.crc_calculating):
|
||
|
|
self.crc_internal = (self.crc_internal & ~(1 << 0)) | ((crc_feedback & 1) << 0)
|
||
|
|
self.crc_internal = (self.crc_internal & ~(1 << 1)) | ((((crc_prev & 1) ^ crc_feedback) & 1) << 1)
|
||
|
|
self.crc_internal = (self.crc_internal & ~(1 << 2)) | (((((crc_prev >> 1) & 1) ^ crc_feedback) & 1) << 2)
|
||
|
|
self.crc_internal = (self.crc_internal & ~(1 << 3)) | ((((crc_prev >> 2) & 1) & 1) << 3)
|
||
|
|
|
||
|
|
self.fsi_data_prev = fsi_data
|
||
|
|
self.samplenum_prev = current_sample_number
|