mirror of
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108 lines
3.6 KiB
Python
108 lines
3.6 KiB
Python
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##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2016 fenugrec <fenugrec users.sourceforge.net>
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## Copyright (C) 2019 DreamSourceLab <support@dreamsourcelab.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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# TODO:
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# - Annotations are very crude and could be improved.
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# - Annotate every nibble? Would give insight on interrupted shifts.
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# - Annotate invalid "command" nibbles while SYNC==1?
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import sigrokdecode as srd
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'aud'
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name = 'AUD'
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longname = 'Advanced User Debugger'
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desc = 'Renesas/Hitachi Advanced User Debugger (AUD) protocol.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = []
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tags = ['Debug/trace']
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channels = (
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{'id': 'audck', 'name': 'AUDCK', 'desc': 'AUD clock'},
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{'id': 'naudsync', 'name': 'nAUDSYNC', 'desc': 'AUD sync'},
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{'id': 'audata3', 'name': 'AUDATA3', 'desc': 'AUD data line 3'},
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{'id': 'audata2', 'name': 'AUDATA2', 'desc': 'AUD data line 2'},
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{'id': 'audata1', 'name': 'AUDATA1', 'desc': 'AUD data line 1'},
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{'id': 'audata0', 'name': 'AUDATA0', 'desc': 'AUD data line 0'},
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)
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annotations = (
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('dest', 'Destination address'),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.ncnt = 0
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self.nmax = 0
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self.addr = 0
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self.lastaddr = 0
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self.ss = 0
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def putx(self, data):
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self.put(self.ss, self.samplenum, self.out_ann, data)
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def handle_clk_edge(self, clk, sync, datapins):
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# Reconstruct nibble.
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nib = 0
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for i in range(4):
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nib |= datapins[3-i] << i
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# sync == 1: annotate if finished; update cmd.
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# TODO: Annotate idle level (nibble = 0x03 && SYNC=1).
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if sync == 1:
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if (self.ncnt == self.nmax) and (self.nmax != 0):
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# Done shifting an address: annotate.
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self.putx([0, ['0x%08X' % self.addr]])
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self.lastaddr = self.addr
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self.ncnt = 0
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self.addr = self.lastaddr
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self.ss = self.samplenum
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if nib == 0x08:
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self.nmax = 1
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elif nib == 0x09:
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self.nmax = 2
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elif nib == 0x0a:
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self.nmax = 4
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elif nib == 0x0b:
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self.nmax = 8
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else:
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# Undefined or idle.
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self.nmax = 0
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else:
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# sync == 0, valid cmd: start or continue shifting in nibbles.
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if (self.nmax > 0):
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# Clear tgt nibble.
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self.addr &= ~(0x0F << (self.ncnt * 4))
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# Set nibble.
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self.addr |= nib << (self.ncnt * 4)
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self.ncnt += 1
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def decode(self):
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while True:
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(clk, sync, d3, d2, d1, d0) = self.wait({0: 'r'})
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d = (d3, d2, d1, d0)
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self.handle_clk_edge(clk, sync, d)
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