2019-09-09 00:07:19 -07:00
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/*
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* This file is part of the libsigrok project.
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*
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* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
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* Copyright (C) 2013 DreamSourceLab <support@dreamsourcelab.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBDSL_HARDWARE_DSL_H
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#define LIBDSL_HARDWARE_DSL_H
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#include <glib.h>
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#include "libsigrok.h"
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#include "libsigrok-internal.h"
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#include "command.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <errno.h>
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#include <assert.h>
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#include <sys/stat.h>
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#include <inttypes.h>
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#undef min
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#define min(a,b) ((a)<(b)?(a):(b))
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#undef max
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#define max(a,b) ((a)>(b)?(a):(b))
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/* Message logging helpers with subsystem-specific prefix string. */
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#define LOG_PREFIX "DSL Hardware: "
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#define sr_log(l, s, args...) sr_log(l, LOG_PREFIX s, ## args)
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#define sr_spew(s, args...) sr_spew(LOG_PREFIX s, ## args)
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#define sr_dbg(s, args...) sr_dbg(LOG_PREFIX s, ## args)
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#define sr_info(s, args...) sr_info(LOG_PREFIX s, ## args)
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#define sr_warn(s, args...) sr_warn(LOG_PREFIX s, ## args)
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#define sr_err(s, args...) sr_err(LOG_PREFIX s, ## args)
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#define USB_INTERFACE 0
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#define USB_CONFIGURATION 1
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#define NUM_TRIGGER_STAGES 16
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#define NUM_SIMUL_TRANSFERS 64
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#define DSL_REQUIRED_VERSION_MAJOR 2
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#define DSL_REQUIRED_VERSION_MINOR 0
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/* hardware Capabilities */
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#define CAPS_MODE_LOGIC (1 << 0)
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#define CAPS_MODE_ANALOG (1 << 1)
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#define CAPS_MODE_DSO (1 << 2)
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#define CAPS_FEATURE_NONE 0
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// voltage threshold
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#define CAPS_FEATURE_VTH (1 << 0)
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// with external buffer
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#define CAPS_FEATURE_BUF (1 << 1)
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// pre offset control
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#define CAPS_FEATURE_PREOFF (1 << 2)
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// small startup eemprom
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#define CAPS_FEATURE_SEEP (1 << 3)
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// zero calibration ability
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#define CAPS_FEATURE_ZERO (1 << 4)
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// use HMCAD1511 adc chip
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#define CAPS_FEATURE_HMCAD1511 (1 << 5)
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// usb 3.0
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#define CAPS_FEATURE_USB30 (1 << 6)
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// pogopin panel
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#define CAPS_FEATURE_POGOPIN (1 << 7)
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// use ADF4360-7 vco chip
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#define CAPS_FEATURE_ADF4360 (1 << 8)
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// 20M bandwidth limitation
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#define CAPS_FEATURE_20M (1 << 8)
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/* end */
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#define DSLOGIC_ATOMIC_BITS 6
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#define DSLOGIC_ATOMIC_SAMPLES (1 << DSLOGIC_ATOMIC_BITS)
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#define DSLOGIC_ATOMIC_SIZE (1 << (DSLOGIC_ATOMIC_BITS - 3))
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#define DSLOGIC_ATOMIC_MASK (0xFFFF << DSLOGIC_ATOMIC_BITS)
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/*
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* for basic configuration
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*/
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#define TRIG_EN_BIT 0
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#define CLK_TYPE_BIT 1
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#define CLK_EDGE_BIT 2
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#define RLE_MODE_BIT 3
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#define DSO_MODE_BIT 4
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#define HALF_MODE_BIT 5
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#define QUAR_MODE_BIT 6
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#define ANALOG_MODE_BIT 7
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#define FILTER_BIT 8
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#define INSTANT_BIT 9
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#define STRIG_MODE_BIT 11
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#define STREAM_MODE_BIT 12
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#define LPB_TEST_BIT 13
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#define EXT_TEST_BIT 14
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#define INT_TEST_BIT 15
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#define bmNONE 0
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#define bmEEWP (1 << 0)
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#define bmFORCE_RDY (1 << 1)
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#define bmFORCE_STOP (1 << 2)
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#define bmSCOPE_SET (1 << 3)
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#define bmSCOPE_CLR (1 << 4)
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#define bmBW20M_SET (1 << 5)
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#define bmBW20M_CLR (1 << 6)
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/*
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* packet content check
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*/
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#define TRIG_CHECKID 0x55555555
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#define DSO_PKTID 0xa500
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/*
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* for DSCope device
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* trans: x << 8 + y
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* x = vpos(coarse), each step(1024 total) indicate x(mv) at 1/20 attenuation, and x/10(mv) at 1/2 attenuation
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* y = voff(fine), each step(1024 total) indicate y/100(mv) at 1/20 attenuation, adn y/1000(mv) at 1/2 attenuation
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* voff: x << 10 + y
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* x = vpos(coarse) default bias
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* y = voff(fine) default bias
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* the final offset: x+DSCOPE_CONSTANT_BIAS->vpos(coarse); y->voff(fine)
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*/
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#define DSCOPE_CONSTANT_BIAS 160
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#define DSCOPE_TRANS_CMULTI 10
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#define DSCOPE_TRANS_FMULTI 100.0
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/*
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* for DSCope20 device
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* trans: the whole windows offset map to the offset pwm(1024 total)
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* voff: offset pwm constant bias to balance circuit offset
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*/
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#define CALI_VGAIN_RANGE 100
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enum LANGUAGE {
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LANGUAGE_CN = 25,
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LANGUAGE_EN = 31,
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};
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struct DSL_caps {
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uint64_t mode_caps;
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uint64_t feature_caps;
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uint64_t channels;
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uint64_t hw_depth;
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uint64_t dso_depth;
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uint8_t intest_channel;
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const uint64_t *vdivs;
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const uint64_t *samplerates;
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uint8_t vga_id;
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uint16_t default_channelmode;
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uint64_t default_samplerate;
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uint64_t default_samplelimit;
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uint16_t default_pwmtrans;
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uint16_t default_pwmmargin;
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uint32_t ref_min;
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uint32_t ref_max;
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uint16_t default_comb_comp;
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};
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struct DSL_profile {
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uint16_t vid;
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uint16_t pid;
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2019-11-03 18:21:46 -08:00
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enum libusb_speed usb_speed;
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2019-09-09 00:07:19 -07:00
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const char *vendor;
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const char *model;
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const char *model_version;
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const char *firmware;
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const char *fpga_bit33;
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const char *fpga_bit50;
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struct DSL_caps dev_caps;
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};
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static const uint64_t vdivs10to2000[] = {
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SR_mV(10),
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SR_mV(20),
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SR_mV(50),
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SR_mV(100),
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SR_mV(200),
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SR_mV(500),
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SR_V(1),
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SR_V(2),
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0,
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};
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static const uint64_t samplerates100[] = {
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SR_HZ(10),
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SR_HZ(20),
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SR_HZ(50),
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SR_HZ(100),
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SR_HZ(200),
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SR_HZ(500),
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SR_KHZ(1),
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SR_KHZ(2),
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SR_KHZ(5),
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SR_KHZ(10),
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SR_KHZ(20),
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SR_KHZ(40),
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SR_KHZ(50),
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SR_KHZ(100),
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SR_KHZ(200),
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SR_KHZ(400),
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SR_KHZ(500),
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SR_MHZ(1),
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SR_MHZ(2),
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SR_MHZ(4),
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SR_MHZ(5),
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SR_MHZ(10),
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SR_MHZ(20),
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SR_MHZ(25),
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SR_MHZ(50),
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SR_MHZ(100),
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0,
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};
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static const uint64_t samplerates400[] = {
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SR_HZ(10),
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SR_HZ(20),
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SR_HZ(50),
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SR_HZ(100),
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SR_HZ(200),
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SR_HZ(500),
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SR_KHZ(1),
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SR_KHZ(2),
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SR_KHZ(5),
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SR_KHZ(10),
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SR_KHZ(20),
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SR_KHZ(40),
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SR_KHZ(50),
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SR_KHZ(100),
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SR_KHZ(200),
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SR_KHZ(400),
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SR_KHZ(500),
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SR_MHZ(1),
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SR_MHZ(2),
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SR_MHZ(4),
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SR_MHZ(5),
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SR_MHZ(10),
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SR_MHZ(20),
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SR_MHZ(25),
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SR_MHZ(50),
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SR_MHZ(100),
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SR_MHZ(200),
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SR_MHZ(400),
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0,
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};
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static const uint64_t samplerates1000[] = {
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SR_HZ(10),
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SR_HZ(20),
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SR_HZ(50),
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SR_HZ(100),
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SR_HZ(200),
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SR_HZ(500),
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SR_KHZ(1),
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SR_KHZ(2),
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SR_KHZ(5),
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SR_KHZ(10),
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SR_KHZ(20),
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SR_KHZ(40),
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SR_KHZ(50),
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SR_KHZ(100),
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SR_KHZ(200),
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SR_KHZ(400),
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SR_KHZ(500),
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SR_MHZ(1),
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SR_MHZ(2),
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SR_MHZ(4),
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SR_MHZ(5),
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SR_MHZ(10),
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SR_MHZ(20),
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SR_MHZ(25),
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SR_MHZ(50),
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SR_MHZ(100),
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SR_MHZ(125),
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SR_MHZ(250),
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SR_MHZ(500),
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SR_GHZ(1),
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0,
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};
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struct DSL_vga {
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uint8_t id;
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uint64_t key;
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uint64_t vgain;
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uint16_t preoff;
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uint16_t preoff_comp;
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};
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static const struct DSL_vga vga_defaults[] = {
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{1, 10, 0x162400, (32<<10)+558, (32<<10)+558},
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{1, 20, 0x14C000, (32<<10)+558, (32<<10)+558},
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{1, 50, 0x12E800, (32<<10)+558, (32<<10)+558},
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{1, 100, 0x118000, (32<<10)+558, (32<<10)+558},
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{1, 200, 0x102400, (32<<10)+558, (32<<10)+558},
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{1, 500, 0x2E800, (32<<10)+558, (32<<10)+558},
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{1, 1000, 0x18000, (32<<10)+558, (32<<10)+558},
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{1, 2000, 0x02400, (32<<10)+558, (32<<10)+558},
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{2, 10, 0x1DA800, 45, 1024-920-45},
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{2, 20, 0x1A7200, 45, 1024-920-45},
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{2, 50, 0x164200, 45, 1024-920-45},
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{2, 100, 0x131800, 45, 1024-920-45},
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{2, 200, 0xBD000, 45, 1024-920-45},
|
|
|
|
|
{2, 500, 0x7AD00, 45, 1024-920-45},
|
|
|
|
|
{2, 1000, 0x48800, 45, 1024-920-45},
|
|
|
|
|
{2, 2000, 0x12000, 45, 1024-920-45},
|
|
|
|
|
|
|
|
|
|
{3, 10, 0x1C5C00, 45, 1024-920-45},
|
|
|
|
|
{3, 20, 0x19EB00, 45, 1024-920-45},
|
|
|
|
|
{3, 50, 0x16AE00, 45, 1024-920-45},
|
|
|
|
|
{3, 100, 0x143D00, 45, 1024-920-45},
|
|
|
|
|
{3, 200, 0xB1000, 45, 1024-920-45},
|
|
|
|
|
{3, 500, 0x7F000, 45, 1024-920-45},
|
|
|
|
|
{3, 1000, 0x57200, 45, 1024-920-45},
|
|
|
|
|
{3, 2000, 0x2DD00, 45, 1024-920-45},
|
|
|
|
|
|
|
|
|
|
{4, 10, 0x1C6C00, 45, 1024-945-45},
|
|
|
|
|
{4, 20, 0x19E000, 45, 1024-945-45},
|
|
|
|
|
{4, 50, 0x16A800, 45, 1024-945-45},
|
|
|
|
|
{4, 100, 0x142800, 45, 1024-945-45},
|
|
|
|
|
{4, 200, 0xC7F00, 45, 1024-945-45},
|
|
|
|
|
{4, 500, 0x94000, 45, 1024-945-45},
|
|
|
|
|
{4, 1000, 0x6CF00, 45, 1024-945-45},
|
|
|
|
|
{4, 2000, 0x44F00, 45, 1024-945-45},
|
|
|
|
|
|
|
|
|
|
{0, 0, 0, 0, 0}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
enum CHANNEL_ID {
|
|
|
|
|
DSL_STREAM20x16 = 0,
|
|
|
|
|
DSL_STREAM25x12,
|
|
|
|
|
DSL_STREAM50x6,
|
|
|
|
|
DSL_STREAM100x3,
|
|
|
|
|
DSL_STREAM100x16,
|
|
|
|
|
DSL_STREAM125x16,
|
|
|
|
|
DSL_STREAM250x12,
|
|
|
|
|
DSL_STREAM500x6,
|
|
|
|
|
DSL_STREAM1000x3,
|
|
|
|
|
|
|
|
|
|
DSL_BUFFER100x16,
|
|
|
|
|
DSL_BUFFER200x8,
|
|
|
|
|
DSL_BUFFER400x4,
|
|
|
|
|
DSL_BUFFER500x16,
|
|
|
|
|
DSL_BUFFER1000x8,
|
|
|
|
|
|
|
|
|
|
DSL_ANALOG10x2,
|
|
|
|
|
|
|
|
|
|
DSL_DSO200x2,
|
|
|
|
|
DSL_DSO1000x2,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct DSL_channels {
|
|
|
|
|
enum CHANNEL_ID id;
|
|
|
|
|
enum OPERATION_MODE mode;
|
|
|
|
|
enum CHANNEL_TYPE type;
|
|
|
|
|
gboolean stream;
|
|
|
|
|
uint16_t num;
|
|
|
|
|
uint16_t vld_num;
|
|
|
|
|
uint8_t unit_bits;
|
|
|
|
|
uint64_t min_samplerate;
|
|
|
|
|
uint64_t max_samplerate;
|
|
|
|
|
uint64_t hw_min_samplerate;
|
|
|
|
|
uint64_t hw_max_samplerate;
|
|
|
|
|
uint8_t pre_div;
|
|
|
|
|
const char *descr;
|
|
|
|
|
const char *descr_cn;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct DSL_channels channel_modes[] = {
|
|
|
|
|
// LA Stream
|
|
|
|
|
{DSL_STREAM20x16, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 16, 1, SR_KHZ(10), SR_MHZ(20),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(100), 1, "Use 16 Channels (Max 20MHz)", "使用16个通道(最大采样率 20MHz)"},
|
|
|
|
|
{DSL_STREAM25x12, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 12, 1, SR_KHZ(10), SR_MHZ(25),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(100), 1, "Use 12 Channels (Max 25MHz)", "使用12个通道(最大采样率 25MHz)"},
|
|
|
|
|
{DSL_STREAM50x6, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 6, 1, SR_KHZ(10), SR_MHZ(50),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(100), 1, "Use 6 Channels (Max 50MHz)", "使用6个通道(最大采样率 50MHz)"},
|
|
|
|
|
{DSL_STREAM100x3, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 3, 1, SR_KHZ(10), SR_MHZ(100),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(100), 1, "Use 3 Channels (Max 100MHz)", "使用3个通道(最大采样率 100MHz)"},
|
|
|
|
|
{DSL_STREAM100x16, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 16, 1, SR_KHZ(10), SR_MHZ(100),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(500), 5, "Use 16 Channels (Max 100MHz)", "使用16个通道(最大采样率 100MHz)"},
|
|
|
|
|
{DSL_STREAM125x16, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 16, 1, SR_KHZ(10), SR_MHZ(125),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(500), 5, "Use 16 Channels (Max 125MHz)", "使用16个通道(最大采样率 125MHz)"},
|
|
|
|
|
{DSL_STREAM250x12, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 12, 1, SR_KHZ(10), SR_MHZ(250),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(500), 5, "Use 12 Channels (Max 250MHz)", "使用12个通道(最大采样率 250MHz)"},
|
|
|
|
|
{DSL_STREAM500x6, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 6, 1, SR_KHZ(10), SR_MHZ(500),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(500), 5, "Use 6 Channels (Max 500MHz)", "使用6个通道(最大采样率 500MHz)"},
|
|
|
|
|
{DSL_STREAM1000x3, LOGIC, SR_CHANNEL_LOGIC, TRUE, 16, 3, 1, SR_KHZ(10), SR_GHZ(1),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(500), 5, "Use 3 Channels (Max 1GHz)", "使用3个通道(最大采样率 1GHz)"},
|
|
|
|
|
|
|
|
|
|
// LA Buffer
|
|
|
|
|
{DSL_BUFFER100x16, LOGIC, SR_CHANNEL_LOGIC, FALSE, 16, 16, 1, SR_KHZ(10), SR_MHZ(100),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(100), 1, "Use Channels 0~15 (Max 100MHz)", "使用通道 0~15 (最大采样率 100MHz)"},
|
|
|
|
|
{DSL_BUFFER200x8, LOGIC, SR_CHANNEL_LOGIC, FALSE, 8, 8, 1, SR_KHZ(10), SR_MHZ(200),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(100), 1, "Use Channels 0~7 (Max 200MHz)", "使用通道 0~7 (最大采样率 200MHz)"},
|
|
|
|
|
{DSL_BUFFER400x4, LOGIC, SR_CHANNEL_LOGIC, FALSE, 4, 4, 1, SR_KHZ(10), SR_MHZ(400),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(100), 1, "Use Channels 0~3 (Max 400MHz)", "使用通道 0~3 (最大采样率 400MHz)"},
|
|
|
|
|
{DSL_BUFFER500x16, LOGIC, SR_CHANNEL_LOGIC, FALSE, 16, 16, 1, SR_KHZ(10), SR_MHZ(500),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(500), 5, "Use Channels 0~15 (Max 500MHz)", "使用通道 0~15 (最大采样率 500MHz)"},
|
|
|
|
|
{DSL_BUFFER1000x8, LOGIC, SR_CHANNEL_LOGIC, FALSE, 8, 8, 1, SR_KHZ(10), SR_GHZ(1),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(500), 5, "Use Channels 0~7 (Max 1GHz)", "使用通道 0~7 (最大采样率 1GHz)"},
|
|
|
|
|
|
|
|
|
|
// DAQ
|
|
|
|
|
{DSL_ANALOG10x2, ANALOG, SR_CHANNEL_ANALOG, TRUE, 2, 2, 8, SR_HZ(10), SR_MHZ(10),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(100), 1, "Use Channels 0~1 (Max 10MHz)", "使用通道 0~1 (最大采样率 10MHz)"},
|
|
|
|
|
|
|
|
|
|
// OSC
|
|
|
|
|
{DSL_DSO200x2, DSO, SR_CHANNEL_DSO, FALSE, 2, 2, 8, SR_KHZ(10), SR_MHZ(200),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(100), 1, "Use Channels 0~1 (Max 200MHz)", "使用通道 0~1 (最大采样率 200MHz)"},
|
|
|
|
|
{DSL_DSO1000x2, DSO, SR_CHANNEL_DSO, FALSE, 2, 2, 8, SR_KHZ(10), SR_GHZ(1),
|
|
|
|
|
SR_KHZ(10), SR_MHZ(100), 1, "Use Channels 0~1 (Max 1GHz)", "使用通道 0~1 (最大采样率 1GHz)"}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct DSL_profile supported_DSLogic[] = {
|
|
|
|
|
/*
|
|
|
|
|
* DSLogic
|
|
|
|
|
*/
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0001, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSLogic.fw",
|
|
|
|
|
"DSLogic33.bin",
|
|
|
|
|
"DSLogic50.bin",
|
|
|
|
|
{CAPS_MODE_LOGIC,
|
|
|
|
|
CAPS_FEATURE_SEEP | CAPS_FEATURE_BUF,
|
|
|
|
|
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
|
|
|
|
|
(1 << DSL_BUFFER100x16) | (1 << DSL_BUFFER200x8) | (1 << DSL_BUFFER400x4) |
|
|
|
|
|
(1 << DSL_ANALOG10x2) |
|
|
|
|
|
(1 << DSL_DSO200x2),
|
|
|
|
|
SR_MB(256),
|
|
|
|
|
SR_Mn(2),
|
|
|
|
|
DSL_BUFFER100x16,
|
|
|
|
|
vdivs10to2000,
|
|
|
|
|
samplerates400,
|
|
|
|
|
0,
|
|
|
|
|
DSL_STREAM20x16,
|
|
|
|
|
SR_MHZ(1),
|
|
|
|
|
SR_Mn(1),
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0}
|
|
|
|
|
},
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0003, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic Pro", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSLogicPro.fw",
|
|
|
|
|
"DSLogicPro.bin",
|
|
|
|
|
"DSLogicPro.bin",
|
|
|
|
|
{CAPS_MODE_LOGIC,
|
|
|
|
|
CAPS_FEATURE_SEEP | CAPS_FEATURE_VTH | CAPS_FEATURE_BUF,
|
|
|
|
|
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
|
|
|
|
|
(1 << DSL_BUFFER100x16) | (1 << DSL_BUFFER200x8) | (1 << DSL_BUFFER400x4),
|
|
|
|
|
SR_MB(256),
|
|
|
|
|
0,
|
|
|
|
|
DSL_BUFFER100x16,
|
|
|
|
|
0,
|
|
|
|
|
samplerates400,
|
|
|
|
|
0,
|
|
|
|
|
DSL_STREAM20x16,
|
|
|
|
|
SR_MHZ(1),
|
|
|
|
|
SR_Mn(1),
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0}
|
|
|
|
|
},
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0020, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic PLus", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSLogicPlus.fw",
|
|
|
|
|
"DSLogicPlus.bin",
|
|
|
|
|
"DSLogicPlus.bin",
|
|
|
|
|
{CAPS_MODE_LOGIC,
|
|
|
|
|
CAPS_FEATURE_VTH | CAPS_FEATURE_BUF,
|
|
|
|
|
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
|
|
|
|
|
(1 << DSL_BUFFER100x16) | (1 << DSL_BUFFER200x8) | (1 << DSL_BUFFER400x4),
|
|
|
|
|
SR_MB(256),
|
|
|
|
|
0,
|
|
|
|
|
DSL_BUFFER100x16,
|
|
|
|
|
0,
|
|
|
|
|
samplerates400,
|
|
|
|
|
0,
|
|
|
|
|
DSL_STREAM20x16,
|
|
|
|
|
SR_MHZ(1),
|
|
|
|
|
SR_Mn(1),
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0}
|
|
|
|
|
},
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0021, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic Basic", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSLogicBasic.fw",
|
|
|
|
|
"DSLogicBasic.bin",
|
|
|
|
|
"DSLogicBasic.bin",
|
|
|
|
|
{CAPS_MODE_LOGIC,
|
|
|
|
|
CAPS_FEATURE_VTH,
|
|
|
|
|
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
|
|
|
|
|
(1 << DSL_BUFFER100x16) | (1 << DSL_BUFFER200x8) | (1 << DSL_BUFFER400x4),
|
|
|
|
|
SR_KB(256),
|
|
|
|
|
0,
|
|
|
|
|
DSL_STREAM20x16,
|
|
|
|
|
0,
|
|
|
|
|
samplerates400,
|
|
|
|
|
0,
|
|
|
|
|
DSL_STREAM20x16,
|
|
|
|
|
SR_MHZ(1),
|
|
|
|
|
SR_Mn(1),
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0}
|
|
|
|
|
},
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0029, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic U2Basic", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSLogicU2Basic.fw",
|
|
|
|
|
"DSLogicU2Basic.bin",
|
|
|
|
|
"DSLogicU2Basic.bin",
|
|
|
|
|
{CAPS_MODE_LOGIC,
|
2019-09-15 04:53:45 -07:00
|
|
|
CAPS_FEATURE_VTH | CAPS_FEATURE_BUF,
|
2019-09-09 00:07:19 -07:00
|
|
|
(1 << DSL_STREAM20x16) | (1 << DSL_STREAM25x12) | (1 << DSL_STREAM50x6) | (1 << DSL_STREAM100x3) |
|
|
|
|
|
(1 << DSL_BUFFER100x16),
|
|
|
|
|
SR_MB(64),
|
|
|
|
|
0,
|
2019-09-15 04:53:45 -07:00
|
|
|
DSL_BUFFER100x16,
|
2019-09-09 00:07:19 -07:00
|
|
|
0,
|
|
|
|
|
samplerates100,
|
|
|
|
|
0,
|
|
|
|
|
DSL_STREAM20x16,
|
|
|
|
|
SR_MHZ(1),
|
|
|
|
|
SR_Mn(1),
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0}
|
|
|
|
|
},
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
|
2019-09-09 00:07:19 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct DSL_profile supported_DSCope[] = {
|
|
|
|
|
/*
|
|
|
|
|
* DSCope
|
|
|
|
|
*/
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0002, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSCope.fw",
|
|
|
|
|
"DSCope.bin",
|
|
|
|
|
"DSCope.bin",
|
|
|
|
|
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
|
|
|
|
|
CAPS_FEATURE_ZERO | CAPS_FEATURE_PREOFF | CAPS_FEATURE_SEEP | CAPS_FEATURE_BUF,
|
|
|
|
|
(1 << DSL_ANALOG10x2) |
|
|
|
|
|
(1 << DSL_DSO200x2),
|
|
|
|
|
SR_MB(256),
|
|
|
|
|
SR_Mn(2),
|
|
|
|
|
0,
|
|
|
|
|
vdivs10to2000,
|
|
|
|
|
samplerates400,
|
|
|
|
|
1,
|
|
|
|
|
DSL_DSO200x2,
|
|
|
|
|
SR_MHZ(100),
|
|
|
|
|
SR_Mn(1),
|
|
|
|
|
(129<<8)+167,
|
|
|
|
|
1024-920,
|
|
|
|
|
1,
|
|
|
|
|
255,
|
|
|
|
|
0}
|
|
|
|
|
},
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0004, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope20", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSCope20.fw",
|
|
|
|
|
"DSCope20.bin",
|
|
|
|
|
"DSCope20.bin",
|
|
|
|
|
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
|
|
|
|
|
CAPS_FEATURE_ZERO | CAPS_FEATURE_SEEP | CAPS_FEATURE_BUF,
|
|
|
|
|
(1 << DSL_ANALOG10x2) |
|
|
|
|
|
(1 << DSL_DSO200x2),
|
|
|
|
|
SR_MB(256),
|
|
|
|
|
SR_Mn(2),
|
|
|
|
|
0,
|
|
|
|
|
vdivs10to2000,
|
|
|
|
|
samplerates400,
|
|
|
|
|
2,
|
|
|
|
|
DSL_DSO200x2,
|
|
|
|
|
SR_MHZ(100),
|
|
|
|
|
SR_Mn(1),
|
|
|
|
|
920,
|
|
|
|
|
1024-920,
|
|
|
|
|
1,
|
|
|
|
|
255,
|
|
|
|
|
0}
|
|
|
|
|
},
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0022, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope B20", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSCopeB20.fw",
|
|
|
|
|
"DSCope20.bin",
|
|
|
|
|
"DSCope20.bin",
|
|
|
|
|
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
|
|
|
|
|
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF,
|
|
|
|
|
(1 << DSL_ANALOG10x2) |
|
|
|
|
|
(1 << DSL_DSO200x2),
|
|
|
|
|
SR_MB(256),
|
|
|
|
|
SR_Mn(2),
|
|
|
|
|
0,
|
|
|
|
|
vdivs10to2000,
|
|
|
|
|
samplerates400,
|
|
|
|
|
2,
|
|
|
|
|
DSL_DSO200x2,
|
|
|
|
|
SR_MHZ(100),
|
|
|
|
|
SR_Mn(1),
|
|
|
|
|
920,
|
|
|
|
|
1024-920,
|
|
|
|
|
1,
|
|
|
|
|
255,
|
|
|
|
|
0}
|
|
|
|
|
},
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0023, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope C20", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSCopeC20.fw",
|
|
|
|
|
"DSCopeC20P.bin",
|
|
|
|
|
"DSCopeC20P.bin",
|
|
|
|
|
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
|
|
|
|
|
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF,
|
|
|
|
|
(1 << DSL_ANALOG10x2) |
|
|
|
|
|
(1 << DSL_DSO200x2),
|
|
|
|
|
SR_MB(256),
|
|
|
|
|
SR_Mn(2),
|
|
|
|
|
0,
|
|
|
|
|
vdivs10to2000,
|
|
|
|
|
samplerates400,
|
|
|
|
|
3,
|
|
|
|
|
DSL_DSO200x2,
|
|
|
|
|
SR_MHZ(100),
|
|
|
|
|
SR_Mn(1),
|
|
|
|
|
920,
|
|
|
|
|
1024-920,
|
|
|
|
|
1,
|
|
|
|
|
255,
|
|
|
|
|
0}
|
|
|
|
|
},
|
|
|
|
|
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0024, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope C20P", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSCopeC20P.fw",
|
|
|
|
|
"DSCopeC20P.bin",
|
|
|
|
|
"DSCopeC20P.bin",
|
|
|
|
|
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
|
|
|
|
|
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF | CAPS_FEATURE_POGOPIN,
|
|
|
|
|
(1 << DSL_ANALOG10x2) |
|
|
|
|
|
(1 << DSL_DSO200x2),
|
|
|
|
|
SR_MB(256),
|
|
|
|
|
SR_Mn(2),
|
|
|
|
|
0,
|
|
|
|
|
vdivs10to2000,
|
|
|
|
|
samplerates400,
|
|
|
|
|
3,
|
|
|
|
|
DSL_DSO200x2,
|
|
|
|
|
SR_MHZ(100),
|
|
|
|
|
SR_Mn(1),
|
|
|
|
|
920,
|
|
|
|
|
1024-920,
|
|
|
|
|
1,
|
|
|
|
|
255,
|
|
|
|
|
0}
|
|
|
|
|
},
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0025, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope C20", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSCopeC20B.fw",
|
|
|
|
|
"DSCopeC20B.bin",
|
|
|
|
|
"DSCopeC20B.bin",
|
|
|
|
|
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
|
|
|
|
|
CAPS_FEATURE_ZERO,
|
|
|
|
|
(1 << DSL_ANALOG10x2) |
|
|
|
|
|
(1 << DSL_DSO200x2),
|
|
|
|
|
SR_KB(256),
|
|
|
|
|
SR_Kn(20),
|
|
|
|
|
0,
|
|
|
|
|
vdivs10to2000,
|
|
|
|
|
samplerates400,
|
|
|
|
|
3,
|
|
|
|
|
DSL_DSO200x2,
|
|
|
|
|
SR_MHZ(100),
|
|
|
|
|
SR_Kn(10),
|
|
|
|
|
920,
|
|
|
|
|
1024-920,
|
|
|
|
|
1,
|
|
|
|
|
255,
|
|
|
|
|
0}
|
|
|
|
|
},
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0026, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope U2B20", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSCopeU2B20.fw",
|
|
|
|
|
"DSCopeU2B20.bin",
|
|
|
|
|
"DSCopeU2B20.bin",
|
|
|
|
|
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
|
|
|
|
|
CAPS_FEATURE_ZERO,
|
|
|
|
|
(1 << DSL_ANALOG10x2) |
|
|
|
|
|
(1 << DSL_DSO200x2),
|
|
|
|
|
SR_KB(256),
|
|
|
|
|
SR_Kn(20),
|
|
|
|
|
0,
|
|
|
|
|
vdivs10to2000,
|
|
|
|
|
samplerates400,
|
|
|
|
|
4,
|
|
|
|
|
DSL_DSO200x2,
|
|
|
|
|
SR_MHZ(100),
|
|
|
|
|
SR_Kn(10),
|
|
|
|
|
945,
|
|
|
|
|
1024-945,
|
|
|
|
|
10,
|
|
|
|
|
245,
|
|
|
|
|
22}
|
|
|
|
|
},
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{0x2A0E, 0x0027, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSCope U2P20", NULL,
|
2019-09-09 00:07:19 -07:00
|
|
|
"DSCopeU2P20.fw",
|
|
|
|
|
"DSCopeU2P20.bin",
|
|
|
|
|
"DSCopeU2P20.bin",
|
|
|
|
|
{CAPS_MODE_ANALOG | CAPS_MODE_DSO,
|
|
|
|
|
CAPS_FEATURE_ZERO | CAPS_FEATURE_BUF | CAPS_FEATURE_POGOPIN,
|
|
|
|
|
(1 << DSL_ANALOG10x2) |
|
|
|
|
|
(1 << DSL_DSO200x2),
|
|
|
|
|
SR_MB(256),
|
|
|
|
|
SR_Mn(2),
|
|
|
|
|
0,
|
|
|
|
|
vdivs10to2000,
|
|
|
|
|
samplerates400,
|
|
|
|
|
4,
|
|
|
|
|
DSL_DSO200x2,
|
|
|
|
|
SR_MHZ(100),
|
|
|
|
|
SR_Mn(1),
|
|
|
|
|
945,
|
|
|
|
|
1024-945,
|
|
|
|
|
10,
|
|
|
|
|
245,
|
|
|
|
|
22}
|
|
|
|
|
},
|
|
|
|
|
|
|
|
|
|
|
2019-11-03 18:21:46 -08:00
|
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
|
2019-09-09 00:07:19 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const gboolean default_ms_en[] = {
|
|
|
|
|
FALSE, /* DSO_MS_BEGIN */
|
|
|
|
|
TRUE, /* DSO_MS_FREQ */
|
|
|
|
|
FALSE, /* DSO_MS_PERD */
|
|
|
|
|
TRUE, /* DSO_MS_VMAX */
|
|
|
|
|
TRUE, /* DSO_MS_VMIN */
|
|
|
|
|
FALSE, /* DSO_MS_VRMS */
|
|
|
|
|
FALSE, /* DSO_MS_VMEA */
|
|
|
|
|
FALSE, /* DSO_MS_VP2P */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
enum {
|
|
|
|
|
DSL_ERROR = -1,
|
|
|
|
|
DSL_INIT = 0,
|
|
|
|
|
DSL_START = 1,
|
|
|
|
|
DSL_READY = 2,
|
|
|
|
|
DSL_TRIGGERED = 3,
|
|
|
|
|
DSL_DATA = 4,
|
|
|
|
|
DSL_STOP = 5,
|
|
|
|
|
DSL_FINISH = 7,
|
|
|
|
|
DSL_ABORT = 8,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct DSL_context {
|
|
|
|
|
const struct DSL_profile *profile;
|
|
|
|
|
/*
|
|
|
|
|
* Since we can't keep track of an DSL device after upgrading
|
|
|
|
|
* the firmware (it renumerates into a different device address
|
|
|
|
|
* after the upgrade) this is like a global lock. No device will open
|
|
|
|
|
* until a proper delay after the last device was upgraded.
|
|
|
|
|
*/
|
|
|
|
|
int64_t fw_updated;
|
|
|
|
|
|
|
|
|
|
/* Device/capture settings */
|
|
|
|
|
uint64_t cur_samplerate;
|
|
|
|
|
uint64_t limit_samples;
|
|
|
|
|
uint64_t actual_samples;
|
|
|
|
|
uint64_t actual_bytes;
|
|
|
|
|
|
|
|
|
|
/* Operational settings */
|
|
|
|
|
gboolean clock_type;
|
|
|
|
|
gboolean clock_edge;
|
|
|
|
|
gboolean rle_mode;
|
|
|
|
|
gboolean rle_support;
|
|
|
|
|
gboolean instant;
|
|
|
|
|
uint16_t op_mode;
|
|
|
|
|
gboolean stream;
|
|
|
|
|
uint8_t test_mode;
|
|
|
|
|
uint16_t buf_options;
|
|
|
|
|
enum CHANNEL_ID ch_mode;
|
|
|
|
|
uint16_t samplerates_min_index;
|
|
|
|
|
uint16_t samplerates_max_index;
|
|
|
|
|
uint16_t th_level;
|
|
|
|
|
double vth;
|
|
|
|
|
uint16_t filter;
|
|
|
|
|
uint16_t trigger_mask[NUM_TRIGGER_STAGES];
|
|
|
|
|
uint16_t trigger_value[NUM_TRIGGER_STAGES];
|
|
|
|
|
int trigger_stage;
|
|
|
|
|
uint16_t trigger_buffer[NUM_TRIGGER_STAGES];
|
|
|
|
|
uint64_t timebase;
|
|
|
|
|
uint8_t max_height;
|
|
|
|
|
uint8_t trigger_channel;
|
|
|
|
|
uint8_t trigger_slope;
|
|
|
|
|
uint8_t trigger_source;
|
|
|
|
|
uint8_t trigger_hrate;
|
|
|
|
|
uint32_t trigger_hpos;
|
|
|
|
|
uint64_t trigger_holdoff;
|
|
|
|
|
uint8_t trigger_margin;
|
|
|
|
|
gboolean zero;
|
|
|
|
|
gboolean cali;
|
|
|
|
|
gboolean tune;
|
|
|
|
|
int16_t tune_index;
|
|
|
|
|
int zero_stage;
|
|
|
|
|
int zero_pcnt;
|
|
|
|
|
int tune_stage;
|
|
|
|
|
int tune_pcnt;
|
|
|
|
|
struct sr_channel *tune_probe;
|
|
|
|
|
gboolean roll;
|
|
|
|
|
gboolean data_lock;
|
|
|
|
|
uint16_t unit_pitch;
|
|
|
|
|
|
|
|
|
|
uint64_t num_samples;
|
|
|
|
|
uint64_t num_bytes;
|
|
|
|
|
int submitted_transfers;
|
|
|
|
|
int empty_transfer_count;
|
|
|
|
|
int instant_tail_bytes;
|
|
|
|
|
|
|
|
|
|
void *cb_data;
|
|
|
|
|
unsigned int num_transfers;
|
|
|
|
|
struct libusb_transfer **transfers;
|
|
|
|
|
int *usbfd;
|
|
|
|
|
|
|
|
|
|
int pipe_fds[2];
|
|
|
|
|
GIOChannel *channel;
|
|
|
|
|
|
|
|
|
|
int status;
|
|
|
|
|
int trf_completed;
|
|
|
|
|
gboolean mstatus_valid;
|
|
|
|
|
struct sr_status mstatus;
|
|
|
|
|
gboolean abort;
|
|
|
|
|
gboolean overflow;
|
|
|
|
|
int bw_limit;
|
|
|
|
|
|
|
|
|
|
int language;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* hardware setting for each capture
|
|
|
|
|
*/
|
|
|
|
|
struct DSL_setting {
|
|
|
|
|
uint32_t sync;
|
|
|
|
|
|
|
|
|
|
uint16_t mode_header; // 0
|
|
|
|
|
uint16_t mode;
|
|
|
|
|
uint16_t divider_header; // 1-2
|
|
|
|
|
uint16_t div_l;
|
|
|
|
|
uint16_t div_h;
|
|
|
|
|
uint16_t count_header; // 3-4
|
|
|
|
|
uint16_t cnt_l;
|
|
|
|
|
uint16_t cnt_h;
|
|
|
|
|
uint16_t trig_pos_header; // 5-6
|
|
|
|
|
uint16_t tpos_l;
|
|
|
|
|
uint16_t tpos_h;
|
|
|
|
|
uint16_t trig_glb_header; // 7
|
|
|
|
|
uint16_t trig_glb;
|
|
|
|
|
uint16_t ch_en_header; // 8
|
|
|
|
|
uint16_t ch_en;
|
|
|
|
|
uint16_t dso_count_header; // 9-10
|
|
|
|
|
uint16_t dso_cnt_l;
|
|
|
|
|
uint16_t dso_cnt_h;
|
|
|
|
|
uint16_t misc_align;
|
|
|
|
|
|
|
|
|
|
uint16_t trig_header; // 64
|
|
|
|
|
uint16_t trig_mask0[NUM_TRIGGER_STAGES];
|
|
|
|
|
uint16_t trig_mask1[NUM_TRIGGER_STAGES];
|
|
|
|
|
uint16_t trig_value0[NUM_TRIGGER_STAGES];
|
|
|
|
|
uint16_t trig_value1[NUM_TRIGGER_STAGES];
|
|
|
|
|
uint16_t trig_edge0[NUM_TRIGGER_STAGES];
|
|
|
|
|
uint16_t trig_edge1[NUM_TRIGGER_STAGES];
|
|
|
|
|
uint16_t trig_logic0[NUM_TRIGGER_STAGES];
|
|
|
|
|
uint16_t trig_logic1[NUM_TRIGGER_STAGES];
|
|
|
|
|
uint32_t trig_count[NUM_TRIGGER_STAGES];
|
|
|
|
|
|
|
|
|
|
uint32_t end_sync;
|
|
|
|
|
};
|
|
|
|
|
|
|
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struct DSL_adc_config {
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uint8_t dest;
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uint8_t cnt;
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uint8_t delay;
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uint8_t byte[4];
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};
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static const struct DSL_adc_config adc_single_ch0[] = {
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{ADCC_ADDR+1, 3, 0, {0x03, 0x01, 0x00, 0x00}}, // reset & power down
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{ADCC_ADDR, 4, 0, {0x00, 0x01, 0x00, 0x31}}, // 1x channel 1/1 clock
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{ADCC_ADDR+1, 1, 0, {0x01, 0x00, 0x00, 0x00}}, // power up
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{ADCC_ADDR, 4, 0, {0x00, 0x02, 0x02, 0x3A}}, // adc0: ch0 adc1: ch0
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{ADCC_ADDR, 4, 0, {0x00, 0x02, 0x02, 0x3B}}, // adc2: ch0 adc3: ch0
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{ADCC_ADDR, 4, 0, {0x00, 0x00, 0x00, 0x42}}, // phase_ddr: 270 deg
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{ADCC_ADDR, 4, 0, {0x00, 0x34, 0x00, 0x50}}, // adc core current: -40% (lower performance) / VCM: +-700uA
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{ADCC_ADDR, 4, 0, {0x00, 0x22, 0x02, 0x11}}, // lvds drive strength: 1.5mA(RSDS)
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{ADCC_ADDR, 4, 0, {0x00, 0x7F, 0x00, 0x24}}, // invert all channel
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{ADCC_ADDR, 4, 0, {0x00, 0x00, 0x00, 0x55}}, // full-scale range: -10%
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{ADCC_ADDR, 4, 0, {0x00, 0x02, 0x00, 0x33}}, // x-gain disabled / fine-gain enabled
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{ADCC_ADDR, 4, 0, {0x00, 0x00, 0x03, 0x2B}}, // coarse_gain: 3dB(1.4125x)
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{0, 0, 0, {0, 0, 0, 0}}
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};
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static const struct DSL_adc_config adc_single_ch3[] = {
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{ADCC_ADDR+1, 3, 0, {0x03, 0x01, 0x00, 0x00}}, // reset & power down
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{ADCC_ADDR, 4, 0, {0x00, 0x01, 0x00, 0x31}}, // 1x channel 1/1 clock
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{ADCC_ADDR+1, 1, 0, {0x01, 0x00, 0x00, 0x00}}, // power up
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{ADCC_ADDR, 4, 0, {0x00, 0x10, 0x10, 0x3A}}, // adc0: ch3 adc1: ch3
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{ADCC_ADDR, 4, 0, {0x00, 0x10, 0x10, 0x3B}}, // adc2: ch3 adc3: ch3
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{ADCC_ADDR, 4, 0, {0x00, 0x00, 0x00, 0x42}}, // phase_ddr: 270 deg
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{ADCC_ADDR, 4, 0, {0x00, 0x34, 0x00, 0x50}}, // adc core current: -40% (lower performance) / VCM: +-700uA
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{ADCC_ADDR, 4, 0, {0x00, 0x22, 0x02, 0x11}}, // lvds drive strength: 1.5mA(RSDS)
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{ADCC_ADDR, 4, 0, {0x00, 0x00, 0x00, 0x24}}, // invert none channel
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{ADCC_ADDR, 4, 0, {0x00, 0x00, 0x00, 0x55}}, // full-scale range: -10%
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{ADCC_ADDR, 4, 0, {0x00, 0x02, 0x00, 0x33}}, // x-gain disabled / fine-gain enabled
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{ADCC_ADDR, 4, 0, {0x00, 0x00, 0x03, 0x2B}}, // coarse_gain: 3dB(1.4125x)
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{0, 0, 0, {0, 0, 0, 0}}
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};
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static const struct DSL_adc_config adc_dual_ch03[] = {
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{ADCC_ADDR+1, 3, 0, {0x03, 0x01, 0x00, 0x00}}, // reset & power down
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{ADCC_ADDR, 4, 0, {0x00, 0x02, 0x01, 0x31}}, // 2x channel 1/2 clock
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{ADCC_ADDR+1, 1, 0, {0x01, 0x00, 0x00, 0x00}}, // power up
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{ADCC_ADDR, 4, 0, {0x00, 0x02, 0x02, 0x3A}}, // adc0: ch0 adc1: ch0
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{ADCC_ADDR, 4, 0, {0x00, 0x10, 0x10, 0x3B}}, // adc2: ch3 adc3: ch3
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{ADCC_ADDR, 4, 0, {0x00, 0x00, 0x00, 0x42}}, // phase_ddr: 270 deg
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{ADCC_ADDR, 4, 0, {0x00, 0x34, 0x00, 0x50}}, // adc core current: -40% (lower performance) / VCM: +-700uA
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{ADCC_ADDR, 4, 0, {0x00, 0x22, 0x02, 0x11}}, // lvds drive strength: 1.5mA(RSDS)
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{ADCC_ADDR, 4, 0, {0x00, 0x11, 0x00, 0x24}}, // invert 0 channel
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{ADCC_ADDR, 4, 0, {0x00, 0x00, 0x00, 0x55}}, // full-scale range: -10%
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{ADCC_ADDR, 4, 0, {0x00, 0x02, 0x00, 0x33}}, // x-gain disabled / fine-gain enabled
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{ADCC_ADDR, 4, 0, {0x00, 0x33, 0x00, 0x2B}}, // coarse_gain: 3dB(1.4125x)
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// {ADCC_ADDR, 4, 0, {0x00, 0x03, 0x00, 0x33}}, // x-gain enabled / fine-gain enabled
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// {ADCC_ADDR, 4, 0, {0x00, 0x11, 0x00, 0x2B}}, // coarse_gain: 1.25x
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//{ADCC_ADDR, 4, 0, {0x00, 0x40, 0x00, 0x34}}, // fine_gain: 1.0077x
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//{ADCC_ADDR, 4, 0, {0x00, 0x00, 0x60, 0x35}}, // fine_gain: 1.0077x
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//{ADCC_ADDR, 4, 0, {0x00, 0x10, 0x00, 0x25}}, // fix pattern test
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//{ADCC_ADDR, 4, 0, {0x00, 0x00, 0xab, 0x26}}, // test pattern
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{0, 0, 0, {0, 0, 0, 0}}
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};
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static const struct DSL_adc_config adc_init_fix[] = {
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{ADCC_ADDR+1, 3, 0, {0x03, 0x01, 0x00, 0x00}}, // reset & power down
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{ADCC_ADDR, 4, 0, {0x00, 0x02, 0x01, 0x31}}, // 2x channel 1/2 clock
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{ADCC_ADDR+1, 1, 0, {0x01, 0x00, 0x00, 0x00}}, // power up
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{ADCC_ADDR, 4, 0, {0x00, 0x02, 0x02, 0x3A}}, // adc0: ch0 adc1: ch0
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{ADCC_ADDR, 4, 0, {0x00, 0x10, 0x10, 0x3B}}, // adc2: ch3 adc3: ch3
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{ADCC_ADDR, 4, 0, {0x00, 0x00, 0x00, 0x42}}, // phase_ddr: 270 deg
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{ADCC_ADDR, 4, 0, {0x00, 0x34, 0x00, 0x50}}, // adc core current: -40% (lower performance) / VCM: +-700uA
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{ADCC_ADDR, 4, 0, {0x00, 0x22, 0x02, 0x11}}, // lvds drive strength: 1.5mA(RSDS)
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{ADCC_ADDR, 4, 0, {0x00, 0x10, 0x00, 0x25}}, // fix pattern test
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{ADCC_ADDR, 4, 0, {0x00, 0x00, 0x55, 0x26}}, // test pattern
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{0, 0, 0, {0, 0, 0, 0}}
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};
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static const struct DSL_adc_config adc_clk_init_1g[] = {
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{ADCC_ADDR+2, 1, 0, {0x01, 0x00, 0x00, 0x00}}, // power up
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{ADCC_ADDR, 4, 0, {0x01, 0x61, 0x00, 0x30}}, //
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{ADCC_ADDR, 4, 0, {0x01, 0x40, 0xF1, 0x46}}, //
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{ADCC_ADDR, 4, 10, {0x01, 0x62, 0x3D, 0x00}}, //
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{0, 0, 0, {0, 0, 0, 0}}
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};
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static const struct DSL_adc_config adc_clk_init_500m[] = {
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{ADCC_ADDR+2, 1, 0, {0x01, 0x00, 0x00, 0x00}}, // power up
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{ADCC_ADDR, 4, 0, {0x01, 0x61, 0x00, 0x30}}, //
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{ADCC_ADDR, 4, 0, {0x01, 0x40, 0xF1, 0x46}}, //
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{ADCC_ADDR, 4, 10, {0x01, 0x62, 0x3D, 0x40}}, //
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{0, 0, 0, {0, 0, 0, 0}}
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};
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static const struct DSL_adc_config adc_power_down[] = {
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//{ADCC_ADDR+2, 1, 0, {0x00, 0x00, 0x00, 0x00}}, // ADC_CLK power down
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{ADCC_ADDR+1, 1, 0, {0x00, 0x00, 0x00, 0x00}}, // ADC power down
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{0, 0, 0, {0, 0, 0, 0}}
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};
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static const struct DSL_adc_config adc_power_up[] = {
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{ADCC_ADDR+1, 1, 0, {0x01, 0x00, 0x00, 0x00}}, // ADC power up
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//{ADCC_ADDR+2, 1, 0, {0x01, 0x00, 0x00, 0x00}}, // ADC_CLK power up
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{0, 0, 0, {0, 0, 0, 0}}
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};
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SR_PRIV int dsl_adjust_probes(struct sr_dev_inst *sdi, int num_probes);
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SR_PRIV int dsl_setup_probes(struct sr_dev_inst *sdi, int num_probes);
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SR_PRIV const GSList *dsl_mode_list(const struct sr_dev_inst *sdi);
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SR_PRIV void dsl_adjust_samplerate(struct DSL_context *devc);
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SR_PRIV int dsl_en_ch_num(const struct sr_dev_inst *sdi);
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SR_PRIV gboolean dsl_check_conf_profile(libusb_device *dev);
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SR_PRIV int dsl_configure_probes(const struct sr_dev_inst *sdi);
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SR_PRIV uint64_t dsl_channel_depth(const struct sr_dev_inst *sdi);
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SR_PRIV int dsl_wr_reg(const struct sr_dev_inst *sdi, uint8_t addr, uint8_t value);
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SR_PRIV int dsl_rd_reg(const struct sr_dev_inst *sdi, uint8_t addr, uint8_t *value);
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SR_PRIV int dsl_wr_ext(const struct sr_dev_inst *sdi, uint8_t addr, uint8_t value);
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SR_PRIV int dsl_rd_ext(const struct sr_dev_inst *sdi, unsigned char *ctx, uint16_t addr, uint8_t len);
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SR_PRIV int dsl_wr_dso(const struct sr_dev_inst *sdi, uint64_t cmd);
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SR_PRIV int dsl_wr_nvm(const struct sr_dev_inst *sdi, unsigned char *ctx, uint16_t addr, uint8_t len);
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SR_PRIV int dsl_rd_nvm(const struct sr_dev_inst *sdi, unsigned char *ctx, uint16_t addr, uint8_t len);
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SR_PRIV int dsl_rd_probe(const struct sr_dev_inst *sdi, unsigned char *ctx, uint16_t addr, uint8_t len);
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SR_PRIV int dsl_config_adc(const struct sr_dev_inst *sdi, const struct DSL_adc_config *config);
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SR_PRIV int dsl_fpga_arm(const struct sr_dev_inst *sdi);
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SR_PRIV int dsl_fpga_config(struct libusb_device_handle *hdl, const char *filename);
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SR_PRIV int dsl_config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
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const struct sr_channel *ch,
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const struct sr_channel_group *cg);
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SR_PRIV int dsl_config_set(int id, GVariant *data, struct sr_dev_inst *sdi,
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struct sr_channel *ch,
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struct sr_channel_group *cg );
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SR_PRIV int dsl_config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
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const struct sr_channel_group *cg);
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SR_PRIV int dsl_dev_open(struct sr_dev_driver *di, struct sr_dev_inst *sdi, gboolean *fpga_done);
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SR_PRIV int dsl_dev_close(struct sr_dev_inst *sdi);
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SR_PRIV int dsl_dev_acquisition_stop(const struct sr_dev_inst *sdi, void *cb_data);
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SR_PRIV int dsl_dev_status_get(const struct sr_dev_inst *sdi, struct sr_status *status, gboolean prg, int begin, int end);
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SR_PRIV unsigned int dsl_get_timeout(const struct sr_dev_inst *sdi);
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SR_PRIV int dsl_start_transfers(const struct sr_dev_inst *sdi);
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SR_PRIV int dsl_header_size(const struct DSL_context *devc);
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#endif
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