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update: add a option for decoder wiegand

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This commit is contained in:
dreamsourcelabTAI 2022-06-08 16:31:16 +08:00
parent 7f7b51239b
commit 46a5f5000a
2 changed files with 31 additions and 3 deletions
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9
libsigrokdecode4DSL/decoders/common/srdhelper/mod.py
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@ -21,6 +21,15 @@ from enum import Enum, IntEnum, unique
from itertools import chain from itertools import chain
import re import re
#bits to int
def bits2int(bs):
n = len(bs)
v = 0
for i in range(n):
if bs[i] == 1 or bs[i] == '1':
v += 1 << (n - i - 1)
return v
# Return the specified BCD number (max. 8 bits) as integer. # Return the specified BCD number (max. 8 bits) as integer.
def bcd2int(b): def bcd2int(b):
return (b & 0x0f) + ((b >> 4) * 10) return (b & 0x0f) + ((b >> 4) * 10)

25
libsigrokdecode4DSL/decoders/wiegand/pd.py
View File

@ -18,6 +18,7 @@
## ##
import sigrokdecode as srd import sigrokdecode as srd
from common.srdhelper import bits2int
class SamplerateError(Exception): class SamplerateError(Exception):
pass pass
@ -41,6 +42,7 @@ class Decoder(srd.Decoder):
'default': 'low', 'values': ('low', 'high')}, 'default': 'low', 'values': ('low', 'high')},
{'id': 'bitwidth_ms', 'desc': 'Single bit width in milliseconds', {'id': 'bitwidth_ms', 'desc': 'Single bit width in milliseconds',
'default': 4, 'values': (1, 2, 4, 8, 16, 32)}, 'default': 4, 'values': (1, 2, 4, 8, 16, 32)},
{'id': 'bit-start', 'desc': 'Data bit start index', 'default': -1},
) )
annotations = ( annotations = (
('bits', 'Bits'), ('bits', 'Bits'),
@ -101,9 +103,26 @@ class Decoder(srd.Decoder):
if state != self._state: if state != self._state:
ann = None ann = None
if self._state == 'data': if self._state == 'data':
accum_bits = ''.join(str(x) for x in self._bits) #accum_bits = ''.join(str(x) for x in self._bits)
ann = [1, ['%d bits %s' % (len(self._bits), accum_bits), bstart = int(self.options['bit-start'])
'%d bits' % len(self._bits)]] bits = self._bits
blen = len(self._bits)
# get data block
if bstart != -1:
bits = []
while bstart + 4 <= blen:
bits.append(self._bits[bstart+0]);
bits.append(self._bits[bstart+1]);
bits.append(self._bits[bstart+2]);
bits.append(self._bits[bstart+3]);
bstart += 4
blen = len(bits)
s1 = '%d bits {$}' % blen
s2 = '%d bits' % blen
s3 = '@%02X' % (bits2int(bits))
ann = [1, [s1, s2, s3]]
elif self._state == 'invalid': elif self._state == 'invalid':
ann = [1, [self._state]] ann = [1, [self._state]]
if ann: if ann: