diff --git a/libsigrok4DSL/hardware/DSL/dscope.c b/libsigrok4DSL/hardware/DSL/dscope.c
index df1a2fbe..0adb5acc 100755
--- a/libsigrok4DSL/hardware/DSL/dscope.c
+++ b/libsigrok4DSL/hardware/DSL/dscope.c
@@ -419,8 +419,6 @@ static uint64_t dso_cmd_gen(const struct sr_dev_inst *sdi, struct sr_channel* ch
         cmd += ch->index << ch_bit;
         //  --VGAIN
         uint64_t vgain = dso_vga(ch);
-//        if ((devc->profile->dev_caps.feature_caps & CAPS_FEATURE_HMCAD1511) &&
-//            (dsl_en_ch_num(sdi) == 1))
         if ((ch->comb_comp != 0) && (dsl_en_ch_num(sdi) == 1))
             vgain += (uint64_t)(ch->comb_comp) << 8;
         cmd += vgain;
@@ -632,7 +630,7 @@ static int dso_zero(const struct sr_dev_inst *sdi, gboolean reset)
     if (devc->profile->dev_caps.feature_caps & CAPS_FEATURE_HMCAD1511)
         offset_top = 15;
     else
-        offset_top = 20;
+        offset_top = 30;
     const uint16_t offset_bom = ((1 << channel_modes[devc->ch_mode].unit_bits) - 1) - offset_top;
     const uint16_t offset_mid = (1 << (channel_modes[devc->ch_mode].unit_bits - 1));
     const uint16_t max_trans = ((1 << 10) - 1);
@@ -972,11 +970,12 @@ static int dso_zero(const struct sr_dev_inst *sdi, gboolean reset)
                             for (uint16_t j = 0; j < ARRAY_SIZE(vga_defaults); j++) {
                                 if (vga_defaults[j].id == devc->profile->dev_caps.vga_id &&
                                     vga_defaults[j].key == devc->profile->dev_caps.vdivs[i]) {
-                                    const int64_t vgain_delta = probe->vpos_trans > devc->profile->dev_caps.default_pwmtrans ?
-                                                ((int64_t)(probe->vpos_trans - devc->profile->dev_caps.default_pwmtrans) << 8) :
-                                                (((int64_t)(probe->vpos_trans - devc->profile->dev_caps.default_pwmtrans) << 7) & 0xFFFFFF00);
+                                    const int64_t cur_trans = probe->vpos_trans;
+                                    const int64_t def_trans = devc->profile->dev_caps.default_pwmtrans;
+                                    const int64_t vgain_delta = (cur_trans > def_trans) ? ((cur_trans - def_trans) << 8) :
+                                                                                          (((cur_trans - def_trans) << 7) & ~0xFFLL);
                                     (probe->vga_ptr+i)->vgain = vga_defaults[j].vgain + vgain_delta;
-                                    break;
+									break;
                                 }
                             }
                         }
diff --git a/libsigrok4DSL/hardware/DSL/dsl.h b/libsigrok4DSL/hardware/DSL/dsl.h
index 602c12f4..388acfe1 100755
--- a/libsigrok4DSL/hardware/DSL/dsl.h
+++ b/libsigrok4DSL/hardware/DSL/dsl.h
@@ -740,7 +740,7 @@ static const struct DSL_profile supported_DSLogic[] = {
       SR_GHZ(1)}
     },
 
-    { 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
+    { 0, 0, LIBUSB_SPEED_UNKNOWN, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
 };
 
 static const struct DSL_profile supported_DSCope[] = {
@@ -969,7 +969,7 @@ static const struct DSL_profile supported_DSCope[] = {
      "DSCopeU2B100.bin",
      "DSCopeU2B100.bin",
      {CAPS_MODE_ANALOG | CAPS_MODE_DSO,
-      CAPS_FEATURE_ZERO | CAPS_FEATURE_HMCAD1511 | CAPS_FEATURE_20M,
+      CAPS_FEATURE_ZERO  | CAPS_FEATURE_AUTO_VGAIN | CAPS_FEATURE_HMCAD1511 | CAPS_FEATURE_20M,
       (1 << DSL_ANALOG10x2_500) |
       (1 << DSL_DSO1000x2),
       2,
@@ -982,11 +982,11 @@ static const struct DSL_profile supported_DSCope[] = {
       DSL_DSO1000x2,
       SR_MHZ(500),
       SR_Kn(10),
-      850,
-      1024-850,
+      810,
+      1024-810,
       10,
       245,
-      80,
+      60,
       SR_HZ(0),
       SR_HZ(0)}
     },
@@ -996,7 +996,7 @@ static const struct DSL_profile supported_DSCope[] = {
      "DSCopeU3P100.bin",
      "DSCopeU3P100.bin",
      {CAPS_MODE_ANALOG | CAPS_MODE_DSO,
-      CAPS_FEATURE_ZERO | CAPS_FEATURE_FLASH | CAPS_FEATURE_USB30 | CAPS_FEATURE_HMCAD1511 | CAPS_FEATURE_20M,
+      CAPS_FEATURE_ZERO | CAPS_FEATURE_POGOPIN | CAPS_FEATURE_AUTO_VGAIN | CAPS_FEATURE_FLASH | CAPS_FEATURE_USB30 | CAPS_FEATURE_HMCAD1511 | CAPS_FEATURE_20M,
       (1 << DSL_ANALOG10x2_500) |
       (1 << DSL_DSO1000x2),
       2,
@@ -1009,8 +1009,8 @@ static const struct DSL_profile supported_DSCope[] = {
       DSL_DSO1000x2,
       SR_MHZ(500),
       SR_Mn(1),
-      900,
-      1024-900,
+      830,
+      1024-830,
       10,
       245,
       60,
@@ -1023,7 +1023,7 @@ static const struct DSL_profile supported_DSCope[] = {
      "DSCopeU3P100.bin",
      "DSCopeU3P100.bin",
      {CAPS_MODE_ANALOG | CAPS_MODE_DSO,
-      CAPS_FEATURE_ZERO | CAPS_FEATURE_FLASH | CAPS_FEATURE_USB30 | CAPS_FEATURE_HMCAD1511 | CAPS_FEATURE_20M,
+      CAPS_FEATURE_ZERO | CAPS_FEATURE_POGOPIN | CAPS_FEATURE_AUTO_VGAIN | CAPS_FEATURE_FLASH | CAPS_FEATURE_USB30 | CAPS_FEATURE_HMCAD1511 | CAPS_FEATURE_20M,
       (1 << DSL_ANALOG10x2_500) |
       (1 << DSL_DSO1000x2),
       2,
@@ -1036,8 +1036,8 @@ static const struct DSL_profile supported_DSCope[] = {
       DSL_DSO1000x2,
       SR_MHZ(500),
       SR_Mn(1),
-      900,
-      1024-900,
+      830,
+      1024-830,
       10,
       245,
       60,
@@ -1045,7 +1045,7 @@ static const struct DSL_profile supported_DSCope[] = {
       SR_HZ(0)}
     },
 
-    { 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
+    { 0, 0, LIBUSB_SPEED_UNKNOWN, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}
 };
 
 static const gboolean default_ms_en[] = {