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Add QSPI decoder #143
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libsigrokdecode4DSL/decoders/qspi/__init__.py
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libsigrokdecode4DSL/decoders/qspi/__init__.py
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##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2016 fenugrec <fenugrec users.sourceforge.net>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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'''
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This protocol decoder decodes the AUD (Advanced User Debugger) interface
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of certain Renesas / Hitachi microcontrollers, when set in Branch Trace mode.
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AUD has two modes, this PD currently only supports "Branch Trace" mode.
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Details:
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http://www.renesas.eu/products/mpumcu/superh/sh7050/sh7058/Documentation.jsp
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("rej09b0046 - SH7058 Hardware manual")
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'''
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from .pd import Decoder
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libsigrokdecode4DSL/decoders/qspi/pd.py
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libsigrokdecode4DSL/decoders/qspi/pd.py
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###
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2020 DreamSourceLab <support@dreamsourcelab.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sigrokdecode as srd
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from collections import namedtuple
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Data = namedtuple('Data', ['ss', 'es', 'val'])
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# Key: (CPOL, CPHA). Value: SPI mode.
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# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
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# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
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spi_mode = {
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(0, 0): 0, # Mode 0
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(0, 1): 1, # Mode 1
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(1, 0): 2, # Mode 2
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(1, 1): 3, # Mode 3
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}
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class ChannelError(Exception):
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pass
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'qspi'
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name = 'QSPI'
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longname = 'Quad Serial Peripheral Interface'
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desc = 'Full-duplex, synchronous, serial bus.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = ['spi']
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tags = ['Embedded/industrial']
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channels = (
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{'id': 'clk', 'type': 0, 'name': 'CLK', 'desc': 'Clock'},
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{'id': 'io0', 'type': 107, 'name': 'IO0', 'desc': 'Data i/o 0'},
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)
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optional_channels = (
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{'id': 'io1', 'type': 107, 'name': 'IO1', 'desc': 'Data i/o 1'},
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{'id': 'io2', 'type': 107, 'name': 'IO2', 'desc': 'Data i/o 2'},
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{'id': 'io3', 'type': 107, 'name': 'IO3', 'desc': 'Data i/o 3'},
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{'id': 'cs', 'type': -1, 'name': 'CS#', 'desc': 'Chip-select'},
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)
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options = (
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{'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low',
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'values': ('active-low', 'active-high')},
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{'id': 'cpol', 'desc': 'Clock polarity (CPOL)', 'default': 0,
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'values': (0, 1)},
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{'id': 'cpha', 'desc': 'Clock phase (CPHA)', 'default': 0,
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'values': (0, 1)},
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{'id': 'bitorder', 'desc': 'Bit order',
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'default': 'msb-first', 'values': ('msb-first', 'lsb-first')},
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{'id': 'wordsize', 'desc': 'Word size', 'default': 8},
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)
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annotations = (
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('106', 'data', 'data'),
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)
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annotation_rows = (
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('data', 'data', (0,)),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.samplerate = None
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self.bitcount = 0
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self.data = 0
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self.bits = []
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self.ss_block = -1
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self.samplenum = -1
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self.ss_transfer = -1
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self.cs_was_deasserted = False
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self.have_cs = self.have_io1 = self.have_io3 = None
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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self.bw = (self.options['wordsize'] + 7) // 8
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def metadata(self, key, value):
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if key == srd.SRD_CONF_SAMPLERATE:
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self.samplerate = value
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def putw(self, data):
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self.put(self.ss_block, self.samplenum, self.out_ann, data)
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def putdata(self):
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# Pass bits and then data to the next PD up the stack.
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ss, es = self.bits[-1][1], self.bits[0][2]
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# Dataword annotations.
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self.put(ss, es, self.out_ann, [0, ['%02X' % self.data]])
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def reset_decoder_state(self):
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self.data = 0
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self.bits = []
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self.bitcount = 0
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def cs_asserted(self, cs):
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active_low = (self.options['cs_polarity'] == 'active-low')
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return (cs == 0) if active_low else (cs == 1)
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def handle_bit(self, datapins, clk, cs):
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# If this is the first bit of a dataword, save its sample number.
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if self.bitcount == 0:
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self.ss_block = self.samplenum
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self.cs_was_deasserted = \
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not self.cs_asserted(cs) if self.have_cs else False
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bo = self.options['bitorder']
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ws = self.options['wordsize']
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if self.have_io3:
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nibws = ws >> 2
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elif self.have_io1:
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nibws = ws >> 1
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else:
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nibws = ws
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# Receive bit into our shift register.
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if self.have_io3:
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for i in range(4):
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if bo == 'msb-first':
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self.data |= datapins[i] << (ws - 1 - self.bitcount*4 - i)
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else:
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self.data |= datapins[3-i] << (self.bitcount*4 + i)
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elif self.have_io1:
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for i in range(2):
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if bo == 'msb-first':
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self.data |= datapins[i+2] << (ws - 1 - self.bitcount*2 - i)
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else:
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self.data |= datapins[3-i] << (self.bitcount*2 + i)
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else:
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if bo == 'msb-first':
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self.data |= datapins[3] << (ws - 1 - self.bitcount)
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else:
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self.data |= datapins[3] << self.bitcount
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# Guesstimate the endsample for this bit (can be overridden below).
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es = self.samplenum
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if self.bitcount > 0:
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es += self.samplenum - self.bits[0][1]
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self.bits.insert(0, [datapins[3], self.samplenum, es])
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if self.bitcount > 0:
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self.bits[1][2] = self.samplenum
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self.bitcount += 1
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# Continue to receive if not enough bits were received, yet.
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if self.bitcount != nibws:
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return
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self.putdata()
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self.reset_decoder_state()
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def find_clk_edge(self, datapins, clk, cs, first):
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if self.have_cs and (first or (self.matched & (0b1 << self.have_cs))):
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# Send all CS# pin value changes.
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oldcs = None if first else 1 - cs
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# Reset decoder state when CS# changes (and the CS# pin is used).
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self.reset_decoder_state()
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# We only care about samples if CS# is asserted.
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if self.have_cs and not self.cs_asserted(cs):
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return
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# Ignore sample if the clock pin hasn't changed.
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if first or not (self.matched & (0b1 << 0)):
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return
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# Found the correct clock edge, now get the SPI bit(s).
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self.handle_bit(datapins, clk, cs)
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def decode(self):
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# The CLK & IO0 input is mandatory. Other signals are (individually)
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# optional. Tell stacked decoders when we don't have a CS# signal.
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if not self.has_channel(0):
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raise ChannelError('CLK pin required.')
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self.have_io1 = self.has_channel(2)
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self.have_io3 = self.has_channel(3) & self.has_channel(4)
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self.have_cs = self.has_channel(5)
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# We want all CLK changes. We want all CS changes if CS is used.
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# Map 'have_cs' from boolean to an integer index. This simplifies
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# evaluation in other locations.
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# Sample data on rising/falling clock edge (depends on mode).
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mode = spi_mode[self.options['cpol'], self.options['cpha']]
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if mode == 0 or mode == 3: # Sample on rising clock edge
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wait_cond = [{0: 'r'}]
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else: # Sample on falling clock edge
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wait_cond = [{0: 'f'}]
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if self.have_cs:
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self.have_cs = len(wait_cond)
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wait_cond.append({5: 'e'})
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# "Pixel compatibility" with the v2 implementation. Grab and
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# process the very first sample before checking for edges. The
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# previous implementation did this by seeding old values with
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# None, which led to an immediate "change" in comparison.
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(clk, d0, d1, d2, d3, cs) = self.wait({})
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d = (d3, d2, d1, d0);
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self.find_clk_edge(d, clk, cs, True)
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while True:
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(clk, d0, d1, d2, d3, cs) = self.wait(wait_cond)
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d = (d3, d2, d1, d0);
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self.find_clk_edge(d, clk, cs, False)#
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