mirror of
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Add 'Microchip ENC28J60' decoder from libsigrokdecode
This commit is contained in:
Abdelhak Bougouffa
parent
24ae8658f1
commit
94c7b9fbdb
32
libsigrokdecode4DSL/decoders/enc28j60/__init__.py
Normal file
32
libsigrokdecode4DSL/decoders/enc28j60/__init__.py
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@ -0,0 +1,32 @@
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##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2019 Jiahao Li <reg@ljh.me>
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##
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## Permission is hereby granted, free of charge, to any person obtaining a copy
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## of this software and associated documentation files (the "Software"), to deal
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## in the Software without restriction, including without limitation the rights
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## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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## copies of the Software, and to permit persons to whom the Software is
|
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## furnished to do so, subject to the following conditions:
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##
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## The above copyright notice and this permission notice shall be included in all
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## copies or substantial portions of the Software.
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##
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## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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## SOFTWARE.
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'''
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This decoder stacks on top of the 'spi' PD and decodes the protocol spoken
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by the Microchip ENC28J60 Ethernet chip.
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Details:
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http://ww1.microchip.com/downloads/en/DeviceDoc/39662e.pdf
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'''
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from .pd import Decoder
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161
libsigrokdecode4DSL/decoders/enc28j60/lists.py
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161
libsigrokdecode4DSL/decoders/enc28j60/lists.py
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@ -0,0 +1,161 @@
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##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2019 Jiahao Li <reg@ljh.me>
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##
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## Permission is hereby granted, free of charge, to any person obtaining a copy
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## of this software and associated documentation files (the "Software"), to deal
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## in the Software without restriction, including without limitation the rights
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## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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## copies of the Software, and to permit persons to whom the Software is
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## furnished to do so, subject to the following conditions:
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##
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## The above copyright notice and this permission notice shall be included in all
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## copies or substantial portions of the Software.
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##
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## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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## SOFTWARE.
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REGS = [
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[
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'ERDPTL',
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'ERDPTH',
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'EWRPTL',
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'EWRPTH',
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'ETXSTL',
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'ETXSTH',
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'ETXNDL',
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'ETXNDH',
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'ERXSTL',
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'ERXSTH',
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'ERXNDL',
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'ERXNDH',
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'ERXRDPTL',
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'ERXRDPTH',
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'ERXWRPTL',
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'ERXWRPTH',
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'EDMASTL',
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'EDMASTH',
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'EDMANDL',
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'EDMANDH',
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'EDMADSTL',
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'EDMADSTH',
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'EDMACSL',
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'EDMACSH',
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'—',
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'—',
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'Reserved',
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'EIE',
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'EIR',
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'ESTAT',
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'ECON2',
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'ECON1',
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],
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[
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'EHT0',
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'EHT1',
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'EHT2',
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'EHT3',
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'EHT4',
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'EHT5',
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'EHT6',
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'EHT7',
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'EPMM0',
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'EPMM1',
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'EPMM2',
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'EPMM3',
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'EPMM4',
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'EPMM5',
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'EPMM6',
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'EPMM7',
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'EPMCSL',
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'EPMCSH',
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'—',
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'—',
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'EPMOL',
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'EPMOH',
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'Reserved',
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'Reserved',
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'ERXFCON',
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'EPKTCNT',
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'Reserved',
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'EIE',
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'EIR',
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'ESTAT',
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'ECON2',
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'ECON1',
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],
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[
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'MACON1',
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'Reserved',
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'MACON3',
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'MACON4',
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'MABBIPG',
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'—',
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'MAIPGL',
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'MAIPGH',
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'MACLCON1',
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'MACLCON2',
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'MAMXFLL',
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'MAMXFLH',
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'Reserved',
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'Reserved',
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'Reserved',
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'—',
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'Reserved',
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'Reserved',
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'MICMD',
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'—',
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'MIREGADR',
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'Reserved',
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'MIWRL',
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'MIWRH',
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'MIRDL',
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'MIRDH',
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'Reserved',
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'EIE',
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'EIR',
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'ESTAT',
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'ECON2',
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'ECON1',
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],
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[
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'MAADR5',
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'MAADR6',
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'MAADR3',
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'MAADR4',
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'MAADR1',
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'MAADR2',
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'EBSTSD',
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'EBSTCON',
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'EBSTCSL',
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'EBSTCSH',
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'MISTAT',
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'—',
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'—',
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'—',
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'—',
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'—',
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'—',
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'—',
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'EREVID',
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'—',
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'—',
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'ECOCON',
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'Reserved',
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'EFLOCON',
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'EPAUSL',
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'EPAUSH',
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'Reserved',
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'EIE',
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'EIR',
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'ESTAT',
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'ECON2',
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'ECON1',
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],
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]
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294
libsigrokdecode4DSL/decoders/enc28j60/pd.py
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294
libsigrokdecode4DSL/decoders/enc28j60/pd.py
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@ -0,0 +1,294 @@
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##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2019 Jiahao Li <reg@ljh.me>
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##
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## Permission is hereby granted, free of charge, to any person obtaining a copy
|
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## of this software and associated documentation files (the "Software"), to deal
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## in the Software without restriction, including without limitation the rights
|
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## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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## copies of the Software, and to permit persons to whom the Software is
|
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## furnished to do so, subject to the following conditions:
|
||||
##
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## The above copyright notice and this permission notice shall be included in all
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## copies or substantial portions of the Software.
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||||
##
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## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
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## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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## SOFTWARE.
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import sigrokdecode as srd
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from .lists import *
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OPCODE_MASK = 0b11100000
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REG_ADDR_MASK = 0b00011111
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OPCODE_HANDLERS = {
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0b00000000: '_process_rcr',
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0b00100000: '_process_rbm',
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0b01000000: '_process_wcr',
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0b01100000: '_process_wbm',
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0b10000000: '_process_bfs',
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0b10100000: '_process_bfc',
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0b11100000: '_process_src',
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}
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(ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC, ANN_DATA,
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ANN_REG_ADDR, ANN_WARNING) = range(10)
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REG_ADDR_ECON1 = 0x1F
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BIT_ECON1_BSEL0 = 0b00000001
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BIT_ECON1_BSEL1 = 0b00000010
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'enc28j60'
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name = 'ENC28J60'
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longname = 'Microchip ENC28J60'
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desc = 'Microchip ENC28J60 10Base-T Ethernet controller protocol.'
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license = 'mit'
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inputs = ['spi']
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outputs = []
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tags = ['Embedded/industrial', 'Networking']
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annotations = (
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('rcr', 'Read Control Register'),
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('rbm', 'Read Buffer Memory'),
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('wcr', 'Write Control Register'),
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('wbm', 'Write Buffer Memory'),
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('bfs', 'Bit Field Set'),
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('bfc', 'Bit Field Clear'),
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('src', 'System Reset Command'),
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('data', 'Data'),
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('reg-addr', 'Register Address'),
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('warning', 'Warning'),
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)
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annotation_rows = (
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('commands', 'Commands',
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(ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC)),
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('fields', 'Fields', (ANN_DATA, ANN_REG_ADDR)),
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('warnings', 'Warnings', (ANN_WARNING,)),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.mosi = []
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self.miso = []
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self.ranges = []
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self.cmd_ss = None
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self.cmd_es = None
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self.range_ss = None
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self.range_es = None
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self.active = False
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self.bsel0 = None
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self.bsel1 = None
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def putc(self, data):
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self.put(self.cmd_ss, self.cmd_es, self.out_ann, data)
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def putr(self, data):
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self.put(self.range_ss, self.range_es, self.out_ann, data)
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def _process_command(self):
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if len(self.mosi) == 0:
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self.active = False
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return
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header = self.mosi[0]
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opcode = header & OPCODE_MASK
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if opcode not in OPCODE_HANDLERS:
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self._put_command_warning("Unknown opcode.")
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self.active = False
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return
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getattr(self, OPCODE_HANDLERS[opcode])()
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self.active = False
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def _get_register_name(self, reg_addr):
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if (self.bsel0 is None) or (self.bsel1 is None):
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# We don't know the bank we're in yet.
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return None
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else:
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bank = (self.bsel1 << 1) + self.bsel0
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return REGS[bank][reg_addr]
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def _put_register_header(self):
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reg_addr = self.mosi[0] & REG_ADDR_MASK
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reg_name = self._get_register_name(reg_addr)
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self.range_ss, self.range_es = self.cmd_ss, self.ranges[1][0]
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if reg_name is None:
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# We don't know the bank we're in yet.
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self.putr([ANN_REG_ADDR, [
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'Reg Bank ? Addr 0x{0:02X}'.format(reg_addr),
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'?:{0:02X}'.format(reg_addr)]])
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self.putr([ANN_WARNING, ['Warning: Register bank not known yet.',
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'Warning']])
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else:
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self.putr([ANN_REG_ADDR, ['Reg {0}'.format(reg_name),
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'{0}'.format(reg_name)]])
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if (reg_name == '-') or (reg_name == 'Reserved'):
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self.putr([ANN_WARNING, ['Warning: Invalid register accessed.',
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'Warning']])
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def _put_data_byte(self, data, byte_index, binary=False):
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self.range_ss = self.ranges[byte_index][0]
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if byte_index == len(self.mosi) - 1:
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self.range_es = self.cmd_es
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else:
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self.range_es = self.ranges[byte_index + 1][0]
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if binary:
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self.putr([ANN_DATA, ['Data 0b{0:08b}'.format(data),
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'{0:08b}'.format(data)]])
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else:
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self.putr([ANN_DATA, ['Data 0x{0:02X}'.format(data),
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'{0:02X}'.format(data)]])
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def _put_command_warning(self, reason):
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self.putc([ANN_WARNING, ['Warning: {0}'.format(reason), 'Warning']])
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def _process_rcr(self):
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self.putc([ANN_RCR, ['Read Control Register', 'RCR']])
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if (len(self.mosi) != 2) and (len(self.mosi) != 3):
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self._put_command_warning('Invalid command length.')
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return
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self._put_register_header()
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reg_name = self._get_register_name(self.mosi[0] & REG_ADDR_MASK)
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if reg_name is None:
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# We can't tell if we're accessing MAC/MII registers or not
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# Let's trust the user in this case.
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pass
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else:
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if (reg_name[0] == 'M') and (len(self.mosi) != 3):
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self._put_command_warning('Attempting to read a MAC/MII '
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+ 'register without using the dummy byte.')
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return
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if (reg_name[0] != 'M') and (len(self.mosi) != 2):
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self._put_command_warning('Attempting to read a non-MAC/MII '
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+ 'register using the dummy byte.')
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return
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if len(self.mosi) == 2:
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self._put_data_byte(self.miso[1], 1)
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else:
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self.range_ss, self.range_es = self.ranges[1][0], self.ranges[2][0]
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self.putr([ANN_DATA, ['Dummy Byte', 'Dummy']])
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self._put_data_byte(self.miso[2], 2)
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def _process_rbm(self):
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if self.mosi[0] != 0b00111010:
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self._put_command_warning('Invalid header byte.')
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return
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self.putc([ANN_RBM, ['Read Buffer Memory: Length {0}'.format(
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len(self.mosi) - 1), 'RBM']])
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for i in range(1, len(self.miso)):
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self._put_data_byte(self.miso[i], i)
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def _process_wcr(self):
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self.putc([ANN_WCR, ['Write Control Register', 'WCR']])
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if len(self.mosi) != 2:
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self._put_command_warning('Invalid command length.')
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return
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self._put_register_header()
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self._put_data_byte(self.mosi[1], 1)
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if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
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self.bsel0 = (self.mosi[1] & BIT_ECON1_BSEL0) >> 0
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self.bsel1 = (self.mosi[1] & BIT_ECON1_BSEL1) >> 1
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def _process_wbm(self):
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if self.mosi[0] != 0b01111010:
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self._put_command_warning('Invalid header byte.')
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return
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self.putc([ANN_WBM, ['Write Buffer Memory: Length {0}'.format(
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len(self.mosi) - 1), 'WBM']])
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for i in range(1, len(self.mosi)):
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self._put_data_byte(self.mosi[i], i)
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def _process_bfc(self):
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self.putc([ANN_BFC, ['Bit Field Clear', 'BFC']])
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if len(self.mosi) != 2:
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self._put_command_warning('Invalid command length.')
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return
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self._put_register_header()
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self._put_data_byte(self.mosi[1], 1, True)
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if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
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if self.mosi[1] & BIT_ECON1_BSEL0:
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self.bsel0 = 0
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if self.mosi[1] & BIT_ECON1_BSEL1:
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self.bsel1 = 0
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def _process_bfs(self):
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self.putc([ANN_BFS, ['Bit Field Set', 'BFS']])
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if len(self.mosi) != 2:
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self._put_command_warning('Invalid command length.')
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return
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self._put_register_header()
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self._put_data_byte(self.mosi[1], 1, True)
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if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
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if self.mosi[1] & BIT_ECON1_BSEL0:
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self.bsel0 = 1
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if self.mosi[1] & BIT_ECON1_BSEL1:
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self.bsel1 = 1
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def _process_src(self):
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self.putc([ANN_SRC, ['System Reset Command', 'SRC']])
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if len(self.mosi) != 1:
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self._put_command_warning('Invalid command length.')
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return
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self.bsel0 = 0
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self.bsel1 = 0
|
||||
|
||||
def decode(self, ss, es, data):
|
||||
ptype, data1, data2 = data
|
||||
|
||||
if ptype == 'CS-CHANGE':
|
||||
new_cs = data2
|
||||
|
||||
if new_cs == 0:
|
||||
self.active = True
|
||||
self.cmd_ss = ss
|
||||
self.mosi = []
|
||||
self.miso = []
|
||||
self.ranges = []
|
||||
elif new_cs == 1:
|
||||
if self.active:
|
||||
self.cmd_es = es
|
||||
self._process_command()
|
||||
elif ptype == 'DATA':
|
||||
mosi, miso = data1, data2
|
||||
|
||||
self.mosi.append(mosi)
|
||||
self.miso.append(miso)
|
||||
self.ranges.append((ss, es))
|
||||
Loading…
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Reference in New Issue
Block a user