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demo:logic random save memory

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This commit is contained in:
yunyaobaihong 2023-05-29 17:22:40 +08:00
parent 4d4a3bce3a
commit ade154d9a8
2 changed files with 36 additions and 31 deletions
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63
libsigrok4DSL/hardware/demo/demo.c
View File

@ -161,34 +161,34 @@ static void dso_status_update(struct session_vdev *vdev)
{
struct sr_status *status = (struct sr_status*)&vdev->mstatus;
status->ch0_cyc_tlen = 340;
status->ch1_cyc_tlen = 340;
status->ch0_cyc_cnt = 100;
status->ch1_cyc_cnt = 85;
status->ch0_max = 158;
status->ch1_max = 158;
status->ch0_min = 78;
status->ch1_min = 78;
status->ch0_cyc_plen = 170;
status->ch1_cyc_plen = 170;
status->ch0_cyc_llen = 0;
status->ch1_cyc_llen = 0;
status->ch0_level_valid = 0;
status->ch1_level_valid = 0;
status->ch0_plevel = 1;
status->ch1_plevel = 1;
status->ch0_low_level = 78;
status->ch1_low_level = 78;
status->ch0_high_level = 178;
status->ch1_high_level = 178;
status->ch0_cyc_rlen = 85;
status->ch1_cyc_rlen = 85;
status->ch0_cyc_flen = 85;
status->ch1_cyc_flen = 85;
status->ch0_acc_square = 12496225;
status->ch1_acc_square = 12496225;
status->ch0_acc_mean = 1280000;
status->ch1_acc_mean = 1280000;
// status->ch0_cyc_tlen = 340;
// status->ch1_cyc_tlen = 340;
// status->ch0_cyc_cnt = 100;
// status->ch1_cyc_cnt = 85;
// status->ch0_max = 158;
// status->ch1_max = 158;
// status->ch0_min = 78;
// status->ch1_min = 78;
// status->ch0_cyc_plen = 170;
// status->ch1_cyc_plen = 170;
// status->ch0_cyc_llen = 0;
// status->ch1_cyc_llen = 0;
// status->ch0_level_valid = 0;
// status->ch1_level_valid = 0;
// status->ch0_plevel = 1;
// status->ch1_plevel = 1;
// status->ch0_low_level = 78;
// status->ch1_low_level = 78;
// status->ch0_high_level = 178;
// status->ch1_high_level = 178;
// status->ch0_cyc_rlen = 85;
// status->ch1_cyc_rlen = 85;
// status->ch0_cyc_flen = 85;
// status->ch1_cyc_flen = 85;
// status->ch0_acc_square = 12496225;
// status->ch1_acc_square = 12496225;
// status->ch0_acc_mean = 1280000;
// status->ch1_acc_mean = 1280000;
}
static int logic_adjust_probe(struct sr_dev_inst *sdi, int num_probes)
@ -1325,6 +1325,9 @@ static int hw_dev_acquisition_start(struct sr_dev_inst *sdi,
sr_err("%s: logic_post_buf malloc error", __func__);
return SR_ERR_MALLOC;
}
vdev->logic_mem_limit = (((vdev->total_samples/8)*vdev->enabled_probes) >= LOGIC_MEMORY_LIMIT) ? TRUE : FALSE;
init_random_data(vdev,sdi);
g_timer_start(run_time);
sr_session_source_add(-1, 0, 0, receive_data_logic, sdi);
@ -1475,7 +1478,7 @@ static int receive_data_logic(int fd, int revents, const struct sr_dev_inst *sdi
}
memset(logic_post_buf,LOGIC_LOW_LEVEL,chan_num * vdev->packet_len);
if(vdev->samplerate >= LOGIC_FREQ_LIMIT && vdev->total_samples/vdev->samplerate >= SEC)
if(vdev->logic_mem_limit)
{
for(int i = 0; i < vdev->logic_sel_probe_num;i++)
{
@ -1508,7 +1511,7 @@ static int receive_data_logic(int fd, int revents, const struct sr_dev_inst *sdi
}
ds_data_forward(sdi, &packet);
if(vdev->samplerate >= LOGIC_FREQ_LIMIT && vdev->total_samples/vdev->samplerate >= SEC)
if(vdev->logic_mem_limit)
{
uint16_t target_packet = (LOGIC_BLOCK_LEN/vdev->packet_len);
if(vdev->logci_cur_packet_num % target_packet == 0)

4
libsigrok4DSL/hardware/demo/demo.h
View File

@ -43,6 +43,7 @@
#define LOGIC_BUF_LEN SR_MB(2)
#define LOGIC_FREQ_LIMIT SR_MHZ(100)
#define LOGIC_MEMORY_LIMIT SR_MB(500)
#define DSO_PACKET_NUM_PER_SEC (gdouble)200
#define DSO_PACKET_TIME ((SEC)/(DSO_PACKET_NUM_PER_SEC))
@ -59,7 +60,7 @@
#define ANALOG_MIN_PACKET_NUM(n) ((ANALOG_POST_DATA_PER_SECOND(n))/(ANALOG_MIN_PACKET_LEN))
#define ANALOG_PACKET_ALIGN 2
#define LOGIC_HW_DEPTH (SR_GHZ(10))
#define LOGIC_HW_DEPTH (SR_GHZ(16))
#define LOGIC_MAX_PROBE_NUM 16
@ -234,6 +235,7 @@ struct session_vdev
gboolean offset_change;
gboolean timebase_change;
gboolean channel_mode_change;
gboolean logic_mem_limit;
//post
uint64_t post_data_len;