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fix: The Bandwidth have not save with session file

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This commit is contained in:
dreamsourcelabTAI 2023-03-28 17:10:13 +08:00
parent 4f21488835
commit ba7ef42a7f
7 changed files with 12 additions and 31 deletions
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10
DSView/pv/mainwindow.cpp
View File

@ -700,7 +700,6 @@ namespace pv
{
s_obj["strigger"] = logicSig->get_trig();
}
if (s->signal_type() == DSO_SIGNAL)
{
@ -722,6 +721,7 @@ namespace pv
s_obj["mapUnit"] = analogSig->get_mapUnit();
s_obj["mapMin"] = analogSig->get_mapMin();
s_obj["mapMax"] = analogSig->get_mapMax();
s_obj["mapDefault"] = analogSig->get_mapDefault();
}
channelVar.append(s_obj);
}
@ -903,6 +903,7 @@ namespace pv
for (const QJsonValue &value : sessionObj["channel"].toArray())
{
QJsonObject obj = value.toObject();
if ((probe->index == obj["index"].toDouble()) &&
(probe->type == obj["type"].toDouble()))
{
@ -921,6 +922,12 @@ namespace pv
probe->map_unit = g_strdup(obj["mapUnit"].toString().toStdString().c_str());
probe->map_min = obj["mapMin"].toDouble();
probe->map_max = obj["mapMax"].toDouble();
if (obj.contains("mapDefault"))
{
probe->map_default = obj["mapDefault"].toBool();
}
break;
}
}
@ -934,7 +941,6 @@ namespace pv
// load signal setting
if (mode == DSO)
{
for (auto s : _session->get_signals())
{
for (const QJsonValue &value : sessionObj["channel"].toArray())

1
DSView/pv/sigsession.cpp
View File

@ -458,6 +458,7 @@ namespace pv
int run_dex = 0;
clear_all_decode_task(run_dex);
clear_decode_result();
_capture_data->clear();
_view_data->clear();

1
libsigrok4DSL/hardware/DSL/dscope.c
View File

@ -83,6 +83,7 @@ static const int32_t sessions_daq[] = {
SR_CONF_SAMPLERATE,
SR_CONF_LIMIT_SAMPLES,
SR_CONF_OPERATION_MODE,
SR_CONF_BANDWIDTH_LIMIT,
SR_CONF_TIMEBASE,
SR_CONF_TRIGGER_SLOPE,
SR_CONF_TRIGGER_SOURCE,

14
libsigrok4DSL/hardware/DSL/dsl.c
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@ -45,15 +45,6 @@ static const int32_t probeOptions[] = {
SR_CONF_PROBE_MAP_MAX,
};
static const int32_t probeSessions[] = {
SR_CONF_PROBE_COUPLING,
SR_CONF_PROBE_VDIV,
SR_CONF_PROBE_MAP_DEFAULT,
SR_CONF_PROBE_MAP_UNIT,
SR_CONF_PROBE_MAP_MIN,
SR_CONF_PROBE_MAP_MAX,
};
static const uint8_t probeCoupling[] = {
SR_DC_COUPLING,
SR_AC_COUPLING,
@ -1775,10 +1766,7 @@ SR_PRIV int dsl_config_list(int key, GVariant **data, const struct sr_dev_inst *
*data = g_variant_new_from_data(G_VARIANT_TYPE("ai"),
probeOptions, ARRAY_SIZE(probeOptions)*sizeof(int32_t), TRUE, NULL, NULL);
break;
case SR_CONF_PROBE_SESSIONS:
*data = g_variant_new_from_data(G_VARIANT_TYPE("ai"),
probeSessions, ARRAY_SIZE(probeSessions)*sizeof(int32_t), TRUE, NULL, NULL);
break;
case SR_CONF_PROBE_VDIV:
g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
for (i = 0; devc->profile->dev_caps.vdivs[i]; i++);

5
libsigrok4DSL/hardware/demo/demo.c
View File

@ -637,10 +637,7 @@ static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
*data = g_variant_new_from_data(G_VARIANT_TYPE("ai"),
probeOptions, ARRAY_SIZE(probeOptions)*sizeof(int32_t), TRUE, NULL, NULL);
break;
case SR_CONF_PROBE_SESSIONS:
*data = g_variant_new_from_data(G_VARIANT_TYPE("ai"),
probeSessions, ARRAY_SIZE(probeSessions)*sizeof(int32_t), TRUE, NULL, NULL);
break;
case SR_CONF_PROBE_VDIV:
g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
for (i = 0; devc->profile->dev_caps.vdivs[i]; i++);

9
libsigrok4DSL/hardware/demo/demo.h
View File

@ -227,15 +227,6 @@ static const int32_t probeOptions[] = {
SR_CONF_PROBE_MAP_MAX,
};
static const int32_t probeSessions[] = {
SR_CONF_PROBE_COUPLING,
SR_CONF_PROBE_VDIV,
SR_CONF_PROBE_MAP_DEFAULT,
SR_CONF_PROBE_MAP_UNIT,
SR_CONF_PROBE_MAP_MIN,
SR_CONF_PROBE_MAP_MAX,
};
static const uint8_t probeCoupling[] = {
SR_DC_COUPLING,
SR_AC_COUPLING,

3
libsigrok4DSL/libsigrok.h
View File

@ -984,9 +984,6 @@ enum sr_config_option_id
/** Probe options */
SR_CONF_PROBE_CONFIGS = 30078,
/** Probe options */
SR_CONF_PROBE_SESSIONS = 30079,
/** Enable */
SR_CONF_PROBE_EN = 30080,