Embedded/DSView
1
0
Fork 0
mirror of https://github.com/DreamSourceLab/DSView.git synced 2025-01-13 13:32:53 +08:00
Code Issues Projects Releases Wiki Activity

Merge branch 'master' of https://github.com/dreamsourcelab/DSView

Browse Source
This commit is contained in:
dreamsourcelabTAI 2022-06-27 14:28:12 +08:00
commit f33649df0d
4 changed files with 291 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
libsigrokdecode4DSL/decoders/c2/__init__.py Normal file
View File

@ -0,0 +1,32 @@
##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##
'''
The SPI (Serial Peripheral Interface) protocol decoder supports synchronous
SPI(-like) protocols with a clock line, a MISO and MOSI line for data
transfer in two directions, and an optional CS# pin.
Either MISO or MOSI (but not both) can be optional.
If CS# is supplied, data is only decoded when CS# is asserted (clock
transitions where CS# is not asserted are ignored). If CS# is not supplied,
data is decoded on every clock transition (depending on SPI mode).
'''
from .pd import Decoder

204
libsigrokdecode4DSL/decoders/c2/pd.py Normal file
View File

@ -0,0 +1,204 @@
import sigrokdecode as srd
'''
'''
class ChannelError(Exception):
pass
class Decoder(srd.Decoder):
api_version = 3
id = 'C2'
name = 'C2 interface'
longname = 'Silabs C2 Interface'
desc = 'Half-duplex, synchronous, serial bus.'
license = 'gplv2+'
inputs = ['logic']
outputs = ['C2']
tags = ['Embedded/mcu']
channels = (
{'id': 'c2ck', 'type': 0, 'name': 'c2ck', 'desc': 'Clock'},
{'id': 'c2d', 'type': 0, 'name': 'c2d', 'desc': 'Data'},
)
optional_channels = ()
annotations = (
('106', 'raw-Data', 'raw data'),
('106', 'c2-data', 'c2 data'),
('warnings', 'Warnings'),
)
annotation_rows = (
('raw-Data', 'raw data', (0,)),
('c2-data', 'c2 data', (1,)),
('warnings', 'Warnings', (2,)),
)
def __init__(self):
self.reset()
def reset(self):
self.samplerate = None
self.state= 'reset'
self.bitcount = 0
self.c2data = 0
self.data=0
self.c2dbits = []
self.ss_block = -1
self.samplenum = -1
self.have_c2ck = self.have_c2d = None
self.ins= None
self.dataLen=0
self.remainData=0
def start(self):
self.out_ann = self.register(srd.OUTPUT_ANN)
def metadata(self, key, value):
if key == srd.SRD_CONF_SAMPLERATE:
self.samplerate = value
def decode(self):
if not self.has_channel(0):
raise ChannelError('CLK pin required.')
self.have_c2d = self.has_channel(1)
if not self.have_c2d:
raise ChannelError('C2D pins required.')
tf=0
tr=0
while True:
(c2ck,c2d)=self.wait({0:'e'})
if c2ck == 0: #<23>½<EFBFBD><C2BD><EFBFBD>
tf=self.samplenum
if self.state == 'dataRead':
if self.bitcount ==0:
ss=tr
self.c2data=0
self.c2data |= c2d <<self.bitcount
self.bitcount += 1
if self.bitcount >= 8:
self.put(ss, tf, self.out_ann, [0, ['%02X' % self.c2data]])
self.bitcount=0
self.data|=self.c2data<<((self.dataLen-self.remainData)*8)
self.remainData -= 1
if self.remainData ==0:
self.state = 'end'
elif self.state == 'addressRead':
if self.bitcount ==0:
ss=tr
self.c2data=0
self.c2data |= c2d <<self.bitcount
self.bitcount += 1
if self.bitcount >= 8:
self.put(ss, tf, self.out_ann, [0, ['%02X' % self.c2data]])
self.state = 'end'
elif self.state == 'readWait':
if self.bitcount ==0:
ss=tf
self.bitcount +=1
if c2d == 1:
self.put(ss, tf, self.out_ann, [0, ['Wait','W']])
self.bitcount=0
self.state = 'dataRead'
elif self.state == 'writeWait':
if self.bitcount ==0:
ss=tr
self.bitcount += 1
if c2d == 1:
self.put(ss, tf, self.out_ann, [0, ['Wait','W']])
self.state = 'end'
else: #<23><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
tr=self.samplenum
interval=(tr-tf)*1000*1000/self.samplerate #us
if interval>20:
self.put(tf, tr, self.out_ann, [0, [ 'Reset','R']])
self.state='start'
elif self.state == 'start':
self.put(tf, tr, self.out_ann, [0, [ 'Start','S']])
self.state='ins'
self.bitcount=0
self.ins=0
self.data=0
self.dataLen=0
ss1=tf
elif self.state == 'ins':
if self.bitcount ==0:
ss=tr
self.c2data=0
self.ins |= c2d <<self.bitcount
self.bitcount += 1
if self.bitcount >= 2:
(c2ck,c2d)=self.wait({0:'f'})
if self.ins == 0 :
self.state = 'dataReadLen'
elif self.ins == 2:
self.state = 'addressRead'
elif self.ins == 1:
self.state = 'dataWriteLen'
else:
self.state = 'addressWrite'
self.put(ss, self.samplenum, self.out_ann, [0, [ '%1d'%self.ins]])
self.bitcount=0
elif self.state == 'addressWrite':
if self.bitcount ==0:
ss=tr
self.c2data=0
self.c2data |= c2d <<self.bitcount
self.bitcount += 1
if self.bitcount >= 8:
(c2ck,c2d)=self.wait({0:'f'})
tf=self.samplenum
self.put(ss, tf, self.out_ann, [0, ['%02X' % self.c2data]])
self.bitcount=0
self.state = 'end'
elif self.state == 'dataReadLen':
if self.bitcount ==0:
ss=tr
self.c2data=0
self.c2data |= c2d <<self.bitcount
self.bitcount += 1
if self.bitcount >= 2:
self.dataLen=self.c2data+1
self.remainData=self.dataLen
#(c2ck,c2d)=self.wait({0:'f'})
self.put(ss, self.samplenum, self.out_ann, [0, [ '%01d'%self.c2data]])
self.state='readWait'
self.bitcount=0
elif self.state == 'dataWriteLen':
if self.bitcount ==0:
ss=tr
self.c2data=0
self.c2data |= c2d <<self.bitcount
self.bitcount += 1
if self.bitcount >= 2:
self.dataLen=self.c2data+1
self.remainData=self.dataLen
(c2ck,c2d)=self.wait({0:'f'})
self.put(ss, self.samplenum, self.out_ann, [0, ['%01d'%self.c2data]])
self.state='dataWrite'
self.bitcount=0
self.c2data=0
elif self.state == 'dataWrite':
if self.bitcount ==0:
ss=tr
self.c2data=0
self.c2data |= c2d <<self.bitcount
self.bitcount += 1
if self.bitcount >= 8:
self.put(ss, tr, self.out_ann, [0, ['%02X' % self.c2data]])
self.bitcount=0
self.data|=self.c2data<<((self.dataLen-self.remainData)*8)
self.remainData -= 1
if self.remainData ==0:
self.state='writeWait'
elif self.state == 'end':
self.state='start'
self.put(tf, tr, self.out_ann, [0, [ 'End','E']])
if self.ins == 0:
self.put(ss1, tr, self.out_ann, [1, [ 'ReadData(%01d)=0x%02X'%(self.dataLen,self.data)]])
elif self.ins == 1:
self.put(ss1, tr, self.out_ann, [1, [ 'WriteData(0x%02X,%01d)'%(self.data,self.dataLen)]])
elif self.ins == 2:
self.put(ss1, tr, self.out_ann, [1, [ 'ReadAddress()=0x%02X'%self.c2data]])
elif self.ins == 3:
self.put(ss1, tr, self.out_ann, [1, [ 'WriteAddress(0x%02X)'%self.c2data]])

2
libsigrokdecode4DSL/decoders/modbus/pd.py
View File

@ -814,7 +814,7 @@ class Modbus_ADU_CS(Modbus_ADU):
class Decoder(srd.Decoder):
api_version = 3
id = 'modbus'
name = 'Modbus'
name = 'Modbus RTU'
longname = 'Modbus RTU over RS232/RS485'
desc = 'Modbus RTU protocol for industrial applications.'
license = 'gplv3+'

68
libsigrokdecode4DSL/decoders/usb_power_delivery/pd.py
View File

@ -67,6 +67,25 @@ DATA_TYPES = {
15: 'VDM'
}
# Extended message type
EXTENDED_TYPES = {
1: 'Source_Cap_Extended',
2: 'Status',
3: 'Get_Battery_Cap',
4: 'Get_Battery_Status',
5: 'Battery_Cap',
6: 'Get_Manufacturer_Info',
7: 'Manufacturer_Info',
8: 'Security_Request',
9: 'Security_Response',
10: 'Firmware_Update_Request',
11: 'Firmware_Update_Response',
12: 'PPS_Status',
13: 'Country_Info',
14: 'Country_Codes'
}
# 4b5b encoding of the symbols
DEC4B5B = [
0x10, # Error 00000
@ -252,7 +271,7 @@ class Decoder(srd.Decoder):
mark = self.cap_mark[pos]
if mark == 3:
op_v = ((rdo >> 9) & 0x7ff) * 0.02
op_a = (rdo & 0x3f) * 0.05
op_a = (rdo & 0xff) * 0.05
t_settings = '%gV %gA' % (op_v, op_a)
elif mark == 2:
op_w = ((rdo >> 10) & 0x3ff) * 0.25
@ -320,19 +339,19 @@ class Decoder(srd.Decoder):
minv = ((pdo >> 10) & 0x3ff) * 0.05
maxv = ((pdo >> 20) & 0x3ff) * 0.05
ma = ((pdo >> 0) & 0x3ff) * 0.01
p = '%g/%gV %gA' % (minv, maxv, ma)
p = '%g/%gV %gA (%gW)' % (minv, maxv, ma, maxv*ma)
self.stored_pdos[idx] = '%s %g/%gV' % (t_name, minv, maxv)
elif t1 == 3:
t2 = (pdo >> 28) & 3
if t2 == 0:
t_name = 'Programmable|PPS'
t_name = 'PPS'
flags = {
(1 << 29): 'power_limited',
}
minv = ((pdo >> 8) & 0xff) * 0.1
maxv = ((pdo >> 17) & 0xff) * 0.1
ma = ((pdo >> 0) & 0xff) * 0.05
p = '%g/%gV %gA' % (minv, maxv, ma)
p = '%g/%gV %gA (%gW)' % (minv, maxv, ma, maxv*ma)
if (pdo >> 27) & 0x1:
p += ' [limited]'
self.stored_pdos[idx] = '%s %g/%gV' % (t_name, minv, maxv)
@ -376,10 +395,26 @@ class Decoder(srd.Decoder):
# TODO: Check all 0 bits are 0 / emit warnings.
return 'mode %s' % (mode_name) if idx == 0 else 'invalid BRO'
def get_hex(self, idx, data):
if idx == 0:
txt = 'Ext H:%04x' % ( data & 0xFFFF )
txt += ' DATA: %02x' % ((data >> 24)&0xFF)
txt += ' %02x' % ((data >> 16)&0xFF)
else:
txt = '%02x' % ((data >> 8)&0xFF)
txt += ' %02x' % ((data >> 0)&0xFF)
txt += ' %02x' % ((data >> 24)&0xFF)
txt += ' %02x' % ((data >> 16)&0xFF)
return txt
def putpayload(self, s0, s1, idx):
t = self.head_type()
t = self.head_type() if self.head_ext() == 0 else 255
txt = '['+str(idx+1)+'] '
if t == 2:
if t == 255:
txt += self.get_hex(idx, self.data[idx])
elif t == 2:
txt += self.get_request(self.data[idx])
elif t == 1 or t == 4:
txt += self.get_source_sink_cap(self.data[idx], idx+1, t==1)
@ -396,7 +431,10 @@ class Decoder(srd.Decoder):
if self.head_data_role() != self.head_power_role():
role += '/DFP' if self.head_data_role() else '/UFP'
t = self.head_type()
if self.head_count() == 0:
if self.head_ext() == 1:
shortm = EXTENDED_TYPES[t] if t in EXTENDED_TYPES else 'EXTENDED???'
elif self.head_count() == 0:
shortm = CTRL_TYPES[t]
else:
shortm = DATA_TYPES[t] if t in DATA_TYPES else 'DAT???'
@ -405,6 +443,9 @@ class Decoder(srd.Decoder):
self.putx(0, -1, [ann_type, [longm, shortm]])
self.text += longm
def head_ext(self):
return (self.head >> 15) & 1
def head_id(self):
return (self.head >> 9) & 7
@ -418,7 +459,7 @@ class Decoder(srd.Decoder):
return ((self.head >> 6) & 3) + 1
def head_type(self):
return self.head & 0xF
return self.head & 0x1F
def head_count(self):
return (self.head >> 12) & 7
@ -559,15 +600,14 @@ class Decoder(srd.Decoder):
self.head = self.get_short()
self.putx(self.idx-20, self.idx, [3, ['H:%04x' % (self.head), 'HD']])
self.puthead()
# Decode data payload
# Decode data payload
for i in range(self.head_count()):
self.data.append(self.get_word())
self.putx(self.idx-40, self.idx,
[4, ['[%d]%08x' % (i, self.data[i]), 'D%d' % (i)]])
self.putx(self.idx-40, self.idx,[4, ['[%d]%08x' % (i, self.data[i]), 'D%d' % (i)]])
self.putpayload(self.idx-40, self.idx, i)
# CRC check
# CRC check
self.crc = self.get_word()
ccrc = self.compute_crc32()
if self.crc != ccrc: