mirror of
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261 lines
9.7 KiB
Python
Executable File
261 lines
9.7 KiB
Python
Executable File
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2010-2016 Uwe Hermann <uwe@hermann-uwe.de>
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## Copyright (C) 2019 DreamSourceLab <support@dreamsourcelab.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
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# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
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# TODO: Implement support for detecting various bus errors.
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import sigrokdecode as srd
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'''
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OUTPUT_PYTHON format:
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Packet:
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[<ptype>, <pdata>]
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<ptype>:
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- 'START' (START condition)
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- 'START REPEAT' (Repeated START condition)
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- 'ADDRESS READ' (Slave address, read)
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- 'ADDRESS WRITE' (Slave address, write)
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- 'DATA READ' (Data, read)
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- 'DATA WRITE' (Data, write)
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- 'STOP' (STOP condition)
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- 'ACK' (ACK bit)
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- 'NACK' (NACK bit)
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- 'BITS' (<pdata>: list of data/address bits and their ss/es numbers)
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<pdata> is the data or address byte associated with the 'ADDRESS*' and 'DATA*'
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command. Slave addresses do not include bit 0 (the READ/WRITE indication bit).
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For example, a slave address field could be 0x51 (instead of 0xa2).
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For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <pdata> is None.
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'''
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# CMD: [annotation-type-index, long annotation, short annotation]
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proto = {
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'START': [0, 'Start', 'S'],
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'START REPEAT': [1, 'Start repeat', 'Sr'],
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'STOP': [2, 'Stop', 'P'],
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'ACK': [3, 'ACK', 'A'],
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'NACK': [4, 'NACK', 'N'],
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'ADDRESS READ': [5, 'Address read', 'AR'],
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'ADDRESS WRITE': [6, 'Address write', 'AW'],
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'DATA READ': [7, 'Data read', 'DR'],
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'DATA WRITE': [8, 'Data write', 'DW'],
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}
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class Decoder(srd.Decoder):
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api_version = 3
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id = '0:i2c'
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name = '0:I²C'
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longname = 'Inter-Integrated Circuit'
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desc = 'Two-wire, multi-master, serial bus.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = ['i2c']
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tags = ['Embedded/industrial']
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channels = (
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{'id': 'scl', 'type': 8, 'name': 'SCL', 'desc': 'Serial clock line'},
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{'id': 'sda', 'type': 108, 'name': 'SDA', 'desc': 'Serial data line'},
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)
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options = (
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{'id': 'address_format', 'desc': 'Displayed slave address format',
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'default': 'shifted', 'values': ('shifted', 'unshifted')},
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)
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annotations = (
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('7', 'start', 'Start condition'),
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('6', 'repeat-start', 'Repeat start condition'),
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('1', 'stop', 'Stop condition'),
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('5', 'ack', 'ACK'),
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('0', 'nack', 'NACK'),
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('112', 'address-read', 'Address read'),
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('111', 'address-write', 'Address write'),
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('110', 'data-read', 'Data read'),
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('109', 'data-write', 'Data write'),
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('1000', 'warnings', 'Human-readable warnings'),
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)
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annotation_rows = (
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('addr-data', 'Address/Data', (0, 1, 2, 3, 4, 5, 6, 7, 8)),
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('warnings', 'Warnings', (9,)),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.samplerate = None
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self.ss = self.es = self.ss_byte = -1
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self.bitcount = 0
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self.databyte = 0
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self.wr = -1
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self.is_repeat_start = 0
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self.state = 'FIND START'
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self.pdu_start = None
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self.pdu_bits = 0
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self.bits = []
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def metadata(self, key, value):
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if key == srd.SRD_CONF_SAMPLERATE:
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self.samplerate = value
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def putx(self, data):
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self.put(self.ss, self.es, self.out_ann, data)
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def handle_start(self):
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self.ss, self.es = self.samplenum, self.samplenum
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self.pdu_start = self.samplenum
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self.pdu_bits = 0
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cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
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self.putx([proto[cmd][0], proto[cmd][1:]])
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self.state = 'FIND ADDRESS'
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self.bitcount = self.databyte = 0
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self.is_repeat_start = 1
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self.wr = -1
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self.bits = []
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# Gather 8 bits of data plus the ACK/NACK bit.
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def handle_address_or_data(self, scl, sda):
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self.pdu_bits += 1
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# Address and data are transmitted MSB-first.
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self.databyte <<= 1
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self.databyte |= sda
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# Remember the start of the first data/address bit.
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if self.bitcount == 0:
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self.ss_byte = self.samplenum
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# Store individual bits and their start/end samplenumbers.
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# In the list, index 0 represents the LSB (I²C transmits MSB-first).
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self.bits.insert(0, [sda, self.samplenum, self.samplenum])
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if self.bitcount > 0:
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self.bits[1][2] = self.samplenum
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if self.bitcount == 7:
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self.bitwidth = self.bits[1][2] - self.bits[2][2]
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self.bits[0][2] += self.bitwidth
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# Return if we haven't collected all 8 + 1 bits, yet.
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if self.bitcount < 7:
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self.bitcount += 1
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return
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d = self.databyte
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if self.state == 'FIND ADDRESS':
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# The READ/WRITE bit is only in address bytes, not data bytes.
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self.wr = 0 if (self.databyte & 1) else 1
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if self.options['address_format'] == 'shifted':
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d = d >> 1
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bin_class = -1
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if self.state == 'FIND ADDRESS' and self.wr == 1:
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cmd = 'ADDRESS WRITE'
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bin_class = 1
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elif self.state == 'FIND ADDRESS' and self.wr == 0:
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cmd = 'ADDRESS READ'
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bin_class = 0
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elif self.state == 'FIND DATA' and self.wr == 1:
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cmd = 'DATA WRITE'
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bin_class = 3
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elif self.state == 'FIND DATA' and self.wr == 0:
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cmd = 'DATA READ'
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bin_class = 2
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self.ss, self.es = self.ss_byte, self.samplenum + self.bitwidth
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if cmd.startswith('ADDRESS'):
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self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
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w = ['Write', 'Wr', 'W'] if self.wr else ['Read', 'Rd', 'R']
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self.putx([proto[cmd][0], w])
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self.ss, self.es = self.ss_byte, self.samplenum
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self.putx([proto[cmd][0], ['%s: %02X' % (proto[cmd][1], d),
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'%s: %02X' % (proto[cmd][2], d), '%02X' % d]])
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# Done with this packet.
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self.bitcount = self.databyte = 0
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self.bits = []
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self.state = 'FIND ACK'
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def get_ack(self, scl, sda):
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self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
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cmd = 'NACK' if (sda == 1) else 'ACK'
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self.putx([proto[cmd][0], proto[cmd][1:]])
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# There could be multiple data bytes in a row, so either find
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# another data byte or a STOP condition next.
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self.state = 'FIND DATA'
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def handle_stop(self):
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cmd = 'STOP'
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self.ss, self.es = self.samplenum, self.samplenum
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self.putx([proto[cmd][0], proto[cmd][1:]])
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self.state = 'FIND START'
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self.is_repeat_start = 0
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self.wr = -1
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self.bits = []
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def decode(self):
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while True:
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# State machine.
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if self.state == 'FIND START':
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# Wait for a START condition (S): SCL = high, SDA = falling.
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self.wait({0: 'h', 1: 'f'})
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self.handle_start()
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elif self.state == 'FIND ADDRESS':
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# Wait for any of the following conditions (or combinations):
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# a) Data sampling of receiver: SCL = rising, and/or
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# b) START condition (S): SCL = high, SDA = falling, and/or
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# c) STOP condition (P): SCL = high, SDA = rising
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(scl, sda) = self.wait([{0: 'r'}, {0: 'h', 1: 'f'}, {0: 'h', 1: 'r'}])
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# Check which of the condition(s) matched and handle them.
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if (self.matched & (0b1 << 0)):
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self.handle_address_or_data(scl, sda)
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elif (self.matched & (0b1 << 1)):
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self.handle_start()
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elif (self.matched & (0b1 << 2)):
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self.handle_stop()
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elif self.state == 'FIND DATA':
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# Wait for any of the following conditions (or combinations):
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# a) Data sampling of receiver: SCL = rising, and/or
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# b) START condition (S): SCL = high, SDA = falling, and/or
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# c) STOP condition (P): SCL = high, SDA = rising
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(scl, sda) = self.wait([{0: 'r'}, {0: 'h', 1: 'f'}, {0: 'h', 1: 'r'}])
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# Check which of the condition(s) matched and handle them.
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if (self.matched & (0b1 << 0)):
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self.handle_address_or_data(scl, sda)
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elif (self.matched & (0b1 << 1)):
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self.handle_start()
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elif (self.matched & (0b1 << 2)):
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self.handle_stop()
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elif self.state == 'FIND ACK':
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# Wait for any of the following conditions (or combinations):
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# a) a data/ack bit: SCL = rising.
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# b) STOP condition (P): SCL = high, SDA = rising
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(scl, sda) = self.wait([{0: 'r'}, {0: 'h', 1: 'r'}])
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if (self.matched & (0b1 << 0)):
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self.get_ack(scl, sda)
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elif (self.matched & (0b1 << 1)):
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self.handle_stop()
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