mirror of
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332 lines
13 KiB
Python
Executable File
332 lines
13 KiB
Python
Executable File
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2016 Elias Oenal <sigrok@eliasoenal.com>
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## All rights reserved.
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##
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## Redistribution and use in source and binary forms, with or without
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## modification, are permitted provided that the following conditions are met:
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##
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## 1. Redistributions of source code must retain the above copyright notice,
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## this list of conditions and the following disclaimer.
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## 2. Redistributions in binary form must reproduce the above copyright notice,
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## this list of conditions and the following disclaimer in the documentation
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## and/or other materials provided with the distribution.
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##
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## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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## POSSIBILITY OF SUCH DAMAGE.
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##
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import sigrokdecode as srd
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class Decoder(srd.Decoder):
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api_version = 2
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id = 'mdio'
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name = 'MDIO'
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longname = 'Management Data Input/Output'
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desc = 'Half-duplex sync serial bus for MII management between MAC and PHY.'
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license = 'bsd'
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inputs = ['logic']
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outputs = ['mdio']
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channels = (
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{'id': 'mdc', 'name': 'MDC', 'desc': 'Clock'},
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{'id': 'mdio', 'name': 'MDIO', 'desc': 'Data'},
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)
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options = (
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{'id': 'show_debug_bits', 'desc': 'Show debug bits',
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'default': 'no', 'values': ('yes', 'no')},
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)
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annotations = (
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('bit-val', 'Bit value'),
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('bit-num', 'Bit number'),
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('frame', 'Frame'),
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('frame-idle', 'Bus idle state'),
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('frame-error', 'Frame error'),
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('decode', 'Decode'),
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)
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annotation_rows = (
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('bit-val', 'Bit value', (0,)),
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('bit-num', 'Bit number', (1,)),
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('frame', 'Frame', (2, 3)),
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('frame-error', 'Frame error', (4,)),
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('decode', 'Decode', (5,)),
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)
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def __init__(self):
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self.last_mdc = 1
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self.illegal_bus = 0
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self.samplenum = -1
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self.clause45_addr = -1 # Clause 45 is context sensitive.
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self.reset_decoder_state()
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def start(self):
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self.out_python = self.register(srd.OUTPUT_PYTHON)
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def putbit(self, mdio, ss, es):
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self.put(ss, es, self.out_ann, [0, ['%d' % mdio]])
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if self.options['show_debug_bits'] == 'yes':
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self.put(ss, es, self.out_ann, [1, ['%d' % (self.bitcount - 1), '%d' % ((self.bitcount - 1) % 10)]])
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def putff(self, data):
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self.put(self.ss_frame_field, self.samplenum, self.out_ann, data)
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def putdata(self):
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self.put(self.ss_frame_field, self.mdiobits[0][2], self.out_ann,
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[2, ['DATA: %04X' % self.data, 'DATA', 'D']])
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if self.clause45 and self.opcode == 0:
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self.clause45_addr = self.data
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# Decode data.
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if self.opcode > 0 or not self.clause45:
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decoded_min = ''
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if self.clause45 and self.clause45_addr != -1:
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decoded_min += str.format('ADDR: %04X ' % self.clause45_addr)
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elif self.clause45:
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decoded_min += str.format('ADDR: UKWN ' % self.clause45_addr)
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if self.clause45 and self.opcode > 1 \
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or (not self.clause45 and self.opcode):
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decoded_min += str.format('READ: %04X' % self.data)
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is_read = 1
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else:
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decoded_min += str.format('WRITE: %04X' % self.data)
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is_read = 0
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decoded_ext = str.format(' %s: %02d' % \
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('PRTAD' if self.clause45 else 'PHYAD', self.portad))
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decoded_ext += str.format(' %s: %02d' % \
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('DEVAD' if self.clause45 else 'REGAD', self.devad))
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if self.ta_invalid or self.op_invalid:
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decoded_ext += ' ERROR'
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self.put(self.ss_frame, self.mdiobits[0][2], self.out_ann,
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[5, [decoded_min + decoded_ext, decoded_min]])
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self.put(self.ss_frame, self.mdiobits[0][2], self.out_python,
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[(bool(self.clause45), int(self.clause45_addr), \
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bool(is_read), int(self.portad), int(self.devad), \
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int(self.data))])
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# Post read increment address.
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if self.clause45 and self.opcode == 2 and self.clause45_addr != -1:
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self.clause45_addr += 1
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def reset_decoder_state(self):
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self.mdiobits = []
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self.bitcount = -1
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self.opcode = -1
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self.clause45 = 0
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self.ss_frame = -1
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self.ss_frame_field = -1
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self.preamble_len = 0
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self.ta_invalid = -1
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self.op_invalid = ''
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self.portad = -1
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self.portad_bits = 5
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self.devad = -1
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self.devad_bits = 5
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self.data = -1
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self.data_bits = 16
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self.state = 'PRE'
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def state_PRE(self, mdio):
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if self.illegal_bus:
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if mdio == 0: # Stay in illegal bus state.
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return
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else: # Leave and continue parsing.
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self.illegal_bus = 0
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self.put(self.ss_illegal, self.samplenum, self.out_ann,
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[4, ['ILLEGAL BUS STATE', 'ILL']])
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self.ss_frame = self.samplenum
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if self.ss_frame == -1:
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self.ss_frame = self.samplenum
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if mdio == 1:
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self.preamble_len += 1
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# Valid MDIO can't clock more than 16 succeeding ones without being
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# in either IDLE or PRE.
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if self.preamble_len > 16:
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if self.preamble_len >= 10000 + 32:
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self.put(self.ss_frame, self.mdiobits[32][1], self.out_ann,
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[3, ['IDLE #%d' % (self.preamble_len - 32), 'IDLE', 'I']])
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self.ss_frame = self.mdiobits[32][1]
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self.preamble_len = 32
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# This is getting out of hand, free some memory.
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del self.mdiobits[33:-1]
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if mdio == 0:
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if self.preamble_len < 32:
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self.ss_frame = self.mdiobits[self.preamble_len][1]
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self.put(self.ss_frame, self.samplenum, self.out_ann,
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[4, ['SHORT PREAMBLE', 'SHRT PRE']])
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elif self.preamble_len > 32:
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self.ss_frame = self.mdiobits[32][1]
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self.put(self.mdiobits[self.preamble_len][1],
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self.mdiobits[32][1], self.out_ann,
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[3, ['IDLE #%d' % (self.preamble_len - 32),
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'IDLE', 'I']])
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self.preamble_len = 32
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else:
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self.ss_frame = self.mdiobits[32][1]
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self.put(self.ss_frame, self.samplenum, self.out_ann,
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[2, ['PRE #%d' % self.preamble_len, 'PRE', 'P']])
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self.ss_frame_field = self.samplenum
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self.state = 'ST'
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elif mdio == 0:
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self.ss_illegal = self.ss_frame
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self.illegal_bus = 1
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def state_ST(self, mdio):
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if mdio == 0:
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self.clause45 = 1
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self.state = 'OP'
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def state_OP(self, mdio):
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if self.opcode == -1:
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if self.clause45:
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st = ['ST (Clause 45)', 'ST 45']
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else:
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st = ['ST (Clause 22)', 'ST 22']
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self.putff([2, st + ['ST', 'S']])
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self.ss_frame_field = self.samplenum
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if mdio:
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self.opcode = 2
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else:
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self.opcode = 0
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else:
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if self.clause45:
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self.state = 'PRTAD'
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self.opcode += mdio
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else:
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if mdio == self.opcode:
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self.op_invalid = 'invalid for Clause 22'
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self.state = 'PRTAD'
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def state_PRTAD(self, mdio):
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if self.portad == -1:
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self.portad = 0
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if self.clause45:
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if self.opcode == 0:
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op = ['OP: ADDR', 'OP: A']
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elif self.opcode == 1:
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op = ['OP: WRITE', 'OP: W']
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elif self.opcode == 2:
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op = ['OP: READINC', 'OP: RI']
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elif self.opcode == 3:
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op = ['OP: READ', 'OP: R']
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else:
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op = ['OP: READ', 'OP: R'] if self.opcode else ['OP: WRITE', 'OP: W']
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self.putff([2, op + ['OP', 'O']])
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if self.op_invalid:
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self.putff([4, ['OP %s' % self.op_invalid, 'OP', 'O']])
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self.ss_frame_field = self.samplenum
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self.portad_bits -= 1
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self.portad |= mdio << self.portad_bits
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if not self.portad_bits:
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self.state = 'DEVAD'
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def state_DEVAD(self, mdio):
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if self.devad == -1:
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self.devad = 0
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if self.clause45:
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prtad = ['PRTAD: %02d' % self.portad, 'PRT', 'P']
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else:
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prtad = ['PHYAD: %02d' % self.portad, 'PHY', 'P']
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self.putff([2, prtad])
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self.ss_frame_field = self.samplenum
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self.devad_bits -= 1
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self.devad |= mdio << self.devad_bits
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if not self.devad_bits:
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self.state = 'TA'
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def state_TA(self, mdio):
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if self.ta_invalid == -1:
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self.ta_invalid = ''
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if self.clause45:
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regad = ['DEVAD: %02d' % self.devad, 'DEV', 'D']
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else:
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regad = ['REGAD: %02d' % self.devad, 'REG', 'R']
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self.putff([2, regad])
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self.ss_frame_field = self.samplenum
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if mdio != 1 and ((self.clause45 and self.opcode < 2)
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or (not self.clause45 and self.opcode == 0)):
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self.ta_invalid = ' invalid (bit1)'
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else:
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if mdio != 0:
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if self.ta_invalid:
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self.ta_invalid = ' invalid (bit1 and bit2)'
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else:
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self.ta_invalid = ' invalid (bit2)'
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self.state = 'DATA'
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def state_DATA(self, mdio):
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if self.data == -1:
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self.data = 0
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self.putff([2, ['TURNAROUND', 'TA', 'T']])
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if self.ta_invalid:
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self.putff([4, ['TURNAROUND%s' % self.ta_invalid,
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'TA%s' % self.ta_invalid, 'TA', 'T']])
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self.ss_frame_field = self.samplenum
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self.data_bits -= 1
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self.data |= mdio << self.data_bits
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if not self.data_bits:
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# Output final bit.
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self.mdiobits[0][2] = self.mdiobits[0][1] + self.quartile_cycle_length()
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self.bitcount += 1
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self.putbit(self.mdiobits[0][0], self.mdiobits[0][1], self.mdiobits[0][2])
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self.putdata()
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self.reset_decoder_state()
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def process_state(self, argument, mdio):
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method_name = 'state_' + str(argument)
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method = getattr(self, method_name)
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return method(mdio)
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# Returns the first quartile point of the frames cycle lengths. This is a
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# conservative guess for the end of the last cycle. On average it will be
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# more likely to fall short, than being too long, which makes for better
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# readability in GUIs.
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def quartile_cycle_length(self):
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# 48 is the minimum number of samples we have to have at the end of a
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# frame. The last sample only has a leading clock edge and is ignored.
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bitlen = []
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for i in range(1, 49):
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bitlen.append(self.mdiobits[i][2] - self.mdiobits[i][1])
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bitlen = sorted(bitlen)
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return bitlen[12]
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def handle_bit(self, mdio):
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self.bitcount += 1
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self.mdiobits.insert(0, [mdio, self.samplenum, -1])
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if self.bitcount > 0:
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self.mdiobits[1][2] = self.samplenum # Note end of last cycle.
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# Output the last bit we processed.
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self.putbit(self.mdiobits[1][0], self.mdiobits[1][1], self.mdiobits[1][2])
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self.process_state(self.state, mdio)
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def decode(self, ss, es, data):
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for (self.samplenum, pins) in data:
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data.itercnt += 1
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# Ignore identical samples early on (for performance reasons).
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if self.last_mdc == pins[0]:
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continue
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self.last_mdc = pins[0]
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if pins[0] == 0: # Check for rising edge.
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continue
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# Found the correct clock edge, now get/handle the bit(s).
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self.handle_bit(pins[1])
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