mirror of
https://github.com/DreamSourceLab/DSView.git
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138 lines
4.5 KiB
Python
138 lines
4.5 KiB
Python
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2020 Analog Devices Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 3 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sigrokdecode as srd
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modes = {
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0: ['Normal Mode', 'Normal', 'Norm', 'N'],
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1: ['Power Down Mode', 'Power Down', 'PD'],
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2: ['Power Up Mode', 'Power Up', 'PU'],
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}
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input_voltage_format = ['%.6fV', '%.2fV']
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validation = {
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'invalid': ['Invalid data', 'Invalid', 'N/A'],
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'incomplete': ['Incomplete conversion', 'Incomplete', 'I'],
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'complete': ['Complete conversion', 'Complete', 'C'],
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}
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'ad79x0'
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name = 'AD79x0'
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longname = 'Analog Devices AD79x0'
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desc = 'Analog Devices AD7910/AD7920 12-bit ADC.'
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license = 'gplv2+'
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inputs = ['spi']
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outputs = []
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tags = ['IC', 'Analog/digital']
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annotations = (
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('mode', 'Mode'),
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('voltage', 'Voltage'),
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('validation', 'Validation'),
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)
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annotation_rows = (
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('modes', 'Modes', (0,)),
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('voltages', 'Voltages', (1,)),
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('data_validation', 'Data validation', (2,)),
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)
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options = (
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{'id': 'vref', 'desc': 'Reference voltage (V)', 'default': 1.5},
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)
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def __init__(self,):
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self.reset()
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def reset(self):
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self.samplerate = 0
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self.samples_bit = -1
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self.ss = -1
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self.start_sample = 0
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self.previous_state = 0
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self.data = 0
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def metadata(self, key, value):
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if key == srd.SRD_CONF_SAMPLERATE:
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self.samplerate = value
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def put_validation(self, pos, msg):
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self.put(pos[0], pos[1], self.out_ann, [2, validation[msg]])
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def put_data(self, pos, input_voltage):
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ann = []
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for format in input_voltage_format:
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ann.append(format % input_voltage)
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self.put(pos[0], pos[1], self.out_ann, [1, ann])
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def put_mode(self, pos, msg):
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self.put(pos[0], pos[1], self.out_ann, [0, modes[msg]])
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def decode(self, ss, es, data):
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ptype = data[0]
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if ptype == 'CS-CHANGE':
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cs_old, cs_new = data[1:]
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if cs_old is not None and cs_old == 0 and cs_new == 1:
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if self.samples_bit == -1:
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return
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self.data >>= 1
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nb_bits = (ss - self.ss) // self.samples_bit
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if nb_bits >= 10:
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if self.data == 0xFFF:
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self.put_mode([self.start_sample, es], 2)
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self.previous_state = 0
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self.put_validation([self.start_sample, es], 'invalid')
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else:
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self.put_mode([self.start_sample, es], 0)
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if nb_bits == 16:
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self.put_validation([self.start_sample, es], 'complete')
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elif nb_bits < 16:
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self.put_validation([self.start_sample, es], 'incomplete')
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vin = (self.data / ((2**12) - 1)) * self.options['vref']
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self.put_data([self.start_sample, es], vin)
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elif nb_bits < 10:
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self.put_mode([self.start_sample, es], 1)
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self.previous_state = 1
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self.put_validation([self.start_sample, es], 'invalid')
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self.ss = -1
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self.samples_bit = -1
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self.data = 0
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elif cs_old is not None and cs_old == 1 and cs_new == 0:
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self.start_sample = ss
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self.samples_bit = -1
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elif ptype == 'BITS':
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if data[2] is None:
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return
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miso = data[2]
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if self.samples_bit == -1:
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self.samples_bit = miso[0][2] - miso[0][1]
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if self.ss == -1:
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self.ss = ss
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for bit in reversed(miso):
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self.data = self.data | bit[0]
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self.data <<= 1
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