mirror of
https://github.com/DreamSourceLab/DSView.git
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112 lines
3.8 KiB
Python
112 lines
3.8 KiB
Python
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2018 Stefan Petersen <spe@ciellt.se>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import re
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import sigrokdecode as srd
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registers = {
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0x80: ['WRDS', 0, lambda _: ''],
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0x81: ['STO', 1, lambda _: ''],
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0x82: ['SLEEP', 2, lambda _: ''],
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0x83: ['WRITE', 3, lambda v: '0x%x' % v],
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0x84: ['WREN', 4, lambda _: ''],
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0x85: ['RCL', 5, lambda _: ''],
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0x86: ['READ', 6, lambda v: '0x%x' % v],
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0x87: ['READ', 7, lambda v: '0x%x' % v],
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}
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'x2444m'
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name = 'X2444M/P'
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longname = 'Xicor X2444M/P'
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desc = 'Xicor X2444M/P nonvolatile static RAM protocol.'
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license = 'gplv2+'
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inputs = ['spi']
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outputs = []
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tags = ['IC', 'Memory']
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annotations = (
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('wrds', 'Write disable'),
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('sto', 'Store RAM data in EEPROM'),
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('sleep', 'Enter sleep mode'),
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('write', 'Write data into RAM'),
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('wren', 'Write enable'),
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('rcl', 'Recall EEPROM data into RAM'),
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('read', 'Data read from RAM'),
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('read', 'Data read from RAM'),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.cs_start = 0
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self.cs_asserted = False
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self.cmd_digit = 0
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def putreadwrite(self, ss, es, reg, idx, addr, value):
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self.put(ss, es, self.out_ann,
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[idx, ['%s: %s => 0x%4.4x' % (reg, addr, value),
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'%s: %s => 0x%4.4x' % (reg[0], addr, value), reg[0]]])
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def putcmd(self, ss, es, reg, idx):
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self.put(ss, es, self.out_ann, [idx, [reg, reg[0]]])
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def decode(self, ss, es, data):
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ptype, mosi, miso = data
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if ptype == 'DATA':
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if not self.cs_asserted:
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return
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if self.cmd_digit == 0:
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self.addr = mosi
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self.addr_start = ss
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elif self.cmd_digit > 0:
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self.read_value = (self.read_value << 8) + miso
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self.write_value = (self.write_value << 8) + mosi
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self.cmd_digit += 1
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elif ptype == 'CS-CHANGE':
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self.cs_asserted = (miso == 1)
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# When not asserted, CS has just changed from asserted to deasserted.
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if not self.cs_asserted:
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# Only one digit, simple command. Else read/write.
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if self.cmd_digit == 1:
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name, idx, decoder = registers[self.addr & 0x87]
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self.putcmd(self.addr_start, es, name, idx)
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elif self.cmd_digit > 1:
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name, idx, decoder = registers[self.addr & 0x87]
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if name == 'READ':
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value = self.read_value
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elif name == 'WRITE':
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value = self.write_value
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else:
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value = 0
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self.putreadwrite(self.addr_start, es, name, idx,
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decoder((self.addr >> 3) & 0x0f), value)
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if self.cs_asserted:
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self.cs_start = ss
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self.cmd_digit = 0
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self.read_value = 0
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self.write_value = 0
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