mirror of
https://github.com/DreamSourceLab/DSView.git
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454 lines
17 KiB
Python
454 lines
17 KiB
Python
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2020 Analog Devices Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 3 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sigrokdecode as srd
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from common.srdhelper import SrdIntEnum
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from .lists import *
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WORD_SIZE = 8
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class Channel():
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MISO, MOSI = range(2)
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class Operation():
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READ, WRITE = range(2)
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class BitType():
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ENABLE = {1: ['Enable %s', 'En %s', '%s '], 0: ['Disable %s', 'Dis %s', '!%s '],}
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SOURCE = {1: ['Involve %s', 'Inv %s', '%s'], 0: ['Not involve %s', 'Not inv %s', '!%s'],}
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INTERRUPT = {1: ['INT2 %s', 'I2: %s '], 0: ['INT1 %s', 'I1:%s '],}
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AC_DC = {1: ['%s ac', 'ac'], 0: ['%s dc', 'dc'],}
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UNUSED = {1: ['N/A'], 0: ['N/A'],}
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OTHER = 0
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class Bit():
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def __init__(self, name, type, values=None):
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self.value = 0
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self.name = name
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self.type = type
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self.values = values
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def set_value(self, value):
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self.value = value
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def get_bit_annotation(self):
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if self.type == BitType.OTHER:
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annotation = self.values[self.value].copy()
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else:
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annotation = self.type[self.value].copy()
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for index in range(len(annotation)):
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if '%s' in annotation[index]:
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annotation[index] = str(annotation[index] % self.name)
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return annotation
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Ann = SrdIntEnum.from_str('Ann', 'READ WRITE MB REG_ADDRESS REG_DATA WARNING')
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St = SrdIntEnum.from_str('St', 'IDLE ADDRESS_BYTE DATA')
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'adxl345'
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name = 'ADXL345'
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longname = 'Analog Devices ADXL345'
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desc = 'Analog Devices ADXL345 3-axis accelerometer.'
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license = 'gplv2+'
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inputs = ['spi']
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outputs = []
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tags = ['IC', 'Sensor']
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annotations = (
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('read', 'Read'),
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('write', 'Write'),
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('mb', 'Multiple bytes'),
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('reg-address', 'Register address'),
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('reg-data', 'Register data'),
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('warning', 'Warning'),
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)
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annotation_rows = (
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('reg', 'Registers', (Ann.READ, Ann.WRITE, Ann.MB, Ann.REG_ADDRESS)),
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('data', 'Data', (Ann.REG_DATA, Ann.WARNING)),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.mosi, self.miso = [], []
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self.reg = []
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self.operation = None
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self.address = 0
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self.data = -1
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self.state = St.IDLE
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self.ss, self.es = -1, -1
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self.samples_per_bit = 0
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def putx(self, data):
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self.put(self.ss, self.es, self.out_ann, data)
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def putb(self, data, index):
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start = self.ss + (self.samples_per_bit * index)
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self.put(start, start + self.samples_per_bit, self.out_ann, data)
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def putbs(self, data, start_index, stop_index):
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start_index = self.reverse_bit_index(start_index, WORD_SIZE)
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stop_index = self.reverse_bit_index(stop_index, WORD_SIZE)
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start = self.ss + (self.samples_per_bit * start_index)
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stop = start + (self.samples_per_bit * (stop_index - start_index + 1))
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self.put(start, stop, self.out_ann, data)
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def handle_reg_with_scaling_factor(self, data, factor, name, unit, error_msg):
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if data == 0 and error_msg is not None:
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self.putx([Ann.WARNING, error_msg])
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else:
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result = (data * factor) / 1000
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self.putx([Ann.REG_DATA, ['%s: %f %s' % (name, result, unit), '%f %s' % (result, unit)]])
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def handle_reg_bit_msg(self, bit, index, en_msg, dis_msg):
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self.putb([Ann.REG_DATA, [en_msg if bit else dis_msg]], index)
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def interpret_bits(self, data, bits):
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bits_values = []
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for offset in range(8):
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bits_values.insert(0, (data & (1 << offset)) >> offset)
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for index in range(len(bits)):
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if bits[index] is None:
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continue
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bit = bits[index]
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bit.set_value(bits_values[index])
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self.putb([Ann.REG_DATA, bit.get_bit_annotation()], index)
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return list(reversed(bits_values))
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def reverse_bit_index(self, index, word_size):
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return word_size - index - 1
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def get_decimal_number(self, bits, start_index, stop_index):
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number = 0
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interval = range(start_index, stop_index + 1, 1)
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for index, offset in zip(interval, range(len(interval))):
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bit = bits[index]
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number = number | (bit << offset)
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return number
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def get_axis_value(self, data, axis):
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if self.data != - 1:
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data <<= 8
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self.data |= data
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self.put(self.start_index, self.es, self.out_ann,
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[Ann.REG_DATA, ['%s: 0x%04X' % (axis, self.data), str(data)]])
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self.data = -1
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else:
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self.putx([Ann.REG_DATA, [str(data)]])
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def handle_reg_0x1d(self, data):
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self.handle_reg_with_scaling_factor(data, 62.5, 'Threshold', 'g',
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error_messages['undesirable'])
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def handle_reg_0x1e(self, data):
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self.handle_reg_with_scaling_factor(data, 15.6, 'OFSX', 'g', None)
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def handle_reg_0x1f(self, data):
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self.handle_reg_with_scaling_factor(data, 15.6, 'OFSY', 'g', None)
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def handle_reg_0x20(self, data):
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self.handle_reg_with_scaling_factor(data, 15.6, 'OFSZ', 'g', None)
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def handle_reg_0x21(self, data):
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self.handle_reg_with_scaling_factor(data, 0.625, 'Duration', 's',
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error_messages['dis_single_double'])
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def handle_reg_0x22(self, data):
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self.handle_reg_with_scaling_factor(data, 1.25, 'Latency', 's',
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error_messages['dis_double'])
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def handle_reg_0x23(self, data):
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self.handle_reg_with_scaling_factor(data, 1.25, 'Window', 's',
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error_messages['dis_double'])
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def handle_reg_0x24(self, data):
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self.handle_reg_0x1d(data)
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def handle_reg_0x25(self, data):
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self.handle_reg_0x1d(data)
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def handle_reg_0x26(self, data):
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self.handle_reg_with_scaling_factor(data, 1000, 'Time', 's',
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error_messages['interrupt'])
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def handle_reg_0x27(self, data):
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bits = [Bit('ACT', BitType.AC_DC),
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Bit('ACT_X', BitType.ENABLE),
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Bit('ACT_Y', BitType.ENABLE),
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Bit('ACT_Z', BitType.ENABLE),
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Bit('INACT', BitType.AC_DC),
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Bit('INACT_X', BitType.ENABLE),
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Bit('INACT_Y', BitType.ENABLE),
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Bit('INACT_Z', BitType.ENABLE)]
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self.interpret_bits(data, bits)
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def handle_reg_0x28(self, data):
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self.handle_reg_0x1d(data)
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def handle_reg_0x29(self, data):
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self.handle_reg_with_scaling_factor(data, 5, 'Time', 's',
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error_messages['undesirable'])
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def handle_reg_0x2a(self, data):
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bits = [Bit('', BitType.UNUSED),
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Bit('', BitType.UNUSED),
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Bit('', BitType.UNUSED),
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Bit('', BitType.UNUSED),
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Bit('', BitType.OTHER, {1: ['Suppressed', 'Suppr', 'S'],
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0: ['Unsuppressed', 'Unsuppr', 'Uns'],}),
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Bit('TAP_X', BitType.ENABLE),
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Bit('TAP_Y', BitType.ENABLE),
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Bit('TAP_Z', BitType.ENABLE)]
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self.interpret_bits(data, bits)
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def handle_reg_0x2b(self, data):
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bits = [Bit('', BitType.UNUSED),
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Bit('ACT_X', BitType.SOURCE),
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Bit('ACT_Y', BitType.SOURCE),
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Bit('ACT_Z', BitType.SOURCE),
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Bit('', BitType.OTHER, {1: ['Asleep', 'Asl'],
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0: ['Not asleep', 'Not asl', '!Asl'],}),
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Bit('TAP_X', BitType.SOURCE),
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Bit('TAP_Y', BitType.SOURCE),
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Bit('TAP_Z', BitType.SOURCE)]
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self.interpret_bits(data, bits)
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def handle_reg_0x2c(self, data):
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bits = [Bit('', BitType.UNUSED),
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Bit('', BitType.UNUSED),
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Bit('', BitType.UNUSED),
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Bit('', BitType.OTHER, {1: ['Reduce power', 'Reduce pw', 'Red pw'], 0: ['Normal operation', 'Normal op', 'Norm op'],})]
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bits_values = self.interpret_bits(data, bits)
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start_index, stop_index = 0, 3
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rate = self.get_decimal_number(bits_values, start_index, stop_index)
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self.putbs([Ann.REG_DATA, ['%f' % rate_code[rate]]], stop_index, start_index)
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def handle_reg_0x2d(self, data):
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bits = [Bit('', BitType.UNUSED),
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Bit('', BitType.UNUSED),
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Bit('', BitType.OTHER, {1: ['Link'], 0: ['Unlink'], }),
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Bit('AUTO_SLEEP', BitType.ENABLE),
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Bit('', BitType.OTHER, {1: ['Measurement mode', 'Measurement', 'Meas'], 0: ['Standby mode', 'Standby'], }),
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Bit('', BitType.OTHER, {1: ['Sleep mode', 'Sleep', 'Slp'], 0: ['Normal mode', 'Normal', 'Nrm'],})]
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bits_values = self.interpret_bits(data, bits)
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start_index, stop_index = 0, 1
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wakeup = self.get_decimal_number(bits_values, start_index, stop_index)
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frequency = 2 ** (~wakeup & 0x03)
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self.putbs([Ann.REG_DATA, ['%d Hz' % frequency]], stop_index, start_index)
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def handle_reg_0x2e(self, data):
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bits = [Bit('DATA_READY', BitType.ENABLE),
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Bit('SINGLE_TAP', BitType.ENABLE),
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Bit('DOUBLE_TAP', BitType.ENABLE),
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Bit('Activity', BitType.ENABLE),
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Bit('Inactivity', BitType.ENABLE),
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Bit('FREE_FALL', BitType.ENABLE),
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Bit('Watermark', BitType.ENABLE),
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Bit('Overrun', BitType.ENABLE)]
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self.interpret_bits(data, bits)
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def handle_reg_0x2f(self, data):
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bits = [Bit('DATA_READY', BitType.INTERRUPT),
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Bit('SINGLE_TAP', BitType.INTERRUPT),
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Bit('DOUBLE_TAP', BitType.INTERRUPT),
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Bit('Activity', BitType.INTERRUPT),
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Bit('Inactivity', BitType.INTERRUPT),
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Bit('FREE_FALL', BitType.INTERRUPT),
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Bit('Watermark', BitType.INTERRUPT),
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Bit('Overrun', BitType.INTERRUPT)]
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self.interpret_bits(data, bits)
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def handle_reg_0x30(self, data):
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bits = [Bit('DATA_READY', BitType.SOURCE),
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Bit('SINGLE_TAP', BitType.SOURCE),
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Bit('DOUBLE_TAP', BitType.SOURCE),
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Bit('Activity', BitType.SOURCE),
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Bit('Inactivity', BitType.SOURCE),
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Bit('FREE_FALL', BitType.SOURCE),
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Bit('Watermark', BitType.SOURCE),
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Bit('Overrun', BitType.SOURCE)]
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self.interpret_bits(data, bits)
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def handle_reg_0x31(self, data):
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bits = [Bit('SELF_TEST', BitType.ENABLE),
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Bit('', BitType.OTHER, {1: ['3-wire SPI', '3-SPI'], 0: ['4-wire SPI', '4-SPI'],}),
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Bit('', BitType.OTHER, {1: ['INT ACT LOW', 'INT LOW'], 0: ['INT ACT HIGH', 'INT HIGH'],}),
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Bit('', BitType.UNUSED),
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Bit('', BitType.OTHER, {1: ['Full resolution', 'Full res'], 0: ['10-bit mode', '10-bit'],}),
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Bit('', BitType.OTHER, {1: ['MSB mode', 'MSB'], 0: ['LSB mode', 'LSB'],})]
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bits_values = self.interpret_bits(data, bits)
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start_index, stop_index = 0, 1
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range_g = self.get_decimal_number(bits_values, start_index, stop_index)
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result = 2 ** (range_g + 1)
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self.putbs([Ann.REG_DATA, ['+/-%d g' % result]], stop_index, start_index)
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def handle_reg_0x32(self, data):
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self.data = data
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self.putx([Ann.REG_DATA, [str(data)]])
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def handle_reg_0x33(self, data):
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self.get_axis_value(data, 'X')
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def handle_reg_0x34(self, data):
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self.handle_reg_0x32(data)
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def handle_reg_0x35(self, data):
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self.get_axis_value(data, 'Y')
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def handle_reg_0x36(self, data):
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self.handle_reg_0x32(data)
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def handle_reg_0x37(self, data):
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self.get_axis_value(data, 'Z')
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def handle_reg_0x38(self, data):
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bits = [None,
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None,
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Bit('', BitType.OTHER, {1: ['Trig-INT2', 'INT2'], 0: ['Trig-INT1', 'INT1'], })]
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bits_values = self.interpret_bits(data, bits)
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start_index, stop_index = 6, 7
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fifo = self.get_decimal_number(bits_values, start_index, stop_index)
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self.putbs([Ann.REG_DATA, [fifo_modes[fifo]]], stop_index, start_index)
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start_index, stop_index = 0, 4
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samples = self.get_decimal_number(bits_values, start_index, stop_index)
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self.putbs([Ann.REG_DATA, ['Samples: %d' % samples, '%d' % samples]], stop_index, start_index)
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def handle_reg_0x39(self, data):
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bits = [Bit('', BitType.OTHER, {1: ['Triggered', 'Trigg'], 0: ['Not triggered', 'Not trigg'],}),
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Bit('', BitType.UNUSED)]
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bits_values = self.interpret_bits(data, bits)
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start_index, stop_index = 0, 5
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entries = self.get_decimal_number(bits_values, start_index, stop_index)
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self.putbs([Ann.REG_DATA, ['Entries: %d' % entries, '%d' % entries]], stop_index, start_index)
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def get_bit(self, channel):
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if (channel == Channel.MOSI and self.mosi is None) or \
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(channel == Channel.MISO and self.miso is None):
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raise Exception('No available data')
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mosi_bit, miso_bit = 0, 0
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if self.miso is not None:
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if len(self.mosi) < 0:
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raise Exception('No available data')
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miso_bit = self.miso.pop(0)
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if self.miso is not None:
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if len(self.miso) < 0:
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raise Exception('No available data')
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mosi_bit = self.mosi.pop(0)
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if channel == Channel.MOSI:
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return mosi_bit
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return miso_bit
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def decode(self, ss, es, data):
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ptype = data[0]
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if ptype == 'CS-CHANGE':
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cs_old, cs_new = data[1:]
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if cs_old is not None and cs_old == 1 and cs_new == 0:
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self.ss, self.es = ss, es
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self.state = St.ADDRESS_BYTE
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else:
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self.state = St.IDLE
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elif ptype == 'BITS':
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if data[1] is not None:
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self.mosi = list(reversed(data[1]))
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if data[2] is not None:
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self.miso = list(reversed(data[2]))
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if self.mosi is None and self.miso is None:
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return
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if self.state == St.ADDRESS_BYTE:
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# OPERATION BIT
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op_bit = self.get_bit(Channel.MOSI)
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self.put(op_bit[1], op_bit[2], self.out_ann,
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[Ann.READ if op_bit[0] else Ann.WRITE, operations[op_bit[0]]])
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self.operation = Operation.READ if op_bit[0] else Operation.WRITE
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# MULTIPLE-BYTE BIT
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mb_bit = self.get_bit(Channel.MOSI)
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self.put(mb_bit[1], mb_bit[2], self.out_ann, [Ann.MB, number_bytes[mb_bit[0]]])
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# REGISTER 6-BIT ADDRESS
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self.address = 0
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start_sample = self.mosi[0][1]
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addr_bit = []
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for i in range(6):
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addr_bit = self.get_bit(Channel.MOSI)
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self.address |= addr_bit[0]
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self.address <<= 1
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self.address >>= 1
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self.put(start_sample, addr_bit[2], self.out_ann,
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[Ann.REG_ADDRESS, ['ADDRESS: 0x%02X' % self.address, 'ADDR: 0x%02X'
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% self.address, '0x%02X' % self.address]])
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self.ss = -1
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self.state = St.DATA
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elif self.state == St.DATA:
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self.reg.extend(self.mosi if self.operation == Operation.WRITE else self.miso)
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self.mosi, self.miso = [], []
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if self.ss == -1:
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self.ss, self.es = self.reg[0][1], es
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self.samples_per_bit = self.reg[0][2] - self.ss
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if len(self.reg) < 8:
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return
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else:
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reg_value = 0
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reg_bit = []
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for offset in range(7, -1, -1):
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reg_bit = self.reg.pop(0)
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mask = reg_bit[0] << offset
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reg_value |= mask
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if self.address < 0x00 or self.address > 0x39:
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return
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if self.address in [0x32, 0x34, 0x36]:
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self.start_index = self.ss
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if 0x1D > self.address >= 0x00:
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self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, [str(self.address)]])
|
|
self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_DATA, [str(reg_value)]])
|
|
else:
|
|
self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, registers[self.address]])
|
|
handle_reg = getattr(self, 'handle_reg_0x%02x' % self.address)
|
|
handle_reg(reg_value)
|
|
|
|
self.reg = []
|
|
self.address += 1
|
|
self.ss = -1
|