mirror of
https://github.com/DreamSourceLab/DSView.git
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169 lines
5.9 KiB
Python
169 lines
5.9 KiB
Python
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2017 Marcus Comstedt <marcus@mc.pp.se>
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## Copyright (C) 2019 DreamSourceLab <support@dreamsourcelab.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sigrokdecode as srd
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step_wait_conds = (
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[{2: 'f'}, {0: 'l', 1: 'h'}],
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[{2: 'f'}, {0: 'h', 1: 'h'}, {1: 'l'}],
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[{2: 'f'}, {0: 'f'}, {1: 'l'}],
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[{2: 'f'}, {1: 'e'}],
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)
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'iec'
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name = 'IEC'
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longname = 'Commodore IEC bus'
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desc = 'Commodore serial IEEE-488 (IEC) bus protocol.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = []
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tags = ['PC', 'Retro computing']
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channels = (
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{'id': 'data', 'name': 'DATA', 'desc': 'Data I/O'},
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{'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
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{'id': 'atn', 'name': 'ATN', 'desc': 'Attention'},
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)
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optional_channels = (
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{'id': 'srq', 'name': 'SRQ', 'desc': 'Service request'},
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)
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annotations = (
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('items', 'Items'),
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('gpib', 'DAT/CMD'),
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('eoi', 'EOI'),
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)
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annotation_rows = (
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('bytes', 'Bytes', (0,)),
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('gpib', 'DAT/CMD', (1,)),
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('eoi', 'EOI', (2,)),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.saved_ATN = False
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self.saved_EOI = False
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self.ss_item = self.es_item = None
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self.step = 0
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self.bits = 0
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self.numbits = 0
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def putb(self, data):
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self.put(self.ss_item, self.es_item, self.out_ann, data)
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def handle_bits(self):
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# Output the saved item.
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dbyte = self.bits
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dATN = self.saved_ATN
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dEOI = self.saved_EOI
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self.es_item = self.samplenum
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self.putb([0, ['%02X' % dbyte]])
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# Encode item byte to GPIB convention.
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self.strgpib = ' '
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if dATN: # ATN, decode commands.
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# Note: Commands < 0x20 are not used on IEC bus.
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if dbyte == 0x01: self.strgpib = 'GTL'
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if dbyte == 0x04: self.strgpib = 'SDC'
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if dbyte == 0x05: self.strgpib = 'PPC'
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if dbyte == 0x08: self.strgpib = 'GET'
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if dbyte == 0x09: self.strgpib = 'TCT'
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if dbyte == 0x11: self.strgpib = 'LLO'
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if dbyte == 0x14: self.strgpib = 'DCL'
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if dbyte == 0x15: self.strgpib = 'PPU'
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if dbyte == 0x18: self.strgpib = 'SPE'
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if dbyte == 0x19: self.strgpib = 'SPD'
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if dbyte == 0x3f: self.strgpib = 'UNL'
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if dbyte == 0x5f: self.strgpib = 'UNT'
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if dbyte > 0x1f and dbyte < 0x3f: # Address listener.
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self.strgpib = 'L' + chr(dbyte + 0x10)
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if dbyte > 0x3f and dbyte < 0x5f: # Address talker.
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self.strgpib = 'T' + chr(dbyte - 0x10)
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if dbyte > 0x5f and dbyte < 0x70: # Channel reopen.
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self.strgpib = 'R' + chr(dbyte - 0x30)
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if dbyte > 0xdf and dbyte < 0xf0: # Channel close.
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self.strgpib = 'C' + chr(dbyte - 0xb0)
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if dbyte > 0xef: # Channel open.
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self.strgpib = 'O' + chr(dbyte - 0xc0)
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else:
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if dbyte > 0x1f and dbyte < 0x7f:
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self.strgpib = chr(dbyte)
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if dbyte == 0x0a:
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self.strgpib = 'LF'
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if dbyte == 0x0d:
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self.strgpib = 'CR'
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self.putb([1, [self.strgpib]])
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self.strEOI = ' '
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if dEOI:
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self.strEOI = 'EOI'
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self.putb([2, [self.strEOI]])
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def decode(self):
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while True:
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(data, clk, atn, srq) = self.wait(step_wait_conds[self.step])
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if (self.matched & (0b1 << 0)):
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# Falling edge on ATN, reset step.
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self.step = 0
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if self.step == 0:
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# Don't use self.matched_[1] here since we might come from
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# a step with different conds due to the code above.
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if data == 0 and clk == 1:
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# Rising edge on CLK while DATA is low: Ready to send.
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self.step = 1
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elif self.step == 1:
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if data == 1 and clk == 1:
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# Rising edge on DATA while CLK is high: Ready for data.
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self.ss_item = self.samplenum
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self.saved_ATN = not atn
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self.saved_EOI = False
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self.bits = 0
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self.numbits = 0
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self.step = 2
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elif clk == 0:
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# CLK low again, transfer aborted.
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self.step = 0
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elif self.step == 2:
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if data == 0 and clk == 1:
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# DATA goes low while CLK is still high, EOI confirmed.
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self.saved_EOI = True
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elif clk == 0:
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self.step = 3
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elif self.step == 3:
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if (self.matched & (0b1 << 1)):
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if clk == 1:
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# Rising edge on CLK; latch DATA.
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self.bits |= data << self.numbits
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elif clk == 0:
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# Falling edge on CLK; end of bit.
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self.numbits += 1
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if self.numbits == 8:
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self.handle_bits()
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self.step = 0
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