mirror of
https://github.com/DreamSourceLab/DSView.git
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206 lines
7.3 KiB
Python
206 lines
7.3 KiB
Python
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2019 Benedikt Otto <benedikt_o@web.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sigrokdecode as srd
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class SamplerateError(Exception):
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pass
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'ir_rc6'
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name = 'IR RC-6'
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longname = 'IR RC-6'
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desc = 'RC-6 infrared remote control protocol.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = []
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tags = ['IR']
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channels = (
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{'id': 'ir', 'name': 'IR', 'desc': 'IR data line'},
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)
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options = (
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{'id': 'polarity', 'desc': 'Polarity', 'default': 'auto',
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'values': ('auto', 'active-low', 'active-high')},
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)
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annotations = (
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('bit', 'Bit'),
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('sync', 'Sync'),
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('startbit', 'Startbit'),
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('field', 'Field'),
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('togglebit', 'Togglebit'),
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('address', 'Address'),
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('command', 'Command'),
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)
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annotation_rows = (
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('bits', 'Bits', (0,)),
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('fields', 'Fields', (1, 2, 3, 4, 5, 6)),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.samplerate = None
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self.edges, self.deltas, self.bits = [], [], []
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self.state = 'IDLE'
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self.mode = 0
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def metadata(self, key, value):
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if key == srd.SRD_CONF_SAMPLERATE:
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self.samplerate = value
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# One bit: 0.889ms (one half low, one half high).
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self.halfbit = int((self.samplerate * 0.000889) / 2.0)
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def putb(self, bit, data):
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self.put(bit[0], bit[1], self.out_ann, data)
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def putbits(self, bit1, bit2, data):
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self.put(bit1[0], bit2[1], self.out_ann, data)
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def putx(self, ss, es, data):
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self.put(ss, es, self.out_ann, data)
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def handle_bit(self):
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if len(self.bits) != 6:
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return
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if self.bits[0][2] == 8 and self.bits[0][3] == 1:
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self.putb(self.bits[0], [1, ['Synchronisation', 'Sync']])
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else:
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return
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if self.bits[1][3] == 1:
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self.putb(self.bits[1], [2, ['Startbit', 'Start']])
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else:
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return
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self.mode = sum([self.bits[2 + i][3] << (2 - i) for i in range(3)])
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self.putbits(self.bits[2], self.bits[4], [3, ['Field: %d' % self.mode]])
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self.putb(self.bits[5], [4, ['Toggle: %d' % self.bits[5][3]]])
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def handle_package(self):
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# Sync and start bits have to be 1.
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if self.bits[0][3] == 0 or self.bits[1][3] == 0:
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return
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if len(self.bits) <= 6:
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return
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if self.mode == 0 and len(self.bits) == 22: # Mode 0 standard
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value = sum([self.bits[6 + i][3] << (7 - i) for i in range(8)])
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self.putbits(self.bits[6], self.bits[13], [5, ['Address: %0.2X' % value]])
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value = sum([self.bits[14 + i][3] << (7 - i) for i in range(8)])
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self.putbits(self.bits[14], self.bits[21], [6, ['Data: %0.2X' % value]])
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self.bits = []
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if self.mode == 6 and len(self.bits) >= 15: # Mode 6
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if self.bits[6][3] == 0: # Short addr, Mode 6A
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value = sum([self.bits[6 + i][3] << (7 - i) for i in range(8)])
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self.putbits(self.bits[6], self.bits[13], [5, ['Address: %0.2X' % value]])
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num_data_bits = len(self.bits) - 14
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value = sum([self.bits[14 + i][3] << (num_data_bits - 1 - i) for i in range(num_data_bits)])
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self.putbits(self.bits[14], self.bits[-1], [6, ['Data: %X' % value]])
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self.bits = []
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elif len(self.bits) >= 23: # Long addr, Mode 6B
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value = sum([self.bits[6 + i][3] << (15 - i) for i in range(16)])
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self.putbits(self.bits[6], self.bits[21], [5, ['Address: %0.2X' % value]])
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num_data_bits = len(self.bits) - 22
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value = sum([self.bits[22 + i][3] << (num_data_bits - 1 - i) for i in range(num_data_bits)])
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self.putbits(self.bits[22], self.bits[-1], [6, ['Data: %X' % value]])
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self.bits = []
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def decode(self):
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if not self.samplerate:
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raise SamplerateError('Cannot decode without samplerate.')
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value = 0
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num_edges = -1
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self.invert = False
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while True:
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conditions = [{0: 'e'}]
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if self.state == 'DATA':
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conditions.append({'skip': self.halfbit * 6})
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(self.ir,) = self.wait(conditions)
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if len(conditions) == 2:
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if self.matched & 0b10:
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self.state = 'IDLE'
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self.edges.append(self.samplenum)
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if len(self.edges) < 2:
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continue
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delta = (self.edges[-1] - self.edges[-2]) / self.halfbit
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delta = int(delta + 0.5)
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self.deltas.append(delta)
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if len(self.deltas) < 2:
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continue
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if self.deltas[-2:] == [6, 2]:
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self.state = 'SYNC'
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num_edges = 0
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self.bits = []
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if self.options['polarity'] == 'auto':
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value = 1
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else:
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value = self.ir if self.options['polarity'] == 'active-high' else 1 - self.ir
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self.bits.append((self.edges[-3], self.edges[-1], 8, value))
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self.invert = self.ir == 0
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self.putb(self.bits[-1], [0, ['%d' % value]]) # Add bit.
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if (num_edges % 2) == 0: # Only count every second edge.
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if self.deltas[-2] in [1, 2, 3] and self.deltas[-1] in [1, 2, 3, 6]:
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self.state = 'DATA'
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if self.deltas[-2] != self.deltas[-1]:
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# Insert border between 2 bits.
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self.edges.insert(-1, self.edges[-2] + self.deltas[-2] * self.halfbit)
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total = self.deltas[-1]
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self.deltas[-1] = self.deltas[-2]
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self.deltas.append(total - self.deltas[-1])
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self.bits.append((self.edges[-4], self.edges[-2], self.deltas[-2] * 2, value))
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num_edges += 1
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else:
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self.bits.append((self.edges[-3], self.edges[-1], self.deltas[-1] * 2, value))
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self.putb(self.bits[-1], [0, ['%d' % value]]) # Add bit.
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if len(self.bits) > 0:
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self.handle_bit()
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if self.state == 'IDLE':
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self.handle_package()
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if self.options['polarity'] == 'auto':
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value = self.ir if self.invert else 1 - self.ir
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else:
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value = self.ir if self.options['polarity'] == 'active-low' else 1 - self.ir
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num_edges += 1
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