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357 lines
14 KiB
Python
357 lines
14 KiB
Python
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
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## Copyright (C) 2019 DreamSourceLab <support@dreamsourcelab.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sigrokdecode as srd
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from collections import namedtuple
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Data = namedtuple('Data', ['ss', 'es', 'val'])
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'''
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OUTPUT_PYTHON format:
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Packet:
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[<ptype>, <data1>, <data2>]
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<ptype>:
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- 'DATA': <data1> contains the MOSI data, <data2> contains the MISO data.
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The data is _usually_ 8 bits (but can also be fewer or more bits).
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Both data items are Python numbers (not strings), or None if the respective
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channel was not supplied.
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- 'BITS': <data1>/<data2> contain a list of bit values in this MOSI/MISO data
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item, and for each of those also their respective start-/endsample numbers.
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- 'CS-CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
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Both data items are Python numbers (0/1), not strings. At the beginning of
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the decoding a packet is generated with <data1> = None and <data2> being the
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initial state of the CS# pin or None if the chip select pin is not supplied.
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- 'TRANSFER': <data1>/<data2> contain a list of Data() namedtuples for each
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byte transferred during this block of CS# asserted time. Each Data() has
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fields ss, es, and val.
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Examples:
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['CS-CHANGE', None, 1]
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['CS-CHANGE', 1, 0]
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['DATA', 0xff, 0x3a]
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['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88],
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[1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]],
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[[0, 80, 82], [1, 83, 84], [0, 85, 86], [1, 87, 88],
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[1, 89, 90], [1, 91, 92], [0, 93, 94], [0, 95, 96]]]
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['DATA', 0x65, 0x00]
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['DATA', 0xa8, None]
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['DATA', None, 0x55]
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['CS-CHANGE', 0, 1]
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['TRANSFER', [Data(ss=80, es=96, val=0xff), ...],
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[Data(ss=80, es=96, val=0x3a), ...]]
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'''
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# Key: (CPOL, CPHA). Value: SPI mode.
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# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
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# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
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spi_mode = {
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(0, 0): 0, # Mode 0
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(0, 1): 1, # Mode 1
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(1, 0): 2, # Mode 2
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(1, 1): 3, # Mode 3
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}
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class ChannelError(Exception):
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pass
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class Decoder(srd.Decoder):
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api_version = 3
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id = '1:spi'
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name = '1:SPI'
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longname = 'Serial Peripheral Interface'
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desc = 'Full-duplex, synchronous, serial bus.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = ['spi']
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tags = ['Embedded/industrial']
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channels = (
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{'id': 'clk', 'type': 0, 'name': 'CLK', 'desc': 'Clock' ,'idn':'dec_1spi_chan_clk'},
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)
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optional_channels = (
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{'id': 'miso', 'type': 107, 'name': 'MISO', 'desc': 'Master in, slave out', 'idn':'dec_1spi_opt_chan_miso'},
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{'id': 'mosi', 'type': 109, 'name': 'MOSI', 'desc': 'Master out, slave in', 'idn':'dec_1spi_opt_chan_mosi'},
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{'id': 'cs', 'type': -1, 'name': 'CS#', 'desc': 'Chip-select', 'idn':'dec_1spi_opt_chan_cs'},
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)
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options = (
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{'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low',
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'values': ('active-low', 'active-high'), 'idn':'dec_1spi_opt_cs_pol'},
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{'id': 'cpol', 'desc': 'Clock polarity (CPOL)', 'default': 0,
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'values': (0, 1) , 'idn':'dec_1spi_opt_cpol'},
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{'id': 'cpha', 'desc': 'Clock phase (CPHA)', 'default': 0,
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'values': (0, 1), 'idn':'dec_1spi_opt_cpha'},
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{'id': 'bitorder', 'desc': 'Bit order',
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'default': 'msb-first', 'values': ('msb-first', 'lsb-first'), 'idn':'dec_1spi_opt_bitorder'},
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{'id': 'wordsize', 'desc': 'Word size', 'default': 8,
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'values': tuple(range(5,129,1)), 'idn':'dec_1spi_opt_wordsize'},
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{'id': 'frame', 'desc': 'Frame Decoder', 'default': 'no',
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'values': ('yes', 'no'), 'idn':'dec_1spi_opt_frame'},
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)
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annotations = (
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('106', 'miso-data', 'MISO data'),
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('108', 'mosi-data', 'MOSI data'),
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('207', 'miso-bits', 'MISO bits'),
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('209', 'mosi-bits', 'MOSI bits'),
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('1000', 'warnings', 'Human-readable warnings'),
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('6', 'miso-transfer', 'MISO transfer'),
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('8', 'mosi-transfer', 'MOSI transfer'),
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)
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annotation_rows = (
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('miso-bits', 'MISO bits', (2,)),
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('miso-data', 'MISO data', (0,)),
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('miso-transfer', 'MISO transfer', (5,)),
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('mosi-bits', 'MOSI bits', (3,)),
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('mosi-data', 'MOSI data', (1,)),
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('mosi-transfer', 'MOSI transfer', (6,)),
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('other', 'Other', (4,)),
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)
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binary = (
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('miso', 'MISO'),
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('mosi', 'MOSI'),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.samplerate = None
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self.bitcount = 0
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self.misodata = self.mosidata = 0
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self.misobits = []
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self.mosibits = []
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self.misobytes = []
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self.mosibytes = []
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self.ss_block = -1
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self.samplenum = -1
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self.ss_transfer = -1
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self.cs_was_deasserted = False
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self.have_cs = self.have_miso = self.have_mosi = None
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def start(self):
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self.out_python = self.register(srd.OUTPUT_PYTHON)
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self.out_ann = self.register(srd.OUTPUT_ANN)
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self.out_binary = self.register(srd.OUTPUT_BINARY)
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self.out_bitrate = self.register(srd.OUTPUT_META,
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meta=(int, 'Bitrate', 'Bitrate during transfers'))
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self.bw = (self.options['wordsize'] + 7) // 8
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def metadata(self, key, value):
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if key == srd.SRD_CONF_SAMPLERATE:
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self.samplerate = value
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def putw(self, data):
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self.put(self.ss_block, self.samplenum, self.out_ann, data)
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def putdata(self, frame):
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# Pass MISO and MOSI bits and then data to the next PD up the stack.
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so = self.misodata if self.have_miso else None
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si = self.mosidata if self.have_mosi else None
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so_bits = self.misobits if self.have_miso else None
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si_bits = self.mosibits if self.have_mosi else None
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if self.have_miso:
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ss, es = self.misobits[-1][1], self.misobits[0][2]
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bdata = so.to_bytes(self.bw, byteorder='big')
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self.put(ss, es, self.out_binary, [0, bdata])
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if self.have_mosi:
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ss, es = self.mosibits[-1][1], self.mosibits[0][2]
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bdata = si.to_bytes(self.bw, byteorder='big')
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self.put(ss, es, self.out_binary, [1, bdata])
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self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
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self.put(ss, es, self.out_python, ['DATA', si, so])
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if frame:
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if self.have_miso:
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self.misobytes.append(Data(ss=ss, es=es, val=so))
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if self.have_mosi:
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self.mosibytes.append(Data(ss=ss, es=es, val=si))
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# Bit annotations.
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if self.have_miso:
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blen = len(self.misobits)
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for i in range(0, blen):
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bit = self.misobits[blen-i-1]
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self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]])
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if self.have_mosi:
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blen = len(self.mosibits)
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for i in range(0, blen):
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bit = self.mosibits[blen-i-1]
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self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]])
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# Dataword annotations.
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if self.have_miso:
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self.put(ss, es, self.out_ann, [0, ['@%02X' % self.misodata]])
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if self.have_mosi:
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self.put(ss, es, self.out_ann, [1, ['@%02X' % self.mosidata]])
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def reset_decoder_state(self):
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self.misodata = 0 if self.have_miso else None
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self.mosidata = 0 if self.have_mosi else None
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self.misobits = [] if self.have_miso else None
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self.mosibits = [] if self.have_mosi else None
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self.bitcount = 0
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def cs_asserted(self, cs):
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active_low = (self.options['cs_polarity'] == 'active-low')
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return (cs == 0) if active_low else (cs == 1)
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def handle_bit(self, miso, mosi, clk, cs, frame):
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# If this is the first bit of a dataword, save its sample number.
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if self.bitcount == 0:
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self.ss_block = self.samplenum
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self.cs_was_deasserted = \
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not self.cs_asserted(cs) if self.have_cs else False
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ws = self.options['wordsize']
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bo = self.options['bitorder']
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# Receive MISO bit into our shift register.
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if self.have_miso:
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if bo == 'msb-first':
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self.misodata |= miso << (ws - 1 - self.bitcount)
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else:
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self.misodata |= miso << self.bitcount
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# Receive MOSI bit into our shift register.
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if self.have_mosi:
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if bo == 'msb-first':
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self.mosidata |= mosi << (ws - 1 - self.bitcount)
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else:
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self.mosidata |= mosi << self.bitcount
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# Guesstimate the endsample for this bit (can be overridden below).
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es = self.samplenum
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if self.bitcount > 0:
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if self.have_miso:
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es += self.samplenum - self.misobits[0][1]
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elif self.have_mosi:
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es += self.samplenum - self.mosibits[0][1]
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if self.have_miso:
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self.misobits.insert(0, [miso, self.samplenum, es])
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if self.have_mosi:
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self.mosibits.insert(0, [mosi, self.samplenum, es])
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if self.bitcount > 0 and self.have_miso:
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self.misobits[1][2] = self.samplenum
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if self.bitcount > 0 and self.have_mosi:
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self.mosibits[1][2] = self.samplenum
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self.bitcount += 1
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# Continue to receive if not enough bits were received, yet.
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if self.bitcount != ws:
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return
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self.putdata(frame)
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# Meta bitrate.
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if self.samplerate:
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elapsed = 1 / float(self.samplerate)
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elapsed *= (self.samplenum - self.ss_block + 1)
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bitrate = int(1 / elapsed * ws)
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self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate)
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if self.have_cs and self.cs_was_deasserted:
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self.putw([4, ['CS# was deasserted during this data word!']])
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self.reset_decoder_state()
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def find_clk_edge(self, miso, mosi, clk, cs, first, frame):
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if self.have_cs and (first or (self.matched & (0b1 << self.have_cs))):
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# Send all CS# pin value changes.
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oldcs = None if first else 1 - cs
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self.put(self.samplenum, self.samplenum, self.out_python,
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['CS-CHANGE', oldcs, cs])
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if frame:
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if self.cs_asserted(cs):
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self.ss_transfer = self.samplenum
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self.misobytes = []
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self.mosibytes = []
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elif self.ss_transfer != -1:
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if self.have_miso:
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self.put(self.ss_transfer, self.samplenum, self.out_ann,
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[5, ['@' + ' '.join(format(x.val, '02X') for x in self.misobytes)]])
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if self.have_mosi:
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self.put(self.ss_transfer, self.samplenum, self.out_ann,
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[6, ['@' + ' '.join(format(x.val, '02X') for x in self.mosibytes)]])
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self.put(self.ss_transfer, self.samplenum, self.out_python,
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['TRANSFER', self.mosibytes, self.misobytes])
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# Reset decoder state when CS# changes (and the CS# pin is used).
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self.reset_decoder_state()
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# We only care about samples if CS# is asserted.
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if self.have_cs and not self.cs_asserted(cs):
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return
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# Ignore sample if the clock pin hasn't changed.
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if first or not (self.matched & (0b1 << 0)):
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return
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# Found the correct clock edge, now get the SPI bit(s).
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self.handle_bit(miso, mosi, clk, cs, frame)
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def decode(self):
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# The CLK input is mandatory. Other signals are (individually)
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# optional. Yet either MISO or MOSI (or both) must be provided.
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# Tell stacked decoders when we don't have a CS# signal.
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if not self.has_channel(0):
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raise ChannelError('CLK pin required.')
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self.have_miso = self.has_channel(1)
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self.have_mosi = self.has_channel(2)
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if not self.have_miso and not self.have_mosi:
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raise ChannelError('Either MISO or MOSI (or both) pins required.')
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self.have_cs = self.has_channel(3)
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if not self.have_cs:
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self.put(0, 0, self.out_python, ['CS-CHANGE', None, None])
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frame = self.options['frame'] == 'yes'
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# We want all CLK changes. We want all CS changes if CS is used.
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# Map 'have_cs' from boolean to an integer index. This simplifies
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# evaluation in other locations.
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# Sample data on rising/falling clock edge (depends on mode).
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mode = spi_mode[self.options['cpol'], self.options['cpha']]
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if mode == 0 or mode == 3: # Sample on rising clock edge
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wait_cond = [{0: 'r'}]
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else: # Sample on falling clock edge
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wait_cond = [{0: 'f'}]
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if self.have_cs:
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self.have_cs = len(wait_cond)
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wait_cond.append({3: 'e'})
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# "Pixel compatibility" with the v2 implementation. Grab and
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# process the very first sample before checking for edges. The
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# previous implementation did this by seeding old values with
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# None, which led to an immediate "change" in comparison.
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(clk, miso, mosi, cs) = self.wait({})
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self.find_clk_edge(miso, mosi, clk, cs, True, frame)
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while True:
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(clk, miso, mosi, cs) = self.wait(wait_cond)
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self.find_clk_edge(miso, mosi, clk, cs, False, frame)
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