mirror of
https://github.com/DreamSourceLab/DSView.git
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182 lines
4.1 KiB
C
182 lines
4.1 KiB
C
/*
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* This file is part of the libsigrok project.
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*
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* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBDSL_HARDWARE_COMMAND_H
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#define LIBDSL_HARDWARE_COMMAND_H
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#include <glib.h>
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#include "../../libsigrok-internal.h"
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/* Protocol commands */
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#define CMD_CTL_WR 0xb0
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#define CMD_CTL_RD_PRE 0xb1
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#define CMD_CTL_RD 0xb2
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// read only
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#define bmGPIF_DONE (1 << 7)
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#define bmFPGA_DONE (1 << 6)
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#define bmFPGA_INIT_B (1 << 5)
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// write only
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#define bmCH_CH0 (1 << 7)
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#define bmCH_COM (1 << 6)
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#define bmCH_CH1 (1 << 5)
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// read/write
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#define bmSYS_OVERFLOW (1 << 4)
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#define bmSYS_CLR (1 << 3)
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#define bmSYS_EN (1 << 2)
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#define bmLED_RED (1 << 1)
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#define bmLED_GREEN (1 << 0)
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#define bmWR_PROG_B (1 << 2)
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#define bmWR_INTRDY (1 << 7)
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#define bmWR_WORDWIDE (1 << 0)
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#define VTH_ADDR 0x78
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#define CTR1_ADDR 0x71
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#define CTR0_ADDR 0x70
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#define COMB_ADDR 0x68
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#define EI2C_ADDR 0x60
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#define ADCC_ADDR 0x48
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#define HDL_VERSION_ADDR 0x04
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#define EI2C_CTR_OFF 0x2
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#define EI2C_RXR_OFF 0x3
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#define EI2C_SR_OFF 0x4
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#define EI2C_TXR_OFF 0x3
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#define EI2C_CR_OFF 0x4
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#define EI2C_SEL_OFF 0x7
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#define bmEI2C_EN (1 << 7)
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#define bmEI2C_STA (1 << 7)
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#define bmEI2C_STO (1 << 6)
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#define bmEI2C_RD (1 << 5)
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#define bmEI2C_WR (1 << 4)
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#define bmEI2C_NACK (1 << 3)
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#define bmEI2C_RXNACK (1 << 7)
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#define bmEI2C_TIP (1 << 1)
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#define EI2C_AWR 0x82
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#define EI2C_ARD 0x83
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enum {
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DSL_CTL_FW_VERSION = 0,
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DSL_CTL_REVID_VERSION = 1,
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DSL_CTL_HW_STATUS = 2,
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DSL_CTL_PROG_B = 3,
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DSL_CTL_SYS = 4,
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DSL_CTL_LED = 5,
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DSL_CTL_INTRDY = 6,
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DSL_CTL_WORDWIDE = 7,
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DSL_CTL_START = 8,
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DSL_CTL_STOP = 9,
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DSL_CTL_BULK_WR = 10,
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DSL_CTL_REG = 11,
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DSL_CTL_NVM = 12,
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DSL_CTL_I2C_DSO = 13,
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DSL_CTL_I2C_REG = 14,
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DSL_CTL_I2C_STATUS = 15,
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DSL_CTL_DSO_EN0 = 16,
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DSL_CTL_DSO_DC0 = 17,
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DSL_CTL_DSO_ATT0 = 18,
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DSL_CTL_DSO_EN1 = 19,
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DSL_CTL_DSO_DC1 = 20,
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DSL_CTL_DSO_ATT1 = 21,
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DSL_CTL_AWG_WR = 22,
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DSL_CTL_I2C_PROBE = 23,
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DSL_CTL_I2C_EXT = 24,
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};
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#pragma pack(push, 1) // byte align
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struct version_info {
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uint8_t major;
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uint8_t minor;
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};
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struct cmd_zero_info {
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uint8_t zero_addr;
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uint8_t voff0;
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uint8_t voff1;
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uint8_t voff2;
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uint8_t voff3;
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uint8_t voff4;
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uint8_t voff5;
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uint8_t voff6;
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uint8_t voff7;
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uint8_t voff8;
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uint8_t voff9;
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uint8_t voff10;
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uint8_t voff11;
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uint8_t voff12;
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uint8_t voff13;
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uint8_t voff14;
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uint8_t voff15;
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uint8_t diff0;
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uint8_t diff1;
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uint8_t trans0;
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uint8_t trans1;
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uint8_t comb_comp;
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uint8_t fgain0_code;
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uint8_t fgain1_code;
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uint8_t fgain2_code;
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uint8_t fgain3_code;
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uint8_t comb_fgain0_code;
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uint8_t comb_fgain1_code;
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uint8_t comb_fgain2_code;
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uint8_t comb_fgain3_code;
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};
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struct cmd_vga_info {
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uint8_t vga_addr;
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uint16_t vga0;
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uint16_t vga1;
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uint16_t vga2;
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uint16_t vga3;
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uint16_t vga4;
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uint16_t vga5;
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uint16_t vga6;
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uint16_t vga7;
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};
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struct ctl_header {
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uint8_t dest;
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uint16_t offset;
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uint8_t size;
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};
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struct ctl_wr_cmd {
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struct ctl_header header;
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uint8_t data[60];
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};
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struct ctl_rd_cmd {
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struct ctl_header header;
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uint8_t *data;
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};
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#pragma pack(pop)
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SR_PRIV int command_ctl_wr(libusb_device_handle *devhdl, struct ctl_wr_cmd cmd);
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SR_PRIV int command_ctl_rd(libusb_device_handle *devhdl, struct ctl_rd_cmd cmd);
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#endif
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