mirror of
https://github.com/DreamSourceLab/DSView.git
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211 lines
8.1 KiB
Python
Executable File
211 lines
8.1 KiB
Python
Executable File
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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import sigrokdecode as srd
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dacs = {
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0: 'DACA',
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1: 'DACB',
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2: 'DACC',
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3: 'DACD',
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}
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class Decoder(srd.Decoder):
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api_version = 2
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id = 'tlc5620'
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name = 'TI TLC5620'
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longname = 'Texas Instruments TLC5620'
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desc = 'Texas Instruments TLC5620 8-bit quad DAC.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = ['tlc5620']
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channels = (
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{'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'},
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{'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'},
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)
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optional_channels = (
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{'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'},
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{'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'},
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)
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options = (
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{'id': 'vref_a', 'desc': 'Reference voltage DACA (V)', 'default': 3.3},
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{'id': 'vref_b', 'desc': 'Reference voltage DACB (V)', 'default': 3.3},
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{'id': 'vref_c', 'desc': 'Reference voltage DACC (V)', 'default': 3.3},
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{'id': 'vref_d', 'desc': 'Reference voltage DACD (V)', 'default': 3.3},
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)
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annotations = (
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('dac-select', 'DAC select'),
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('gain', 'Gain'),
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('value', 'DAC value'),
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('data-latch', 'Data latch point'),
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('ldac-fall', 'LDAC falling edge'),
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('bit', 'Bit'),
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('reg-write', 'Register write'),
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('voltage-update', 'Voltage update'),
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('voltage-update-all', 'Voltage update (all DACs)'),
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('invalid-cmd', 'Invalid command'),
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)
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annotation_rows = (
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('bits', 'Bits', (5,)),
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('fields', 'Fields', (0, 1, 2)),
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('registers', 'Registers', (6, 7)),
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('voltage-updates', 'Voltage updates', (8,)),
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('events', 'Events', (3, 4)),
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('errors', 'Errors', (9,)),
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)
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def __init__(self):
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self.oldpins = self.oldclk = self.oldload = self.oldldac = None
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self.bits = []
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self.ss_dac_first = None
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self.ss_dac = self.es_dac = 0
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self.ss_gain = self.es_gain = 0
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self.ss_value = self.es_value = 0
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self.dac_select = self.gain = self.dac_value = None
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self.dacval = {'A': '?', 'B': '?', 'C': '?', 'D': '?'}
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self.gains = {'A': '?', 'B': '?', 'C': '?', 'D': '?'}
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def handle_11bits(self):
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# Only look at the last 11 bits, the rest is ignored by the TLC5620.
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if len(self.bits) > 11:
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self.bits = self.bits[-11:]
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# If there are less than 11 bits, something is probably wrong.
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if len(self.bits) < 11:
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ss, es = self.samplenum, self.samplenum
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if len(self.bits) >= 2:
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ss = self.bits[0][1]
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es = self.bits[-1][1] + (self.bits[1][1] - self.bits[0][1])
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self.put(ss, es, self.out_ann, [9, ['Command too short']])
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self.bits = []
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return False
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self.ss_dac = self.bits[0][1]
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self.es_dac = self.ss_gain = self.bits[2][1]
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self.es_gain = self.ss_value = self.bits[3][1]
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self.clock_width = self.es_gain - self.ss_gain
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self.es_value = self.bits[10][1] + self.clock_width # Guessed.
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if self.ss_dac_first is None:
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self.ss_dac_first = self.ss_dac
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s = ''.join(str(i[0]) for i in self.bits[:2])
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self.dac_select = s = dacs[int(s, 2)]
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self.put(self.ss_dac, self.es_dac, self.out_ann,
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[0, ['DAC select: %s' % s, 'DAC sel: %s' % s,
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'DAC: %s' % s, 'D: %s' % s, s, s[3]]])
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self.gain = g = 1 + self.bits[2][0]
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self.put(self.ss_gain, self.es_gain, self.out_ann,
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[1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]])
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s = ''.join(str(i[0]) for i in self.bits[3:])
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self.dac_value = v = int(s, 2)
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self.put(self.ss_value, self.es_value, self.out_ann,
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[2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v,
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'V: %d' % v, '%d' % v]])
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# Emit an annotation for each bit.
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for i in range(1, 11):
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self.put(self.bits[i - 1][1], self.bits[i][1], self.out_ann,
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[5, [str(self.bits[i - 1][0])]])
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self.put(self.bits[10][1], self.bits[10][1] + self.clock_width,
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self.out_ann, [5, [str(self.bits[10][0])]])
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self.bits = []
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return True
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def handle_falling_edge_load(self):
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if not self.handle_11bits():
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return
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s, v, g = self.dac_select, self.dac_value, self.gain
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self.put(self.samplenum, self.samplenum, self.out_ann,
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[3, ['Falling edge on LOAD', 'LOAD fall', 'F']])
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vref = self.options['vref_%s' % self.dac_select[3].lower()]
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v = '%.2fV' % (vref * (v / 256) * self.gain)
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if self.ldac == 0:
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# If LDAC is low, the voltage is set immediately.
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self.put(self.ss_dac, self.es_value, self.out_ann,
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[7, ['Setting %s voltage to %s' % (s, v),
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'%s=%s' % (s, v)]])
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else:
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# If LDAC is high, the voltage is not set immediately, but rather
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# stored in a register. When LDAC goes low all four DAC voltages
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# (DAC A/B/C/D) will be set at the same time.
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self.put(self.ss_dac, self.es_value, self.out_ann,
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[6, ['Setting %s register value to %s' % \
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(s, v), '%s=%s' % (s, v)]])
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# Save the last value the respective DAC was set to.
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self.dacval[self.dac_select[-1]] = str(self.dac_value)
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self.gains[self.dac_select[-1]] = self.gain
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def handle_falling_edge_ldac(self):
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self.put(self.samplenum, self.samplenum, self.out_ann,
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[4, ['Falling edge on LDAC', 'LDAC fall', 'LDAC', 'L']])
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# Don't emit any annotations if we didn't see any register writes.
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if self.ss_dac_first is None:
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return
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# Calculate voltages based on Vref and the per-DAC gain.
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dacval = {}
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for key, val in self.dacval.items():
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if val == '?':
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dacval[key] = '?'
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else:
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vref = self.options['vref_%s' % key.lower()]
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v = vref * (int(val) / 256) * self.gains[key]
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dacval[key] = '%.2fV' % v
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s = ''.join(['DAC%s=%s ' % (d, dacval[d]) for d in 'ABCD']).strip()
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self.put(self.ss_dac_first, self.samplenum, self.out_ann,
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[8, ['Updating voltages: %s' % s, s, s.replace('DAC', '')]])
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self.ss_dac_first = None
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def handle_new_dac_bit(self):
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self.bits.append([self.datapin, self.samplenum])
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def decode(self, ss, es, data):
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for (self.samplenum, pins) in data:
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data.itercnt += 1
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# Ignore identical samples early on (for performance reasons).
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if self.oldpins == pins:
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continue
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self.oldpins, (clk, self.datapin, load, ldac) = pins, pins
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self.ldac = ldac
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# DATA is shifted in the DAC on the falling CLK edge (MSB-first).
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# A falling edge of LOAD will latch the data.
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if self.oldload == 1 and load == 0:
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self.handle_falling_edge_load()
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if self.oldldac == 1 and ldac == 0:
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self.handle_falling_edge_ldac()
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if self.oldclk == 1 and clk == 0:
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self.handle_new_dac_bit()
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self.oldclk = clk
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self.oldload = load
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self.oldldac = ldac
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