mirror of
https://github.com/DreamSourceLab/DSView.git
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245 lines
9.4 KiB
Python
245 lines
9.4 KiB
Python
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2015 Josef Gajdusek <atx@atx.name>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sigrokdecode as srd
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import operator
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import collections
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from functools import reduce
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end_codes = (
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'Unknown',
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'Charge Complete',
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'Internal Fault',
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'Over Temperature',
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'Over Voltage',
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'Over Current',
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'Battery Failure',
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'Reconfigure',
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'No Response',
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)
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class SamplerateError(Exception):
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pass
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def calc_checksum(packet):
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return reduce(operator.xor, packet[:-1])
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def bits_to_uint(bits):
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# LSB first
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return reduce(lambda i, v: (i >> 1) | (v << (len(bits) - 1)), bits, 0)
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'qi'
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name = 'Qi'
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longname = 'Qi charger protocol'
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desc = 'Protocol used by Qi receiver.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = []
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tags = ['Embedded/industrial', 'Wireless/RF']
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channels = (
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{'id': 'qi', 'name': 'Qi', 'desc': 'Demodulated Qi data line'},
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)
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annotations = (
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('bits', 'Bits'),
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('bytes-errors', 'Bit errors'),
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('bytes-start', 'Start bits'),
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('bytes-info', 'Info bits'),
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('bytes-data', 'Data bytes'),
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('packets-data', 'Packet data'),
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('packets-checksum-ok', 'Packet checksum'),
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('packets-checksum-err', 'Packet checksum'),
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)
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annotation_rows = (
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('bits', 'Bits', (0,)),
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('bytes', 'Bytes', (1, 2, 3, 4)),
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('packets', 'Packets', (5, 6, 7)),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.samplerate = None
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self.reset_variables()
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def reset_variables(self):
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self.counter = 0
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self.prev = None
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self.state = 'IDLE'
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self.lastbit = 0
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self.bytestart = 0
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self.deq = collections.deque(maxlen = 2)
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self.bits = []
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self.bitsi = [0]
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self.bytesi = []
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self.packet = []
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def metadata(self, key, value):
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if key == srd.SRD_CONF_SAMPLERATE:
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self.samplerate = value
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self.bit_width = float(self.samplerate) / 2e3
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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self.reset_variables()
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def packet_len(self, byte):
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if 0x00 <= byte <= 0x1f:
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return int(1 + (byte - 0) / 32)
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if 0x20 <= byte <= 0x7f:
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return int(2 + (byte - 32) / 16)
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if 0x80 <= byte <= 0xdf:
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return int(8 + (byte - 128) / 8)
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if 0xe0 <= byte <= 0xff:
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return int(20 + (byte - 224) / 4)
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def in_tolerance(self, l):
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return (0.75 * self.bit_width) < l < (1.25 * self.bit_width)
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def putp(self, data):
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self.put(self.bytesi[0], self.bytesi[-1], self.out_ann, [5, data])
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def process_packet(self):
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if self.packet[0] == 0x01: # Signal Strength
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self.putp(['Signal Strength: %d' % self.packet[1],
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'SS: %d' % self.packet[1], 'SS'])
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elif self.packet[0] == 0x02: # End Power Transfer
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reason = end_codes[self.packet[1]] if self.packet[1] < len(end_codes) else 'Reserved'
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self.putp(['End Power Transfer: %s' % reason,
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'EPT: %s' % reason, 'EPT'])
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elif self.packet[0] == 0x03: # Control Error
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val = self.packet[1] if self.packet[1] < 128 else (self.packet[1] & 0x7f) - 128
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self.putp(['Control Error: %d' % val, 'CE: %d' % val, 'CE'])
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elif self.packet[0] == 0x04: # Received Power
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self.putp(['Received Power: %d' % self.packet[1],
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'RP: %d' % self.packet[1], 'RP'])
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elif self.packet[0] == 0x05: # Charge Status
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self.putp(['Charge Status: %d' % self.packet[1],
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'CS: %d' % self.packet[1], 'CS'])
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elif self.packet[0] == 0x06: # Power Control Hold-off
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self.putp(['Power Control Hold-off: %dms' % self.packet[1],
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'PCH: %d' % self.packet[1]], 'PCH')
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elif self.packet[0] == 0x51: # Configuration
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powerclass = (self.packet[1] & 0xc0) >> 7
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maxpower = self.packet[1] & 0x3f
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prop = (self.packet[3] & 0x80) >> 7
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count = self.packet[3] & 0x07
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winsize = (self.packet[4] & 0xf8) >> 3
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winoff = self.packet[4] & 0x07
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self.putp(['Configuration: Power Class = %d, Maximum Power = %d, Prop = %d,'
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'Count = %d, Window Size = %d, Window Offset = %d' %
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(powerclass, maxpower, prop, count, winsize, winoff),
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'C: PC = %d MP = %d P = %d C = %d WS = %d WO = %d' %
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(powerclass, maxpower, prop, count, winsize, winoff),
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'Configuration', 'C'])
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elif self.packet[0] == 0x71: # Identification
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version = '%d.%d' % ((self.packet[1] & 0xf0) >> 4, self.packet[1] & 0x0f)
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mancode = '%02x%02x' % (self.packet[2], self.packet[3])
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devid = '%02x%02x%02x%02x' % (self.packet[4] & ~0x80,
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self.packet[5], self.packet[6], self.packet[7])
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self.putp(['Identification: Version = %s, Manufacturer = %s, ' \
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'Device = %s' % (version, mancode, devid),
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'ID: %s %s %s' % (version, mancode, devid), 'ID'])
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elif self.packet[0] == 0x81: # Extended Identification
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edevid = '%02x%02x%02x%02x%02x%02x%02x%02x' % self.packet[1:-1]
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self.putp(['Extended Identification: %s' % edevid,
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'EI: %s' % edevid, 'EI'])
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elif self.packet[0] in (0x18, 0x19, 0x28, 0x29, 0x38, 0x48, 0x58, 0x68,
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0x78, 0x85, 0xa4, 0xc4, 0xe2): # Proprietary
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self.putp(['Proprietary', 'P'])
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else: # Unknown
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self.putp(['Unknown', '?'])
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self.put(self.bytesi[-1], self.samplenum, self.out_ann,
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[6, ['Checksum OK', 'OK']] if \
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calc_checksum(self.packet) == self.packet[-1]
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else [6, ['Checksum error', 'ERR']])
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def process_byte(self):
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self.put(self.bytestart, self.bitsi[0], self.out_ann,
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([2, ['Start bit', 'Start', 'S']]) if self.bits[0] == 0 else
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([1, ['Start error', 'Start err', 'SE']]))
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databits = self.bits[1:9]
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data = bits_to_uint(databits)
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parity = reduce(lambda i, v: (i + v) % 2, databits, 1)
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self.put(self.bitsi[0], self.bitsi[8], self.out_ann, [4, ['%02x' % data]])
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self.put(self.bitsi[8], self.bitsi[9], self.out_ann,
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([3, ['Parity bit', 'Parity', 'P']]) if self.bits[9] == parity else
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([1, ['Parity error', 'Parity err', 'PE']]))
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self.put(self.bitsi[9], self.bitsi[10], self.out_ann,
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([3, ['Stop bit', 'Stop', 'S']]) if self.bits[10] == 1 else
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([1, ['Stop error', 'Stop err', 'SE']]))
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self.bytesi.append(self.bytestart)
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self.packet.append(data)
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if self.packet_len(self.packet[0]) + 2 == len(self.packet):
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self.process_packet()
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self.bytesi.clear()
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self.packet.clear()
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def add_bit(self, bit):
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self.bits.append(bit)
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self.bitsi.append(self.samplenum)
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if self.state == 'IDLE' and len(self.bits) >= 5 and \
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self.bits[-5:] == [1, 1, 1, 1, 0]:
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self.state = 'DATA'
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self.bytestart = self.bitsi[-2]
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self.bits = [0]
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self.bitsi = [self.samplenum]
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self.packet.clear()
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elif self.state == 'DATA' and len(self.bits) == 11:
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self.process_byte()
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self.bytestart = self.samplenum
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self.bits.clear()
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self.bitsi.clear()
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if self.state != 'IDLE':
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self.put(self.lastbit, self.samplenum, self.out_ann, [0, ['%d' % bit]])
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self.lastbit = self.samplenum
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def handle_transition(self, l, htl):
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self.deq.append(l)
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if len(self.deq) >= 2 and \
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(self.in_tolerance(self.deq[-1] + self.deq[-2]) or \
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htl and self.in_tolerance(l * 2) and \
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self.deq[-2] > 1.25 * self.bit_width):
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self.add_bit(1)
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self.deq.clear()
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elif self.in_tolerance(l):
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self.add_bit(0)
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self.deq.clear()
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elif l > (1.25 * self.bit_width):
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self.state = 'IDLE'
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self.bytesi.clear()
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self.packet.clear()
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self.bits.clear()
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self.bitsi.clear()
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def decode(self):
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if not self.samplerate:
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raise SamplerateError('Cannot decode without samplerate.')
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(qi,) = self.wait()
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self.handle_transition(self.samplenum, qi == 0)
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while True:
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prev = self.samplenum
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(qi,) = self.wait({0: 'e'})
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self.handle_transition(self.samplenum - prev, qi == 0)
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