mirror of
https://github.com/armfly/H7-TOOL_STM32H7_App.git
synced 2024-08-09 10:05:34 +08:00
armfly
GitHub
commit
1dca8ad982
@ -1,6 +1,34 @@
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|||||||
【待解决】
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【待解决】
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||||||
3. qspi_read(), lua连续读取存在问题. 2019-07-07
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3. qspi_read(), lua连续读取存在问题. 2019-07-07
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||||||
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||||||
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----------------------------------------------------------------------------
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||||||
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2019-11-29 V1.05 - 功能未增加，但是改动比较大，封一个版本。
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||||||
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1.HAL固件库、USB库升级到最新版（来自于en.stm32cubeh7 （V1.5.0））
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||||||
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-所有的GPIO寄存器操作更改为如下宏（因为新固件库取消了 BSRRH、BSRRL寄存器）
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||||||
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#define BSP_SET_GPIO_1(gpio, pin) gpio->BSRR = pin
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||||||
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#define BSP_SET_GPIO_0(gpio, pin) gpio->BSRR = (uint32_t)pin << 16U
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||||||
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||||||
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2.显示屏驱动采用SPI+DMA驱动。整屏刷新18ms。（驱动由硬汉提供）
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- 修bsp_tft_st7789.c文件
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||||||
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- bsp_Idle()函数执行 ST7789_DrawScreen(); /* 硬件SPI+DMA+刷屏 */
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||||||
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- 使用0x30000000开始的240*240*2字节内存做显存
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||||||
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||||||
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3.为了适应后台刷屏机制。所有的 while循环中bsp_Idle() 位置放到显示刷新后面
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while (g_MainStatus == MS_CURRENT_METER)
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{
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if (fRefresh) /* 刷新整个界面 */
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||||||
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{
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fRefresh = 0;
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||||||
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DispCurrentVolt();
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||||||
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AutoCurrentRange();
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}
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||||||
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bsp_Idle(); /* 必须在fRefresh语句后边, 否则刚进入界面会有闪烁感 */
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||||||
|
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||||||
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...
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||||||
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}
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||||||
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||||||
----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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||||||
2019-11-25 V1.04
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2019-11-25 V1.04
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1.新增脉冲计数和频率计功能。status_pulse_meter.c
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1.新增脉冲计数和频率计功能。status_pulse_meter.c
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||||||
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|||||||
25523
Libraries/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h
Normal file
25523
Libraries/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
26945
Libraries/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h
Normal file
26945
Libraries/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h
Normal file
File diff suppressed because it is too large
Load Diff
30118
Libraries/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h
Normal file
30118
Libraries/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
26442
Libraries/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h
Normal file
26442
Libraries/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h
Normal file
File diff suppressed because it is too large
Load Diff
27214
Libraries/CMSIS/Device/ST/STM32H7xx/Include/stm32h755xx.h
Normal file
27214
Libraries/CMSIS/Device/ST/STM32H7xx/Include/stm32h755xx.h
Normal file
File diff suppressed because it is too large
Load Diff
30387
Libraries/CMSIS/Device/ST/STM32H7xx/Include/stm32h757xx.h
Normal file
30387
Libraries/CMSIS/Device/ST/STM32H7xx/Include/stm32h757xx.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -16,29 +16,13 @@
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|||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
@ -69,20 +53,31 @@
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|||||||
#define STM32H7
|
#define STM32H7
|
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#endif /* STM32H7 */
|
#endif /* STM32H7 */
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||||||
|
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||||||
|
|
||||||
/* Uncomment the line below according to the target STM32H7 device used in your
|
/* Uncomment the line below according to the target STM32H7 device used in your
|
||||||
application
|
application
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx)
|
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
|
||||||
/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743II, STM32H743BI, STM32H743XI Devices */
|
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx)
|
||||||
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753II, STM32H753BI, STM32H753XI Devices */
|
/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
|
||||||
|
/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
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||||||
|
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
|
||||||
/* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
|
/* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
|
||||||
|
/* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
|
||||||
|
/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
|
||||||
|
/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
|
||||||
|
/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||||
devices, you can define the device in your toolchain compiler preprocessor.
|
devices, you can define the device in your toolchain compiler preprocessor.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
|
||||||
|
#error "Dual core device, please select CORE_CM4 or CORE_CM7"
|
||||||
|
#endif
|
||||||
|
|
||||||
#if !defined (USE_HAL_DRIVER)
|
#if !defined (USE_HAL_DRIVER)
|
||||||
/**
|
/**
|
||||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||||
@ -93,10 +88,10 @@
|
|||||||
#endif /* USE_HAL_DRIVER */
|
#endif /* USE_HAL_DRIVER */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief CMSIS Device version number V1.3.0
|
* @brief CMSIS Device version number V1.6.0
|
||||||
*/
|
*/
|
||||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */
|
||||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||||
@ -118,6 +113,16 @@
|
|||||||
#include "stm32h753xx.h"
|
#include "stm32h753xx.h"
|
||||||
#elif defined(STM32H750xx)
|
#elif defined(STM32H750xx)
|
||||||
#include "stm32h750xx.h"
|
#include "stm32h750xx.h"
|
||||||
|
#elif defined(STM32H742xx)
|
||||||
|
#include "stm32h742xx.h"
|
||||||
|
#elif defined(STM32H745xx)
|
||||||
|
#include "stm32h745xx.h"
|
||||||
|
#elif defined(STM32H755xx)
|
||||||
|
#include "stm32h755xx.h"
|
||||||
|
#elif defined(STM32H747xx)
|
||||||
|
#include "stm32h747xx.h"
|
||||||
|
#elif defined(STM32H757xx)
|
||||||
|
#include "stm32h757xx.h"
|
||||||
#else
|
#else
|
||||||
#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
|
#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@ -6,29 +6,13 @@
|
|||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
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||||||
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|||||||
@ -1,238 +1,225 @@
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
|
<!DOCTYPE html>
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||||||
<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
|
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
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|
<head>
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|
<meta charset="utf-8" />
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|
<meta name="generator" content="pandoc" />
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<meta content="text/html; charset=ISO-8859-1" http-equiv="content-type">
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<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
|
||||||
<link rel="File-List" href="Library_files/filelist.xml">
|
<title>Release Notes for STM32H7xx CMSIS</title>
|
||||||
<link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32H7xx CMSIS</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
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|
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|
div.column{display: inline-block; vertical-align: top; width: 50%;}
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
margin-top:12.0pt;
|
<h1 id="release-notes-for-stm32h7xx-cmsis"><strong>Release Notes for STM32H7xx CMSIS</strong></h1>
|
||||||
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|
<p>Copyright © 2017 STMicroelectronics<br />
|
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margin-bottom:3.0pt;
|
</p>
|
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|
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|
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mso-pagination:widow-orphan;
|
</center>
|
||||||
page-break-after:avoid;
|
</div>
|
||||||
mso-outline-level:2;
|
</div>
|
||||||
font-size:14.0pt;
|
<h1 id="license"><strong>License</strong></h1>
|
||||||
font-family:Arial;
|
This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
|
||||||
font-weight:bold;
|
<center>
|
||||||
font-style:italic;}
|
<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
|
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|
||||||
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|
<h1 id="update-history"><strong>Update History</strong></h1>
|
||||||
a:visited, span.MsoHyperlinkFollowed
|
<div class="collapse">
|
||||||
{color:blue;
|
<input type="checkbox" id="collapse-section8" checked aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
|
||||||
text-decoration:underline;
|
<div>
|
||||||
text-underline:single;}
|
<h2 id="main-changes">Main Changes</h2>
|
||||||
p
|
<ul>
|
||||||
{mso-margin-top-alt:auto;
|
<li>Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices</li>
|
||||||
margin-right:0in;
|
<li>Add definition of “ART” instance: pointer to “ART_TypeDef” structure</li>
|
||||||
mso-margin-bottom-alt:auto;
|
<li>Add definition of “ART” bit fields: ART_CTR_EN and ART_CTR_PCACHEADDR<br />
|
||||||
margin-left:0in;
|
</li>
|
||||||
mso-pagination:widow-orphan;
|
<li>Update definitions of “HRTIM1_TIMA” to “HRTIM1_TIME” : pointer to HRTIM_Timerx_TypeDef structure instead of HRTIM_TIM_TypeDef</li>
|
||||||
font-size:12.0pt;
|
<li>Fix Typo in “ETH_TypeDef” definition: use uint32_t for “RESERVED16” registers instead of int32_t</li>
|
||||||
font-family:"Times New Roman";
|
<li>Remove useless definition of “SDMMC” instance (keep only definitions of “SDMMC1” and “SDMMC2”)</li>
|
||||||
mso-fareast-font-family:"Times New Roman";}
|
</ul>
|
||||||
@page Section1
|
</div>
|
||||||
{size:8.5in 11.0in;
|
</div>
|
||||||
margin:1.0in 1.25in 1.0in 1.25in;
|
<div class="collapse">
|
||||||
mso-header-margin:.5in;
|
<input type="checkbox" id="collapse-section7" checked aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
|
||||||
mso-footer-margin:.5in;
|
<div>
|
||||||
mso-paper-source:0;}
|
<h2 id="main-changes-1">Main Changes</h2>
|
||||||
div.Section1
|
<ul>
|
||||||
{page:Section1;}
|
<li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
|
||||||
-->
|
<li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li>
|
||||||
</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
|
<li>Add support of stm32h745xx, stm32h747xx, stm32h755xx, stm32h757xx <strong>Dual Core</strong> devices and STM32H742xx (new single core device):
|
||||||
<meta content="MCD Application Team" name="author"></head>
|
<ul>
|
||||||
<body link="blue" vlink="blue">
|
<li>Add “stm32h745xx.h” , “stm32h747xx.h”, “stm32h755xx.h”, “stm32h757xx.h” and “stm32h742xx.h” files</li>
|
||||||
<div class="Section1">
|
<li>Add startup files “startup_stm32h745xx.s”, “startup_stm32h747xx.s”, “startup_stm32h755xx.s”, “startup_stm32h757xx.s” and “startup_stm32h742xx.s” for EWARM , MDK-ARM and SW4STM32 toolchains</li>
|
||||||
<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
|
<li>Add part numbers list to stm32h7xx.h header file:
|
||||||
</o:p></span></p>
|
<ul>
|
||||||
<div align="center">
|
<li>STM32H742xx: STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI</li>
|
||||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
<li>STM32H743xx: STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI</li>
|
||||||
<tbody>
|
<li>STM32H753xx: STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI</li>
|
||||||
<tr style="">
|
<li>STM32H750xx: STM32H750V, STM32H750I, STM32H750X</li>
|
||||||
<td style="padding: 0cm;" valign="top">
|
<li>STM32H747xx: STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI</li>
|
||||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
<li>STM32H757xx: STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI</li>
|
||||||
<tbody>
|
<li>STM32H745xx: STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI</li>
|
||||||
<tr>
|
<li><p>STM32H755xx: STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI</p></li>
|
||||||
<td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../Release_Notes.html">Back to
|
<li>Add system_stm32h7xx_singlecore.c : system initialization template source file for single core lines (STM32H743xx, STM32H753xx, STM32H750xx and STM32H742xx)</li>
|
||||||
Release page</a></span></td>
|
<li>Add system initialization template source file for dual core lines:
|
||||||
</tr>
|
<ul>
|
||||||
<tr style="">
|
<li>system_stm32h7xx_dualcore_boot_cm4_cm7.c: template for the boot case where Cortex-M7 and Cortex-M4 are boot at once</li>
|
||||||
<td style="padding: 1.5pt;">
|
<li>system_stm32h7xx_dualcore_bootcm7_cm4gated.c: template for the boot case where Cortex-M7 is booting and Cortex-M4 is gated using FLASH Option Bytes</li>
|
||||||
<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
|
<li>system_stm32h7xx_dualcore_bootcm4_cm7gated.c: template for the boot case where Cortex-M4 is booting and Cortex-M7 is gated using FLASH Option Bytes</li>
|
||||||
Notes
|
</ul></li>
|
||||||
for STM32H7xx CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
|
<li>Add EWARM, MDK-ARM and SW4STM32 <strong>Dual Core</strong> devices linker files</li>
|
||||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
|
<li><p>Add EWARM STM32H742xx devices linker files</p></li>
|
||||||
2017
|
</ul></li>
|
||||||
STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
|
</ul></li>
|
||||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
<li><strong>Registers and bit field definitions updates</strong>:
|
||||||
</td>
|
<ul>
|
||||||
</tr>
|
<li>Update SYSCFG_TypeDef structure to add
|
||||||
</tbody>
|
<ul>
|
||||||
</table>
|
<li>Add CFGR register: allowing to control connection between double ECC RAMs/Flash errors, PVD errors and CortexM7/M4 lockup to TIM1/8/15/16/17 and HRTIMER Break inputs</li>
|
||||||
<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>
|
<li>Add definitions of SYSCFG_CFGR register bit fields</li>
|
||||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
|
<li>PWRCR registers: allowing to control the PWR overdrive enable/disable for Voltage Scaling zero</li>
|
||||||
<tbody>
|
<li>Add SYSCFG_PWRCR register bit fields</li>
|
||||||
<tr>
|
</ul></li>
|
||||||
<td style="padding: 0cm;" valign="top">
|
<li>Update RCC_TypeDef structure according to STM32H7xx <strong>Rev.V</strong> devices:
|
||||||
<span style="font-family: "Times New Roman";"></span>
|
<ul>
|
||||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update
|
<li>ICSCR: renamed to HSICFGR, HSI Clock Calibration Register</li>
|
||||||
History</span></h2>
|
<li>Rename also RCC_ICSCR_XXX bit definitions RCC_HSICFGR_XXX according to the new register HSICFGR</li>
|
||||||
|
<li>CSICFGR: New registers (on <strong>Rev.V</strong> devices), CSI Clock Calibration Register</li>
|
||||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0
|
<li>Add dedicated RCC_CSICFGR_XXX bit definitions</li>
|
||||||
/ 29-June-2018</span></h3>
|
</ul></li>
|
||||||
|
<li>Keep RCC_Core_TypeDef structure used for Dual Core lines devices only: allowing RCC clock enabling/allocation for each Core(Cortex-M7/M4)
|
||||||
|
<ul>
|
||||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
<li>RCC_Core_TypeDef structure and RCC_C1_BASE/RCC_C1 definition removed from STM32H743xx/53xx and STM32H750xx lines</li>
|
||||||
Changes</span></u></b></p>
|
</ul></li>
|
||||||
|
<li>Add CRYP_CR_NPBLB bit field definition: upon refresh of the CRYP peripheral on the STM32H7 <strong>Rev.V</strong> devices</li>
|
||||||
|
<li>Update ADC_CR_BOOST bot field definition for STM32H7 <strong>Rev.V</strong> devices: 2 bits instead of 1</li>
|
||||||
<ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">Add support for <span style="font-weight: bold;">stm32h750xx</span> value line devices</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">Add "stm32h750xx.h" file</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">Add startup files startup_stm32h750xx.s for EWARM, MDK-ARM and SW4STM32<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0
|
<li>Remove useless I2C_CR1_SWRST definition: alignment with the reference manual</li>
|
||||||
/
|
<li>Add SAI_xCR1_NODIV bit field definition upon SAI peripheral update for STM32H7 <strong>Rev.V</strong> devices</li>
|
||||||
29-December-2017</span></h3>
|
<li>Rename SPI_TXCRC_RXCRC to SPI_RXCRC_RXCRC: typo fix and alignment with the reference manual</li>
|
||||||
|
<li>Fix QUADSPI_SR_FLEVEL bit field definition: Mask on 6 bits (0x3F mask) instead of 5 bits(0x1F mask) and add definition of QUADSPI_SR_FLEVEL_6</li>
|
||||||
|
<li>Add definition of SYSCFG_EXTICR3_EXTI8_PK, SYSCFG_EXTICR3_EXTI9_PK, SYSCFG_EXTICR3_EXTI10_PK, SYSCFG_EXTICR3_EXTI11_PK and SYSCFG_EXTICR4_EXTI13_PK</li>
|
||||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
<li>Add definition of FLASH_LATENCY_DEFAULT: default safe FLASH latency</li>
|
||||||
Changes</span></u></b></p>
|
</ul></li>
|
||||||
|
</ul>
|
||||||
|
</div>
|
||||||
<ul style="margin-top: 0cm;" type="square">
|
</div>
|
||||||
<li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">Update FDCAN bit definition.</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access.<br>
|
<div class="collapse">
|
||||||
</span></li>
|
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label>
|
||||||
</ul>
|
<div>
|
||||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0
|
<h2 id="main-changes-2">Main Changes</h2>
|
||||||
/
|
<ul>
|
||||||
31-August-2017</span></h3>
|
<li><strong>Patch Release on top of V1.3.0</strong></li>
|
||||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
<li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files:
|
||||||
Changes</span></u></b></p>
|
<ul>
|
||||||
<ul style="margin-top: 0cm;" type="square">
|
<li>stm32h743xx.h, stm32h750xx.h and stm32h753xx.h</li>
|
||||||
<li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">Update
|
</ul></li>
|
||||||
USB OTG bit definition.</span></li>
|
</ul>
|
||||||
<li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">Adjust
|
</div>
|
||||||
PLL fractional computation.</span></li>
|
</div>
|
||||||
</ul>
|
<div class="collapse">
|
||||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0
|
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
|
||||||
/
|
<div>
|
||||||
21-April-2017</span></h3>
|
<h2 id="main-changes-3">Main Changes</h2>
|
||||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
<ul>
|
||||||
Changes<o:p></o:p></span></u></b></p>
|
<li>STM32H7xx include files:
|
||||||
<ul style="margin-top: 0cm;" type="square">
|
<ul>
|
||||||
<li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">First
|
<li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
|
||||||
official release for </span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-style: italic; font-weight: bold;">STM32H743xx/753xx</span>
|
<li>Update "_Mask" bits definition using UL suffix for Misra-C 2012 compliance</li>
|
||||||
devices</span></li>
|
<li>Add definition of <strong>RAMECC_MonitorTypeDef</strong> and <strong>RAMECC_TypeDef</strong> structure</li>
|
||||||
</ul>
|
<li>Add definition of <strong>RAMECC</strong> peripheral base addresses</li>
|
||||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span>
|
<li>Add <strong>RAMECC</strong> peripheral registers bit definitions</li>
|
||||||
<ul style="margin-top: 0in;" type="disc">
|
<li>Add IS_RAMECC_MONITOR_ALL_INSTANCE macro</li>
|
||||||
</ul>
|
<li>Add <strong>EXTI</strong> SWIER3 bit definitions</li>
|
||||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
|
<li>Update <strong>FLASH</strong> sector number to 8 instead of 16 (8 sectors for each bank)</li>
|
||||||
<p class="MsoNormal"></p>
|
<li>Remove extra bit definition : FLASH_CR_SNB_3 to FLASH_CR_SNB_7</li>
|
||||||
<div style="text-align: center;">
|
<li>Update <strong>FLASH</strong> user option bytes bit definition</li>
|
||||||
<div style="text-align: justify;">
|
<li>Fix FLASH_BANK_SIZE definition: add parenthesis</li>
|
||||||
<div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistribution
|
<li>Remove <strong>PWR</strong> extra bit definition PWR_CR1_RLPSN</li>
|
||||||
and
|
<li>Add <strong>PWR</strong> bit definition PWR_WKUPEPR_WKUPEN</li>
|
||||||
use in source and binary forms, with or
|
<li>Fix typo in <strong>SDMMC</strong> bit definition: SDMMC_MASK_SDIOITIE_Pos, SDMMC_MASK_SDIOITIE_Msk and SDMMC_MASK_SDIOITIE</li>
|
||||||
without
|
<li>Add <strong>SDMMC</strong> instance check macro: IS_SDMMC_ALL_INSTANCE</li>
|
||||||
modification, are permitted provided that the
|
<li>Fix typo in <strong>SYSCFG</strong> bit definition: SYSCFG_PMCR_EPIS_SEL_Pos, SYSCFG_PMCR_EPIS_SEL_Msk, SYSCFG_PMCR_EPIS_SEL and SYSCFG_PMCR_EPIS_SEL_0 to SYSCFG_PMCR_EPIS_SEL_2</li>
|
||||||
following conditions are
|
<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR1_EXTI0_Msk, to SYSCFG_EXTICR1_EXTI3_Msk, 4 bits instead of 3</li>
|
||||||
met:</span><br>
|
<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR2_EXTI0_Msk, to SYSCFG_EXTICR2_EXTI3_Msk, 4 bits instead of 3</li>
|
||||||
</font>
|
<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR3_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI3_Msk, 4 bits instead of 3</li>
|
||||||
<ol>
|
<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR4_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI4_Msk, 4 bits instead of 3</li>
|
||||||
<li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
|
<li>Fix IS_ADC_COMMON_INSTANCE macro : add parenthesis</li>
|
||||||
of
|
<li>Fix HSEM_CR_COREID_CURRENT and HSEM_CR_COREID_CURRENT: add parenthesis</li>
|
||||||
source code must retain the above
|
<li>Update <strong>USART</strong> and <strong>SMARTCARD</strong> bits definition</li>
|
||||||
copyright notice, this list of
|
<li>Update <strong>GPIO</strong> registers and bit definition (BSRR register)</li>
|
||||||
conditions and the following disclaimer.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li>
|
<li>Add IS_GPIO_AF_INSTANCE macro</li>
|
||||||
<li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
|
<li>Update <strong>DAC</strong> bits definition</li>
|
||||||
in
|
<li>Update <strong>FDCAN</strong> bits definition</li>
|
||||||
binary form must reproduce the above
|
<li>Update <strong>USB</strong> bits definition (OTEPSPRM register)</li>
|
||||||
copyright notice, this list of
|
<li>Fix <strong>CEC</strong> bit definition (RXDR register)</li>
|
||||||
conditions and the following disclaimer in
|
<li>Update <strong>TIM</strong> registers and bits definition naming</li>
|
||||||
</span><span style="font-family: "Verdana","sans-serif";">the
|
<li>Fix IS_TIM_CCX_INSTANCE macro : add TIM_CHANNEL_4 to TIM_CHANNEL_6</li>
|
||||||
documentation
|
<li>Update <strong>SPI</strong> and <strong>I2S</strong> bits definition</li>
|
||||||
and/or other materials provided with the
|
<li>Update <strong>BDMA</strong> bits definition</li>
|
||||||
distribution.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li>
|
<li>Update <strong>FMC</strong> bits definition</li>
|
||||||
<li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Neither
|
</ul></li>
|
||||||
the
|
</ul>
|
||||||
name of STMicroelectronics nor the names
|
</div>
|
||||||
of its contributors may be
|
</div>
|
||||||
used to endorse or promote products
|
<div class="collapse">
|
||||||
derived </span><br>
|
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
|
||||||
</font> </li>
|
<div>
|
||||||
</ol>
|
<h2 id="main-changes-4">Main Changes</h2>
|
||||||
<font size="-1"><span style="font-family: "Verdana","sans-serif";">
|
<ul>
|
||||||
from
|
<li>Add support for stm32h750xx value line devices:
|
||||||
this software without specific prior written
|
<ul>
|
||||||
permission.</span><br>
|
<li>Add “stm32h750xx.h” file</li>
|
||||||
<span style="font-family: "Verdana","sans-serif";"></span><br>
|
<li>Add startup files startup_stm32h750xx.s for EWARM, MDK-ARM and SW4STM32</li>
|
||||||
<span style="font-family: "Verdana","sans-serif";">THIS
|
</ul></li>
|
||||||
SOFTWARE
|
</ul>
|
||||||
IS PROVIDED BY THE COPYRIGHT HOLDERS AND
|
</div>
|
||||||
CONTRIBUTORS "AS IS"
|
</div>
|
||||||
AND ANY EXPRESS OR IMPLIED</span><span style="font-family: "Verdana","sans-serif";">
|
<div class="collapse">
|
||||||
WARRANTIES,
|
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
|
||||||
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
<div>
|
||||||
WARRANTIES OF
|
<h2 id="main-changes-5">Main Changes</h2>
|
||||||
MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: "Verdana","sans-serif";">PARTICULAR
|
<ul>
|
||||||
PURPOSE
|
<li>Update FDCAN bit definition</li>
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL THE
|
<li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li>
|
||||||
COPYRIGHT HOLDER OR
|
</ul>
|
||||||
CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: "Verdana","sans-serif";">DIRECT,
|
</div>
|
||||||
INDIRECT,
|
</div>
|
||||||
INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
<div class="collapse">
|
||||||
CONSEQUENTIAL DAMAGES
|
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
|
||||||
(INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: "Verdana","sans-serif";">PROCUREMENT
|
<div>
|
||||||
OF
|
<h2 id="main-changes-6">Main Changes</h2>
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
<ul>
|
||||||
DATA, OR PROFITS; OR
|
<li>Update USB OTG bit definition</li>
|
||||||
BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: "Verdana","sans-serif";">
|
<li>Adjust PLL fractional computation</li>
|
||||||
CAUSED AND ON
|
</ul>
|
||||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
</div>
|
||||||
STRICT LIABILITY, OR TORT
|
</div>
|
||||||
(INCLUDING NEGLIGENCE OR </span><span style="font-family: "Verdana","sans-serif";">OTHERWISE)
|
<div class="collapse">
|
||||||
ARISING
|
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
|
||||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
<div>
|
||||||
EVEN IF ADVISED OF
|
<h2 id="main-changes-7">Main Changes</h2>
|
||||||
THE POSSIBILITY OF SUCH DAMAGE.</span></font>
|
<ul>
|
||||||
</div>
|
<li>First official release for <strong>STM32H743xx/753xx</strong> devices</li>
|
||||||
<span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></div>
|
</ul>
|
||||||
<span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></div>
|
</div>
|
||||||
<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> </span></p>
|
</div>
|
||||||
<span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span>
|
</div>
|
||||||
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
|
</div>
|
||||||
<hr align="center" size="2" width="100%"></span></div>
|
<footer class="sticky">
|
||||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
|
For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>
|
||||||
complete
|
</footer>
|
||||||
documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers
|
</body>
|
||||||
visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
|
</html>
|
||||||
</td>
|
|
||||||
</tr>
|
|
||||||
</tbody>
|
|
||||||
</table>
|
|
||||||
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
|
||||||
</td>
|
|
||||||
</tr>
|
|
||||||
</tbody>
|
|
||||||
</table>
|
|
||||||
</div>
|
|
||||||
<p class="MsoNormal"><o:p> </o:p></p>
|
|
||||||
</div>
|
|
||||||
</body></html>
|
|
||||||
|
|||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x08100000 0x00100000 { ; load region size_region
|
||||||
|
ER_IROM1 0x08100000 0x00100000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x10000000 0x10048000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
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|||||||
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||||||
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; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
|
||||||
|
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x20000000 0x20020000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
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||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x24000000 0x00040000 { ; load region size_region
|
||||||
|
ER_IROM1 0x24000000 0x00040000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x24040000 0x24080000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x10000000 0x00020000 { ; load region size_region
|
||||||
|
ER_IROM1 0x10000000 0x00020000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x10020000 0x10048000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x08100000 0x00100000 { ; load region size_region
|
||||||
|
ER_IROM1 0x08100000 0x00100000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x10000000 0x10048000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
|
||||||
|
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x20000000 0x20020000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x24000000 0x00040000 { ; load region size_region
|
||||||
|
ER_IROM1 0x24000000 0x00040000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x24040000 0x24080000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x10000000 0x00020000 { ; load region size_region
|
||||||
|
ER_IROM1 0x10000000 0x00020000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x10020000 0x10048000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x08100000 0x00100000 { ; load region size_region
|
||||||
|
ER_IROM1 0x08100000 0x00100000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x10000000 0x10048000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
|
||||||
|
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x20000000 0x20020000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x24000000 0x00040000 { ; load region size_region
|
||||||
|
ER_IROM1 0x24000000 0x00040000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x24040000 0x24080000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x10000000 0x00020000 { ; load region size_region
|
||||||
|
ER_IROM1 0x10000000 0x00020000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x10020000 0x10048000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x08100000 0x00100000 { ; load region size_region
|
||||||
|
ER_IROM1 0x08100000 0x00100000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x10000000 0x10048000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
|
||||||
|
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x20000000 0x20020000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x24000000 0x00040000 { ; load region size_region
|
||||||
|
ER_IROM1 0x24000000 0x00040000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x24040000 0x24080000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,14 @@
|
|||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x10000000 0x00020000 { ; load region size_region
|
||||||
|
ER_IROM1 0x10000000 0x00020000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x10020000 0x10048000{ ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1,605 @@
|
|||||||
|
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32h742xx.s
|
||||||
|
;* @author MCD Application Team
|
||||||
|
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
;******************************************************************************
|
||||||
|
;* @attention
|
||||||
|
;*
|
||||||
|
;* Copyright (c) 2019 STMicroelectronics.
|
||||||
|
;* All rights reserved.
|
||||||
|
;*
|
||||||
|
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
;* the "License"; You may not use this file except in compliance with the
|
||||||
|
;* License. You may obtain a copy of the License at:
|
||||||
|
;* opensource.org/licenses/BSD-3-Clause
|
||||||
|
;*
|
||||||
|
;******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
|
||||||
|
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
|
||||||
|
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||||
|
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||||
|
DCD FLASH_IRQHandler ; FLASH
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||||
|
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||||
|
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||||
|
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||||
|
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||||
|
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||||
|
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||||
|
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||||
|
DCD ADC_IRQHandler ; ADC1, ADC2
|
||||||
|
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
|
||||||
|
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
|
||||||
|
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
|
||||||
|
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
|
||||||
|
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; External Line[15:10]
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
|
||||||
|
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
|
||||||
|
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
|
||||||
|
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
|
||||||
|
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||||
|
DCD FMC_IRQHandler ; FMC
|
||||||
|
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||||
|
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||||
|
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||||
|
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||||
|
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||||
|
DCD ETH_IRQHandler ; Ethernet
|
||||||
|
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||||
|
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||||
|
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||||
|
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||||
|
DCD USART6_IRQHandler ; USART6
|
||||||
|
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||||
|
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||||
|
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||||
|
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||||
|
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||||
|
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||||
|
DCD DCMI_IRQHandler ; DCMI
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD RNG_IRQHandler ; Rng
|
||||||
|
DCD FPU_IRQHandler ; FPU
|
||||||
|
DCD UART7_IRQHandler ; UART7
|
||||||
|
DCD UART8_IRQHandler ; UART8
|
||||||
|
DCD SPI4_IRQHandler ; SPI4
|
||||||
|
DCD SPI5_IRQHandler ; SPI5
|
||||||
|
DCD SPI6_IRQHandler ; SPI6
|
||||||
|
DCD SAI1_IRQHandler ; SAI1
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA2D_IRQHandler ; DMA2D
|
||||||
|
DCD SAI2_IRQHandler ; SAI2
|
||||||
|
DCD QUADSPI_IRQHandler ; QUADSPI
|
||||||
|
DCD LPTIM1_IRQHandler ; LPTIM1
|
||||||
|
DCD CEC_IRQHandler ; HDMI_CEC
|
||||||
|
DCD I2C4_EV_IRQHandler ; I2C4 Event
|
||||||
|
DCD I2C4_ER_IRQHandler ; I2C4 Error
|
||||||
|
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||||
|
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
|
||||||
|
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
|
||||||
|
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
|
||||||
|
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||||
|
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
|
||||||
|
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
|
||||||
|
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
|
||||||
|
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
|
||||||
|
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
|
||||||
|
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
|
||||||
|
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
|
||||||
|
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
|
||||||
|
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
|
||||||
|
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
|
||||||
|
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
|
||||||
|
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
|
||||||
|
DCD SAI3_IRQHandler ; SAI3 global Interrupt
|
||||||
|
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
|
||||||
|
DCD TIM15_IRQHandler ; TIM15 global Interrupt
|
||||||
|
DCD TIM16_IRQHandler ; TIM16 global Interrupt
|
||||||
|
DCD TIM17_IRQHandler ; TIM17 global Interrupt
|
||||||
|
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
|
||||||
|
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD MDMA_IRQHandler ; MDMA global Interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
|
||||||
|
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD ADC3_IRQHandler ; ADC3 global Interrupt
|
||||||
|
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
|
||||||
|
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
|
||||||
|
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
|
||||||
|
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
|
||||||
|
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
|
||||||
|
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
|
||||||
|
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
|
||||||
|
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
|
||||||
|
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
|
||||||
|
DCD COMP1_IRQHandler ; COMP1 global Interrupt
|
||||||
|
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
|
||||||
|
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
|
||||||
|
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
|
||||||
|
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
|
||||||
|
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||||
|
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||||
|
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
|
||||||
|
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_AVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT FMC_IRQHandler [WEAK]
|
||||||
|
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||||
|
EXPORT ETH_IRQHandler [WEAK]
|
||||||
|
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN_CAL_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART6_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||||
|
EXPORT DCMI_IRQHandler [WEAK]
|
||||||
|
EXPORT RNG_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
EXPORT UART7_IRQHandler [WEAK]
|
||||||
|
EXPORT UART8_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI6_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2D_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI2_IRQHandler [WEAK]
|
||||||
|
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||||
|
EXPORT CEC_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_Master_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI3_IRQHandler [WEAK]
|
||||||
|
EXPORT SWPMI1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM15_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM16_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM17_IRQHandler [WEAK]
|
||||||
|
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT MDIOS_IRQHandler [WEAK]
|
||||||
|
EXPORT MDMA_IRQHandler [WEAK]
|
||||||
|
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||||
|
EXPORT HSEM1_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT COMP1_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT LPUART1_IRQHandler [WEAK]
|
||||||
|
EXPORT CRS_IRQHandler [WEAK]
|
||||||
|
EXPORT ECC_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI4_IRQHandler [WEAK]
|
||||||
|
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_AVD_IRQHandler
|
||||||
|
TAMP_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Stream0_IRQHandler
|
||||||
|
DMA1_Stream1_IRQHandler
|
||||||
|
DMA1_Stream2_IRQHandler
|
||||||
|
DMA1_Stream3_IRQHandler
|
||||||
|
DMA1_Stream4_IRQHandler
|
||||||
|
DMA1_Stream5_IRQHandler
|
||||||
|
DMA1_Stream6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
FDCAN1_IT0_IRQHandler
|
||||||
|
FDCAN2_IT0_IRQHandler
|
||||||
|
FDCAN1_IT1_IRQHandler
|
||||||
|
FDCAN2_IT1_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
TIM8_BRK_TIM12_IRQHandler
|
||||||
|
TIM8_UP_TIM13_IRQHandler
|
||||||
|
TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
TIM8_CC_IRQHandler
|
||||||
|
DMA1_Stream7_IRQHandler
|
||||||
|
FMC_IRQHandler
|
||||||
|
SDMMC1_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
UART5_IRQHandler
|
||||||
|
TIM6_DAC_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
DMA2_Stream0_IRQHandler
|
||||||
|
DMA2_Stream1_IRQHandler
|
||||||
|
DMA2_Stream2_IRQHandler
|
||||||
|
DMA2_Stream3_IRQHandler
|
||||||
|
DMA2_Stream4_IRQHandler
|
||||||
|
ETH_IRQHandler
|
||||||
|
ETH_WKUP_IRQHandler
|
||||||
|
FDCAN_CAL_IRQHandler
|
||||||
|
DMA2_Stream5_IRQHandler
|
||||||
|
DMA2_Stream6_IRQHandler
|
||||||
|
DMA2_Stream7_IRQHandler
|
||||||
|
USART6_IRQHandler
|
||||||
|
I2C3_EV_IRQHandler
|
||||||
|
I2C3_ER_IRQHandler
|
||||||
|
OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
OTG_HS_EP1_IN_IRQHandler
|
||||||
|
OTG_HS_WKUP_IRQHandler
|
||||||
|
OTG_HS_IRQHandler
|
||||||
|
DCMI_IRQHandler
|
||||||
|
RNG_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
UART7_IRQHandler
|
||||||
|
UART8_IRQHandler
|
||||||
|
SPI4_IRQHandler
|
||||||
|
SPI5_IRQHandler
|
||||||
|
SPI6_IRQHandler
|
||||||
|
SAI1_IRQHandler
|
||||||
|
DMA2D_IRQHandler
|
||||||
|
SAI2_IRQHandler
|
||||||
|
QUADSPI_IRQHandler
|
||||||
|
LPTIM1_IRQHandler
|
||||||
|
CEC_IRQHandler
|
||||||
|
I2C4_EV_IRQHandler
|
||||||
|
I2C4_ER_IRQHandler
|
||||||
|
SPDIF_RX_IRQHandler
|
||||||
|
OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
OTG_FS_EP1_IN_IRQHandler
|
||||||
|
OTG_FS_WKUP_IRQHandler
|
||||||
|
OTG_FS_IRQHandler
|
||||||
|
DMAMUX1_OVR_IRQHandler
|
||||||
|
HRTIM1_Master_IRQHandler
|
||||||
|
HRTIM1_TIMA_IRQHandler
|
||||||
|
HRTIM1_TIMB_IRQHandler
|
||||||
|
HRTIM1_TIMC_IRQHandler
|
||||||
|
HRTIM1_TIMD_IRQHandler
|
||||||
|
HRTIM1_TIME_IRQHandler
|
||||||
|
HRTIM1_FLT_IRQHandler
|
||||||
|
DFSDM1_FLT0_IRQHandler
|
||||||
|
DFSDM1_FLT1_IRQHandler
|
||||||
|
DFSDM1_FLT2_IRQHandler
|
||||||
|
DFSDM1_FLT3_IRQHandler
|
||||||
|
SAI3_IRQHandler
|
||||||
|
SWPMI1_IRQHandler
|
||||||
|
TIM15_IRQHandler
|
||||||
|
TIM16_IRQHandler
|
||||||
|
TIM17_IRQHandler
|
||||||
|
MDIOS_WKUP_IRQHandler
|
||||||
|
MDIOS_IRQHandler
|
||||||
|
MDMA_IRQHandler
|
||||||
|
SDMMC2_IRQHandler
|
||||||
|
HSEM1_IRQHandler
|
||||||
|
ADC3_IRQHandler
|
||||||
|
DMAMUX2_OVR_IRQHandler
|
||||||
|
BDMA_Channel0_IRQHandler
|
||||||
|
BDMA_Channel1_IRQHandler
|
||||||
|
BDMA_Channel2_IRQHandler
|
||||||
|
BDMA_Channel3_IRQHandler
|
||||||
|
BDMA_Channel4_IRQHandler
|
||||||
|
BDMA_Channel5_IRQHandler
|
||||||
|
BDMA_Channel6_IRQHandler
|
||||||
|
BDMA_Channel7_IRQHandler
|
||||||
|
COMP1_IRQHandler
|
||||||
|
LPTIM2_IRQHandler
|
||||||
|
LPTIM3_IRQHandler
|
||||||
|
LPTIM4_IRQHandler
|
||||||
|
LPTIM5_IRQHandler
|
||||||
|
LPUART1_IRQHandler
|
||||||
|
CRS_IRQHandler
|
||||||
|
ECC_IRQHandler
|
||||||
|
SAI4_IRQHandler
|
||||||
|
WAKEUP_PIN_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
@ -11,21 +11,18 @@
|
|||||||
;* After Reset the Cortex-M processor is in Thread mode,
|
;* After Reset the Cortex-M processor is in Thread mode,
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||||
;*******************************************************************************
|
;******************************************************************************
|
||||||
;
|
;* @attention
|
||||||
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
;*
|
||||||
; You may not use this file except in compliance with the License.
|
;* Copyright (c) 2017 STMicroelectronics.
|
||||||
; You may obtain a copy of the License at:
|
;* All rights reserved.
|
||||||
;
|
;*
|
||||||
; http://www.st.com/software_license_agreement_liberty_v2
|
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
;
|
;* the "License"; You may not use this file except in compliance with the
|
||||||
; Unless required by applicable law or agreed to in writing, software
|
;* License. You may obtain a copy of the License at:
|
||||||
; distributed under the License is distributed on an "AS IS" BASIS,
|
;* opensource.org/licenses/BSD-3-Clause
|
||||||
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
;*
|
||||||
; See the License for the specific language governing permissions and
|
;******************************************************************************
|
||||||
; limitations under the License.
|
|
||||||
;
|
|
||||||
;*******************************************************************************
|
|
||||||
|
|
||||||
; Amount of memory (in bytes) allocated for Stack
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
; Tailor this value to your application needs
|
; Tailor this value to your application needs
|
||||||
@ -33,7 +30,7 @@
|
|||||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
; </h>
|
; </h>
|
||||||
|
|
||||||
Stack_Size EQU 0x00001000
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
Stack_Mem SPACE Stack_Size
|
Stack_Mem SPACE Stack_Size
|
||||||
@ -44,7 +41,7 @@ __initial_sp
|
|||||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
; </h>
|
; </h>
|
||||||
|
|
||||||
Heap_Size EQU 0x00001000
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
__heap_base
|
__heap_base
|
||||||
@ -224,7 +221,7 @@ __Vectors DCD __initial_sp ; Top of Stack
|
|||||||
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||||
DCD 0 ; Reserved
|
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||||
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
@ -431,7 +428,8 @@ Default_Handler PROC
|
|||||||
EXPORT LPTIM4_IRQHandler [WEAK]
|
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||||
EXPORT LPTIM5_IRQHandler [WEAK]
|
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||||
EXPORT LPUART1_IRQHandler [WEAK]
|
EXPORT LPUART1_IRQHandler [WEAK]
|
||||||
EXPORT CRS_IRQHandler [WEAK]
|
EXPORT CRS_IRQHandler [WEAK]
|
||||||
|
EXPORT ECC_IRQHandler [WEAK]
|
||||||
EXPORT SAI4_IRQHandler [WEAK]
|
EXPORT SAI4_IRQHandler [WEAK]
|
||||||
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||||
|
|
||||||
@ -571,7 +569,8 @@ LPTIM3_IRQHandler
|
|||||||
LPTIM4_IRQHandler
|
LPTIM4_IRQHandler
|
||||||
LPTIM5_IRQHandler
|
LPTIM5_IRQHandler
|
||||||
LPUART1_IRQHandler
|
LPUART1_IRQHandler
|
||||||
CRS_IRQHandler
|
CRS_IRQHandler
|
||||||
|
ECC_IRQHandler
|
||||||
SAI4_IRQHandler
|
SAI4_IRQHandler
|
||||||
WAKEUP_PIN_IRQHandler
|
WAKEUP_PIN_IRQHandler
|
||||||
|
|
||||||
|
|||||||
@ -0,0 +1,621 @@
|
|||||||
|
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32h745xx.s
|
||||||
|
;* @author MCD Application Team
|
||||||
|
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
;******************************************************************************
|
||||||
|
;* @attention
|
||||||
|
;*
|
||||||
|
;* Copyright (c) 2019 STMicroelectronics.
|
||||||
|
;* All rights reserved.
|
||||||
|
;*
|
||||||
|
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
;* the "License"; You may not use this file except in compliance with the
|
||||||
|
;* License. You may obtain a copy of the License at:
|
||||||
|
;* opensource.org/licenses/BSD-3-Clause
|
||||||
|
;*
|
||||||
|
;******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
|
||||||
|
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
|
||||||
|
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||||
|
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||||
|
DCD FLASH_IRQHandler ; FLASH
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||||
|
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||||
|
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||||
|
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||||
|
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||||
|
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||||
|
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||||
|
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||||
|
DCD ADC_IRQHandler ; ADC1, ADC2
|
||||||
|
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
|
||||||
|
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
|
||||||
|
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
|
||||||
|
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
|
||||||
|
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; External Line[15:10]
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
|
||||||
|
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
|
||||||
|
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
|
||||||
|
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
|
||||||
|
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||||
|
DCD FMC_IRQHandler ; FMC
|
||||||
|
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||||
|
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||||
|
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||||
|
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||||
|
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||||
|
DCD ETH_IRQHandler ; Ethernet
|
||||||
|
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||||
|
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
|
||||||
|
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
|
||||||
|
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||||
|
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||||
|
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||||
|
DCD USART6_IRQHandler ; USART6
|
||||||
|
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||||
|
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||||
|
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||||
|
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||||
|
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||||
|
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||||
|
DCD DCMI_IRQHandler ; DCMI
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD RNG_IRQHandler ; Rng
|
||||||
|
DCD FPU_IRQHandler ; FPU
|
||||||
|
DCD UART7_IRQHandler ; UART7
|
||||||
|
DCD UART8_IRQHandler ; UART8
|
||||||
|
DCD SPI4_IRQHandler ; SPI4
|
||||||
|
DCD SPI5_IRQHandler ; SPI5
|
||||||
|
DCD SPI6_IRQHandler ; SPI6
|
||||||
|
DCD SAI1_IRQHandler ; SAI1
|
||||||
|
DCD LTDC_IRQHandler ; LTDC
|
||||||
|
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||||
|
DCD DMA2D_IRQHandler ; DMA2D
|
||||||
|
DCD SAI2_IRQHandler ; SAI2
|
||||||
|
DCD QUADSPI_IRQHandler ; QUADSPI
|
||||||
|
DCD LPTIM1_IRQHandler ; LPTIM1
|
||||||
|
DCD CEC_IRQHandler ; HDMI_CEC
|
||||||
|
DCD I2C4_EV_IRQHandler ; I2C4 Event
|
||||||
|
DCD I2C4_ER_IRQHandler ; I2C4 Error
|
||||||
|
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||||
|
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
|
||||||
|
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
|
||||||
|
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
|
||||||
|
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||||
|
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
|
||||||
|
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
|
||||||
|
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
|
||||||
|
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
|
||||||
|
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
|
||||||
|
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
|
||||||
|
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
|
||||||
|
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
|
||||||
|
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
|
||||||
|
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
|
||||||
|
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
|
||||||
|
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
|
||||||
|
DCD SAI3_IRQHandler ; SAI3 global Interrupt
|
||||||
|
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
|
||||||
|
DCD TIM15_IRQHandler ; TIM15 global Interrupt
|
||||||
|
DCD TIM16_IRQHandler ; TIM16 global Interrupt
|
||||||
|
DCD TIM17_IRQHandler ; TIM17 global Interrupt
|
||||||
|
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
|
||||||
|
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
|
||||||
|
DCD JPEG_IRQHandler ; JPEG global Interrupt
|
||||||
|
DCD MDMA_IRQHandler ; MDMA global Interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
|
||||||
|
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
|
||||||
|
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
|
||||||
|
DCD ADC3_IRQHandler ; ADC3 global Interrupt
|
||||||
|
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
|
||||||
|
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
|
||||||
|
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
|
||||||
|
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
|
||||||
|
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
|
||||||
|
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
|
||||||
|
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
|
||||||
|
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
|
||||||
|
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
|
||||||
|
DCD COMP1_IRQHandler ; COMP1 global Interrupt
|
||||||
|
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
|
||||||
|
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
|
||||||
|
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
|
||||||
|
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
|
||||||
|
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||||
|
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
|
||||||
|
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||||
|
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||||
|
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
|
||||||
|
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
|
||||||
|
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_AVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT FMC_IRQHandler [WEAK]
|
||||||
|
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||||
|
EXPORT ETH_IRQHandler [WEAK]
|
||||||
|
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN_CAL_IRQHandler [WEAK]
|
||||||
|
EXPORT CM7_SEV_IRQHandler [WEAK]
|
||||||
|
EXPORT CM4_SEV_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART6_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||||
|
EXPORT DCMI_IRQHandler [WEAK]
|
||||||
|
EXPORT RNG_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
EXPORT UART7_IRQHandler [WEAK]
|
||||||
|
EXPORT UART8_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI6_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI1_IRQHandler [WEAK]
|
||||||
|
EXPORT LTDC_IRQHandler [WEAK]
|
||||||
|
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2D_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI2_IRQHandler [WEAK]
|
||||||
|
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||||
|
EXPORT CEC_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_Master_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI3_IRQHandler [WEAK]
|
||||||
|
EXPORT SWPMI1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM15_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM16_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM17_IRQHandler [WEAK]
|
||||||
|
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT MDIOS_IRQHandler [WEAK]
|
||||||
|
EXPORT JPEG_IRQHandler [WEAK]
|
||||||
|
EXPORT MDMA_IRQHandler [WEAK]
|
||||||
|
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||||
|
EXPORT HSEM1_IRQHandler [WEAK]
|
||||||
|
EXPORT HSEM2_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT COMP1_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT LPUART1_IRQHandler [WEAK]
|
||||||
|
EXPORT WWDG_RST_IRQHandler [WEAK]
|
||||||
|
EXPORT CRS_IRQHandler [WEAK]
|
||||||
|
EXPORT ECC_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI4_IRQHandler [WEAK]
|
||||||
|
EXPORT HOLD_CORE_IRQHandler [WEAK]
|
||||||
|
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_AVD_IRQHandler
|
||||||
|
TAMP_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Stream0_IRQHandler
|
||||||
|
DMA1_Stream1_IRQHandler
|
||||||
|
DMA1_Stream2_IRQHandler
|
||||||
|
DMA1_Stream3_IRQHandler
|
||||||
|
DMA1_Stream4_IRQHandler
|
||||||
|
DMA1_Stream5_IRQHandler
|
||||||
|
DMA1_Stream6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
FDCAN1_IT0_IRQHandler
|
||||||
|
FDCAN2_IT0_IRQHandler
|
||||||
|
FDCAN1_IT1_IRQHandler
|
||||||
|
FDCAN2_IT1_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
TIM8_BRK_TIM12_IRQHandler
|
||||||
|
TIM8_UP_TIM13_IRQHandler
|
||||||
|
TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
TIM8_CC_IRQHandler
|
||||||
|
DMA1_Stream7_IRQHandler
|
||||||
|
FMC_IRQHandler
|
||||||
|
SDMMC1_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
UART5_IRQHandler
|
||||||
|
TIM6_DAC_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
DMA2_Stream0_IRQHandler
|
||||||
|
DMA2_Stream1_IRQHandler
|
||||||
|
DMA2_Stream2_IRQHandler
|
||||||
|
DMA2_Stream3_IRQHandler
|
||||||
|
DMA2_Stream4_IRQHandler
|
||||||
|
ETH_IRQHandler
|
||||||
|
ETH_WKUP_IRQHandler
|
||||||
|
FDCAN_CAL_IRQHandler
|
||||||
|
CM7_SEV_IRQHandler
|
||||||
|
CM4_SEV_IRQHandler
|
||||||
|
DMA2_Stream5_IRQHandler
|
||||||
|
DMA2_Stream6_IRQHandler
|
||||||
|
DMA2_Stream7_IRQHandler
|
||||||
|
USART6_IRQHandler
|
||||||
|
I2C3_EV_IRQHandler
|
||||||
|
I2C3_ER_IRQHandler
|
||||||
|
OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
OTG_HS_EP1_IN_IRQHandler
|
||||||
|
OTG_HS_WKUP_IRQHandler
|
||||||
|
OTG_HS_IRQHandler
|
||||||
|
DCMI_IRQHandler
|
||||||
|
RNG_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
UART7_IRQHandler
|
||||||
|
UART8_IRQHandler
|
||||||
|
SPI4_IRQHandler
|
||||||
|
SPI5_IRQHandler
|
||||||
|
SPI6_IRQHandler
|
||||||
|
SAI1_IRQHandler
|
||||||
|
LTDC_IRQHandler
|
||||||
|
LTDC_ER_IRQHandler
|
||||||
|
DMA2D_IRQHandler
|
||||||
|
SAI2_IRQHandler
|
||||||
|
QUADSPI_IRQHandler
|
||||||
|
LPTIM1_IRQHandler
|
||||||
|
CEC_IRQHandler
|
||||||
|
I2C4_EV_IRQHandler
|
||||||
|
I2C4_ER_IRQHandler
|
||||||
|
SPDIF_RX_IRQHandler
|
||||||
|
OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
OTG_FS_EP1_IN_IRQHandler
|
||||||
|
OTG_FS_WKUP_IRQHandler
|
||||||
|
OTG_FS_IRQHandler
|
||||||
|
DMAMUX1_OVR_IRQHandler
|
||||||
|
HRTIM1_Master_IRQHandler
|
||||||
|
HRTIM1_TIMA_IRQHandler
|
||||||
|
HRTIM1_TIMB_IRQHandler
|
||||||
|
HRTIM1_TIMC_IRQHandler
|
||||||
|
HRTIM1_TIMD_IRQHandler
|
||||||
|
HRTIM1_TIME_IRQHandler
|
||||||
|
HRTIM1_FLT_IRQHandler
|
||||||
|
DFSDM1_FLT0_IRQHandler
|
||||||
|
DFSDM1_FLT1_IRQHandler
|
||||||
|
DFSDM1_FLT2_IRQHandler
|
||||||
|
DFSDM1_FLT3_IRQHandler
|
||||||
|
SAI3_IRQHandler
|
||||||
|
SWPMI1_IRQHandler
|
||||||
|
TIM15_IRQHandler
|
||||||
|
TIM16_IRQHandler
|
||||||
|
TIM17_IRQHandler
|
||||||
|
MDIOS_WKUP_IRQHandler
|
||||||
|
MDIOS_IRQHandler
|
||||||
|
JPEG_IRQHandler
|
||||||
|
MDMA_IRQHandler
|
||||||
|
SDMMC2_IRQHandler
|
||||||
|
HSEM1_IRQHandler
|
||||||
|
HSEM2_IRQHandler
|
||||||
|
ADC3_IRQHandler
|
||||||
|
DMAMUX2_OVR_IRQHandler
|
||||||
|
BDMA_Channel0_IRQHandler
|
||||||
|
BDMA_Channel1_IRQHandler
|
||||||
|
BDMA_Channel2_IRQHandler
|
||||||
|
BDMA_Channel3_IRQHandler
|
||||||
|
BDMA_Channel4_IRQHandler
|
||||||
|
BDMA_Channel5_IRQHandler
|
||||||
|
BDMA_Channel6_IRQHandler
|
||||||
|
BDMA_Channel7_IRQHandler
|
||||||
|
COMP1_IRQHandler
|
||||||
|
LPTIM2_IRQHandler
|
||||||
|
LPTIM3_IRQHandler
|
||||||
|
LPTIM4_IRQHandler
|
||||||
|
LPTIM5_IRQHandler
|
||||||
|
LPUART1_IRQHandler
|
||||||
|
WWDG_RST_IRQHandler
|
||||||
|
CRS_IRQHandler
|
||||||
|
ECC_IRQHandler
|
||||||
|
SAI4_IRQHandler
|
||||||
|
HOLD_CORE_IRQHandler
|
||||||
|
WAKEUP_PIN_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
@ -0,0 +1,623 @@
|
|||||||
|
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32h747xx.s
|
||||||
|
;* @author MCD Application Team
|
||||||
|
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
;******************************************************************************
|
||||||
|
;* @attention
|
||||||
|
;*
|
||||||
|
;* Copyright (c) 2019 STMicroelectronics.
|
||||||
|
;* All rights reserved.
|
||||||
|
;*
|
||||||
|
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
;* the "License"; You may not use this file except in compliance with the
|
||||||
|
;* License. You may obtain a copy of the License at:
|
||||||
|
;* opensource.org/licenses/BSD-3-Clause
|
||||||
|
;*
|
||||||
|
;******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
|
||||||
|
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
|
||||||
|
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||||
|
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||||
|
DCD FLASH_IRQHandler ; FLASH
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||||
|
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||||
|
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||||
|
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||||
|
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||||
|
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||||
|
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||||
|
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||||
|
DCD ADC_IRQHandler ; ADC1, ADC2
|
||||||
|
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
|
||||||
|
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
|
||||||
|
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
|
||||||
|
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
|
||||||
|
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; External Line[15:10]
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
|
||||||
|
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
|
||||||
|
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
|
||||||
|
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
|
||||||
|
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||||
|
DCD FMC_IRQHandler ; FMC
|
||||||
|
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||||
|
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||||
|
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||||
|
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||||
|
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||||
|
DCD ETH_IRQHandler ; Ethernet
|
||||||
|
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||||
|
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
|
||||||
|
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
|
||||||
|
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||||
|
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||||
|
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||||
|
DCD USART6_IRQHandler ; USART6
|
||||||
|
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||||
|
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||||
|
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||||
|
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||||
|
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||||
|
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||||
|
DCD DCMI_IRQHandler ; DCMI
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD RNG_IRQHandler ; Rng
|
||||||
|
DCD FPU_IRQHandler ; FPU
|
||||||
|
DCD UART7_IRQHandler ; UART7
|
||||||
|
DCD UART8_IRQHandler ; UART8
|
||||||
|
DCD SPI4_IRQHandler ; SPI4
|
||||||
|
DCD SPI5_IRQHandler ; SPI5
|
||||||
|
DCD SPI6_IRQHandler ; SPI6
|
||||||
|
DCD SAI1_IRQHandler ; SAI1
|
||||||
|
DCD LTDC_IRQHandler ; LTDC
|
||||||
|
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||||
|
DCD DMA2D_IRQHandler ; DMA2D
|
||||||
|
DCD SAI2_IRQHandler ; SAI2
|
||||||
|
DCD QUADSPI_IRQHandler ; QUADSPI
|
||||||
|
DCD LPTIM1_IRQHandler ; LPTIM1
|
||||||
|
DCD CEC_IRQHandler ; HDMI_CEC
|
||||||
|
DCD I2C4_EV_IRQHandler ; I2C4 Event
|
||||||
|
DCD I2C4_ER_IRQHandler ; I2C4 Error
|
||||||
|
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||||
|
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
|
||||||
|
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
|
||||||
|
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
|
||||||
|
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||||
|
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
|
||||||
|
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
|
||||||
|
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
|
||||||
|
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
|
||||||
|
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
|
||||||
|
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
|
||||||
|
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
|
||||||
|
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
|
||||||
|
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
|
||||||
|
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
|
||||||
|
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
|
||||||
|
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
|
||||||
|
DCD SAI3_IRQHandler ; SAI3 global Interrupt
|
||||||
|
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
|
||||||
|
DCD TIM15_IRQHandler ; TIM15 global Interrupt
|
||||||
|
DCD TIM16_IRQHandler ; TIM16 global Interrupt
|
||||||
|
DCD TIM17_IRQHandler ; TIM17 global Interrupt
|
||||||
|
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
|
||||||
|
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
|
||||||
|
DCD JPEG_IRQHandler ; JPEG global Interrupt
|
||||||
|
DCD MDMA_IRQHandler ; MDMA global Interrupt
|
||||||
|
DCD DSI_IRQHandler ; DSI global Interrupt
|
||||||
|
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
|
||||||
|
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
|
||||||
|
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
|
||||||
|
DCD ADC3_IRQHandler ; ADC3 global Interrupt
|
||||||
|
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
|
||||||
|
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
|
||||||
|
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
|
||||||
|
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
|
||||||
|
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
|
||||||
|
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
|
||||||
|
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
|
||||||
|
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
|
||||||
|
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
|
||||||
|
DCD COMP1_IRQHandler ; COMP1 global Interrupt
|
||||||
|
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
|
||||||
|
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
|
||||||
|
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
|
||||||
|
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
|
||||||
|
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||||
|
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
|
||||||
|
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||||
|
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||||
|
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
|
||||||
|
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
|
||||||
|
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_AVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT FMC_IRQHandler [WEAK]
|
||||||
|
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||||
|
EXPORT ETH_IRQHandler [WEAK]
|
||||||
|
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN_CAL_IRQHandler [WEAK]
|
||||||
|
EXPORT CM7_SEV_IRQHandler [WEAK]
|
||||||
|
EXPORT CM4_SEV_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART6_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||||
|
EXPORT DCMI_IRQHandler [WEAK]
|
||||||
|
EXPORT RNG_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
EXPORT UART7_IRQHandler [WEAK]
|
||||||
|
EXPORT UART8_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI6_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI1_IRQHandler [WEAK]
|
||||||
|
EXPORT LTDC_IRQHandler [WEAK]
|
||||||
|
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2D_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI2_IRQHandler [WEAK]
|
||||||
|
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||||
|
EXPORT CEC_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_Master_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI3_IRQHandler [WEAK]
|
||||||
|
EXPORT SWPMI1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM15_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM16_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM17_IRQHandler [WEAK]
|
||||||
|
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT MDIOS_IRQHandler [WEAK]
|
||||||
|
EXPORT JPEG_IRQHandler [WEAK]
|
||||||
|
EXPORT MDMA_IRQHandler [WEAK]
|
||||||
|
EXPORT DSI_IRQHandler [WEAK]
|
||||||
|
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||||
|
EXPORT HSEM1_IRQHandler [WEAK]
|
||||||
|
EXPORT HSEM2_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT COMP1_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT LPUART1_IRQHandler [WEAK]
|
||||||
|
EXPORT WWDG_RST_IRQHandler [WEAK]
|
||||||
|
EXPORT CRS_IRQHandler [WEAK]
|
||||||
|
EXPORT ECC_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI4_IRQHandler [WEAK]
|
||||||
|
EXPORT HOLD_CORE_IRQHandler [WEAK]
|
||||||
|
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_AVD_IRQHandler
|
||||||
|
TAMP_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Stream0_IRQHandler
|
||||||
|
DMA1_Stream1_IRQHandler
|
||||||
|
DMA1_Stream2_IRQHandler
|
||||||
|
DMA1_Stream3_IRQHandler
|
||||||
|
DMA1_Stream4_IRQHandler
|
||||||
|
DMA1_Stream5_IRQHandler
|
||||||
|
DMA1_Stream6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
FDCAN1_IT0_IRQHandler
|
||||||
|
FDCAN2_IT0_IRQHandler
|
||||||
|
FDCAN1_IT1_IRQHandler
|
||||||
|
FDCAN2_IT1_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
TIM8_BRK_TIM12_IRQHandler
|
||||||
|
TIM8_UP_TIM13_IRQHandler
|
||||||
|
TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
TIM8_CC_IRQHandler
|
||||||
|
DMA1_Stream7_IRQHandler
|
||||||
|
FMC_IRQHandler
|
||||||
|
SDMMC1_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
UART5_IRQHandler
|
||||||
|
TIM6_DAC_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
DMA2_Stream0_IRQHandler
|
||||||
|
DMA2_Stream1_IRQHandler
|
||||||
|
DMA2_Stream2_IRQHandler
|
||||||
|
DMA2_Stream3_IRQHandler
|
||||||
|
DMA2_Stream4_IRQHandler
|
||||||
|
ETH_IRQHandler
|
||||||
|
ETH_WKUP_IRQHandler
|
||||||
|
FDCAN_CAL_IRQHandler
|
||||||
|
CM7_SEV_IRQHandler
|
||||||
|
CM4_SEV_IRQHandler
|
||||||
|
DMA2_Stream5_IRQHandler
|
||||||
|
DMA2_Stream6_IRQHandler
|
||||||
|
DMA2_Stream7_IRQHandler
|
||||||
|
USART6_IRQHandler
|
||||||
|
I2C3_EV_IRQHandler
|
||||||
|
I2C3_ER_IRQHandler
|
||||||
|
OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
OTG_HS_EP1_IN_IRQHandler
|
||||||
|
OTG_HS_WKUP_IRQHandler
|
||||||
|
OTG_HS_IRQHandler
|
||||||
|
DCMI_IRQHandler
|
||||||
|
RNG_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
UART7_IRQHandler
|
||||||
|
UART8_IRQHandler
|
||||||
|
SPI4_IRQHandler
|
||||||
|
SPI5_IRQHandler
|
||||||
|
SPI6_IRQHandler
|
||||||
|
SAI1_IRQHandler
|
||||||
|
LTDC_IRQHandler
|
||||||
|
LTDC_ER_IRQHandler
|
||||||
|
DMA2D_IRQHandler
|
||||||
|
SAI2_IRQHandler
|
||||||
|
QUADSPI_IRQHandler
|
||||||
|
LPTIM1_IRQHandler
|
||||||
|
CEC_IRQHandler
|
||||||
|
I2C4_EV_IRQHandler
|
||||||
|
I2C4_ER_IRQHandler
|
||||||
|
SPDIF_RX_IRQHandler
|
||||||
|
OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
OTG_FS_EP1_IN_IRQHandler
|
||||||
|
OTG_FS_WKUP_IRQHandler
|
||||||
|
OTG_FS_IRQHandler
|
||||||
|
DMAMUX1_OVR_IRQHandler
|
||||||
|
HRTIM1_Master_IRQHandler
|
||||||
|
HRTIM1_TIMA_IRQHandler
|
||||||
|
HRTIM1_TIMB_IRQHandler
|
||||||
|
HRTIM1_TIMC_IRQHandler
|
||||||
|
HRTIM1_TIMD_IRQHandler
|
||||||
|
HRTIM1_TIME_IRQHandler
|
||||||
|
HRTIM1_FLT_IRQHandler
|
||||||
|
DFSDM1_FLT0_IRQHandler
|
||||||
|
DFSDM1_FLT1_IRQHandler
|
||||||
|
DFSDM1_FLT2_IRQHandler
|
||||||
|
DFSDM1_FLT3_IRQHandler
|
||||||
|
SAI3_IRQHandler
|
||||||
|
SWPMI1_IRQHandler
|
||||||
|
TIM15_IRQHandler
|
||||||
|
TIM16_IRQHandler
|
||||||
|
TIM17_IRQHandler
|
||||||
|
MDIOS_WKUP_IRQHandler
|
||||||
|
MDIOS_IRQHandler
|
||||||
|
JPEG_IRQHandler
|
||||||
|
MDMA_IRQHandler
|
||||||
|
DSI_IRQHandler
|
||||||
|
SDMMC2_IRQHandler
|
||||||
|
HSEM1_IRQHandler
|
||||||
|
HSEM2_IRQHandler
|
||||||
|
ADC3_IRQHandler
|
||||||
|
DMAMUX2_OVR_IRQHandler
|
||||||
|
BDMA_Channel0_IRQHandler
|
||||||
|
BDMA_Channel1_IRQHandler
|
||||||
|
BDMA_Channel2_IRQHandler
|
||||||
|
BDMA_Channel3_IRQHandler
|
||||||
|
BDMA_Channel4_IRQHandler
|
||||||
|
BDMA_Channel5_IRQHandler
|
||||||
|
BDMA_Channel6_IRQHandler
|
||||||
|
BDMA_Channel7_IRQHandler
|
||||||
|
COMP1_IRQHandler
|
||||||
|
LPTIM2_IRQHandler
|
||||||
|
LPTIM3_IRQHandler
|
||||||
|
LPTIM4_IRQHandler
|
||||||
|
LPTIM5_IRQHandler
|
||||||
|
LPUART1_IRQHandler
|
||||||
|
WWDG_RST_IRQHandler
|
||||||
|
CRS_IRQHandler
|
||||||
|
ECC_IRQHandler
|
||||||
|
SAI4_IRQHandler
|
||||||
|
HOLD_CORE_IRQHandler
|
||||||
|
WAKEUP_PIN_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
@ -11,21 +11,18 @@
|
|||||||
;* After Reset the Cortex-M processor is in Thread mode,
|
;* After Reset the Cortex-M processor is in Thread mode,
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||||
;*******************************************************************************
|
;******************************************************************************
|
||||||
;
|
;* @attention
|
||||||
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
;*
|
||||||
; You may not use this file except in compliance with the License.
|
;* Copyright (c) 2018 STMicroelectronics.
|
||||||
; You may obtain a copy of the License at:
|
;* All rights reserved.
|
||||||
;
|
;*
|
||||||
; http://www.st.com/software_license_agreement_liberty_v2
|
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
;
|
;* the "License"; You may not use this file except in compliance with the
|
||||||
; Unless required by applicable law or agreed to in writing, software
|
;* License. You may obtain a copy of the License at:
|
||||||
; distributed under the License is distributed on an "AS IS" BASIS,
|
;* opensource.org/licenses/BSD-3-Clause
|
||||||
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
;*
|
||||||
; See the License for the specific language governing permissions and
|
;******************************************************************************
|
||||||
; limitations under the License.
|
|
||||||
;
|
|
||||||
;*******************************************************************************
|
|
||||||
|
|
||||||
; Amount of memory (in bytes) allocated for Stack
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
; Tailor this value to your application needs
|
; Tailor this value to your application needs
|
||||||
@ -224,7 +221,7 @@ __Vectors DCD __initial_sp ; Top of Stack
|
|||||||
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||||
DCD 0 ; Reserved
|
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||||
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
@ -433,6 +430,7 @@ Default_Handler PROC
|
|||||||
EXPORT LPTIM5_IRQHandler [WEAK]
|
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||||
EXPORT LPUART1_IRQHandler [WEAK]
|
EXPORT LPUART1_IRQHandler [WEAK]
|
||||||
EXPORT CRS_IRQHandler [WEAK]
|
EXPORT CRS_IRQHandler [WEAK]
|
||||||
|
EXPORT ECC_IRQHandler [WEAK]
|
||||||
EXPORT SAI4_IRQHandler [WEAK]
|
EXPORT SAI4_IRQHandler [WEAK]
|
||||||
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||||
|
|
||||||
@ -574,6 +572,7 @@ LPTIM4_IRQHandler
|
|||||||
LPTIM5_IRQHandler
|
LPTIM5_IRQHandler
|
||||||
LPUART1_IRQHandler
|
LPUART1_IRQHandler
|
||||||
CRS_IRQHandler
|
CRS_IRQHandler
|
||||||
|
ECC_IRQHandler
|
||||||
SAI4_IRQHandler
|
SAI4_IRQHandler
|
||||||
WAKEUP_PIN_IRQHandler
|
WAKEUP_PIN_IRQHandler
|
||||||
|
|
||||||
|
|||||||
@ -11,21 +11,18 @@
|
|||||||
;* After Reset the Cortex-M processor is in Thread mode,
|
;* After Reset the Cortex-M processor is in Thread mode,
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||||
;*******************************************************************************
|
;******************************************************************************
|
||||||
;
|
;* @attention
|
||||||
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
;*
|
||||||
; You may not use this file except in compliance with the License.
|
;* Copyright (c) 2017 STMicroelectronics.
|
||||||
; You may obtain a copy of the License at:
|
;* All rights reserved.
|
||||||
;
|
;*
|
||||||
; http://www.st.com/software_license_agreement_liberty_v2
|
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
;
|
;* the "License"; You may not use this file except in compliance with the
|
||||||
; Unless required by applicable law or agreed to in writing, software
|
;* License. You may obtain a copy of the License at:
|
||||||
; distributed under the License is distributed on an "AS IS" BASIS,
|
;* opensource.org/licenses/BSD-3-Clause
|
||||||
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
;*
|
||||||
; See the License for the specific language governing permissions and
|
;******************************************************************************
|
||||||
; limitations under the License.
|
|
||||||
;
|
|
||||||
;*******************************************************************************
|
|
||||||
|
|
||||||
; Amount of memory (in bytes) allocated for Stack
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
; Tailor this value to your application needs
|
; Tailor this value to your application needs
|
||||||
@ -224,7 +221,7 @@ __Vectors DCD __initial_sp ; Top of Stack
|
|||||||
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||||
DCD 0 ; Reserved
|
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||||
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
@ -433,6 +430,7 @@ Default_Handler PROC
|
|||||||
EXPORT LPTIM5_IRQHandler [WEAK]
|
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||||
EXPORT LPUART1_IRQHandler [WEAK]
|
EXPORT LPUART1_IRQHandler [WEAK]
|
||||||
EXPORT CRS_IRQHandler [WEAK]
|
EXPORT CRS_IRQHandler [WEAK]
|
||||||
|
EXPORT ECC_IRQHandler [WEAK]
|
||||||
EXPORT SAI4_IRQHandler [WEAK]
|
EXPORT SAI4_IRQHandler [WEAK]
|
||||||
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||||
|
|
||||||
@ -574,6 +572,7 @@ LPTIM4_IRQHandler
|
|||||||
LPTIM5_IRQHandler
|
LPTIM5_IRQHandler
|
||||||
LPUART1_IRQHandler
|
LPUART1_IRQHandler
|
||||||
CRS_IRQHandler
|
CRS_IRQHandler
|
||||||
|
ECC_IRQHandler
|
||||||
SAI4_IRQHandler
|
SAI4_IRQHandler
|
||||||
WAKEUP_PIN_IRQHandler
|
WAKEUP_PIN_IRQHandler
|
||||||
|
|
||||||
|
|||||||
@ -0,0 +1,623 @@
|
|||||||
|
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32h755xx.s
|
||||||
|
;* @author MCD Application Team
|
||||||
|
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
;******************************************************************************
|
||||||
|
;* @attention
|
||||||
|
;*
|
||||||
|
;* Copyright (c) 2019 STMicroelectronics.
|
||||||
|
;* All rights reserved.
|
||||||
|
;*
|
||||||
|
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
;* the "License"; You may not use this file except in compliance with the
|
||||||
|
;* License. You may obtain a copy of the License at:
|
||||||
|
;* opensource.org/licenses/BSD-3-Clause
|
||||||
|
;*
|
||||||
|
;******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
|
||||||
|
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
|
||||||
|
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||||
|
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||||
|
DCD FLASH_IRQHandler ; FLASH
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||||
|
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||||
|
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||||
|
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||||
|
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||||
|
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||||
|
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||||
|
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||||
|
DCD ADC_IRQHandler ; ADC1, ADC2
|
||||||
|
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
|
||||||
|
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
|
||||||
|
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
|
||||||
|
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
|
||||||
|
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; External Line[15:10]
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
|
||||||
|
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
|
||||||
|
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
|
||||||
|
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
|
||||||
|
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||||
|
DCD FMC_IRQHandler ; FMC
|
||||||
|
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||||
|
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||||
|
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||||
|
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||||
|
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||||
|
DCD ETH_IRQHandler ; Ethernet
|
||||||
|
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||||
|
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
|
||||||
|
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
|
||||||
|
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||||
|
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||||
|
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||||
|
DCD USART6_IRQHandler ; USART6
|
||||||
|
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||||
|
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||||
|
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||||
|
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||||
|
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||||
|
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||||
|
DCD DCMI_IRQHandler ; DCMI
|
||||||
|
DCD CRYP_IRQHandler ; CRYP crypto
|
||||||
|
DCD HASH_RNG_IRQHandler ; Hash and Rng
|
||||||
|
DCD FPU_IRQHandler ; FPU
|
||||||
|
DCD UART7_IRQHandler ; UART7
|
||||||
|
DCD UART8_IRQHandler ; UART8
|
||||||
|
DCD SPI4_IRQHandler ; SPI4
|
||||||
|
DCD SPI5_IRQHandler ; SPI5
|
||||||
|
DCD SPI6_IRQHandler ; SPI6
|
||||||
|
DCD SAI1_IRQHandler ; SAI1
|
||||||
|
DCD LTDC_IRQHandler ; LTDC
|
||||||
|
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||||
|
DCD DMA2D_IRQHandler ; DMA2D
|
||||||
|
DCD SAI2_IRQHandler ; SAI2
|
||||||
|
DCD QUADSPI_IRQHandler ; QUADSPI
|
||||||
|
DCD LPTIM1_IRQHandler ; LPTIM1
|
||||||
|
DCD CEC_IRQHandler ; HDMI_CEC
|
||||||
|
DCD I2C4_EV_IRQHandler ; I2C4 Event
|
||||||
|
DCD I2C4_ER_IRQHandler ; I2C4 Error
|
||||||
|
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||||
|
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
|
||||||
|
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
|
||||||
|
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
|
||||||
|
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||||
|
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
|
||||||
|
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
|
||||||
|
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
|
||||||
|
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
|
||||||
|
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
|
||||||
|
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
|
||||||
|
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
|
||||||
|
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
|
||||||
|
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
|
||||||
|
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
|
||||||
|
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
|
||||||
|
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
|
||||||
|
DCD SAI3_IRQHandler ; SAI3 global Interrupt
|
||||||
|
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
|
||||||
|
DCD TIM15_IRQHandler ; TIM15 global Interrupt
|
||||||
|
DCD TIM16_IRQHandler ; TIM16 global Interrupt
|
||||||
|
DCD TIM17_IRQHandler ; TIM17 global Interrupt
|
||||||
|
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
|
||||||
|
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
|
||||||
|
DCD JPEG_IRQHandler ; JPEG global Interrupt
|
||||||
|
DCD MDMA_IRQHandler ; MDMA global Interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
|
||||||
|
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
|
||||||
|
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
|
||||||
|
DCD ADC3_IRQHandler ; ADC3 global Interrupt
|
||||||
|
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
|
||||||
|
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
|
||||||
|
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
|
||||||
|
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
|
||||||
|
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
|
||||||
|
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
|
||||||
|
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
|
||||||
|
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
|
||||||
|
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
|
||||||
|
DCD COMP1_IRQHandler ; COMP1 global Interrupt
|
||||||
|
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
|
||||||
|
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
|
||||||
|
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
|
||||||
|
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
|
||||||
|
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||||
|
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
|
||||||
|
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||||
|
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||||
|
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
|
||||||
|
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
|
||||||
|
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_AVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT FMC_IRQHandler [WEAK]
|
||||||
|
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||||
|
EXPORT ETH_IRQHandler [WEAK]
|
||||||
|
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN_CAL_IRQHandler [WEAK]
|
||||||
|
EXPORT CM7_SEV_IRQHandler [WEAK]
|
||||||
|
EXPORT CM4_SEV_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART6_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||||
|
EXPORT DCMI_IRQHandler [WEAK]
|
||||||
|
EXPORT CRYP_IRQHandler [WEAK]
|
||||||
|
EXPORT HASH_RNG_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
EXPORT UART7_IRQHandler [WEAK]
|
||||||
|
EXPORT UART8_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI6_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI1_IRQHandler [WEAK]
|
||||||
|
EXPORT LTDC_IRQHandler [WEAK]
|
||||||
|
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2D_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI2_IRQHandler [WEAK]
|
||||||
|
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||||
|
EXPORT CEC_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_Master_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI3_IRQHandler [WEAK]
|
||||||
|
EXPORT SWPMI1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM15_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM16_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM17_IRQHandler [WEAK]
|
||||||
|
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT MDIOS_IRQHandler [WEAK]
|
||||||
|
EXPORT JPEG_IRQHandler [WEAK]
|
||||||
|
EXPORT MDMA_IRQHandler [WEAK]
|
||||||
|
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||||
|
EXPORT HSEM1_IRQHandler [WEAK]
|
||||||
|
EXPORT HSEM2_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT COMP1_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT LPUART1_IRQHandler [WEAK]
|
||||||
|
EXPORT WWDG_RST_IRQHandler [WEAK]
|
||||||
|
EXPORT CRS_IRQHandler [WEAK]
|
||||||
|
EXPORT ECC_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI4_IRQHandler [WEAK]
|
||||||
|
EXPORT HOLD_CORE_IRQHandler [WEAK]
|
||||||
|
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_AVD_IRQHandler
|
||||||
|
TAMP_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Stream0_IRQHandler
|
||||||
|
DMA1_Stream1_IRQHandler
|
||||||
|
DMA1_Stream2_IRQHandler
|
||||||
|
DMA1_Stream3_IRQHandler
|
||||||
|
DMA1_Stream4_IRQHandler
|
||||||
|
DMA1_Stream5_IRQHandler
|
||||||
|
DMA1_Stream6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
FDCAN1_IT0_IRQHandler
|
||||||
|
FDCAN2_IT0_IRQHandler
|
||||||
|
FDCAN1_IT1_IRQHandler
|
||||||
|
FDCAN2_IT1_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
TIM8_BRK_TIM12_IRQHandler
|
||||||
|
TIM8_UP_TIM13_IRQHandler
|
||||||
|
TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
TIM8_CC_IRQHandler
|
||||||
|
DMA1_Stream7_IRQHandler
|
||||||
|
FMC_IRQHandler
|
||||||
|
SDMMC1_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
UART5_IRQHandler
|
||||||
|
TIM6_DAC_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
DMA2_Stream0_IRQHandler
|
||||||
|
DMA2_Stream1_IRQHandler
|
||||||
|
DMA2_Stream2_IRQHandler
|
||||||
|
DMA2_Stream3_IRQHandler
|
||||||
|
DMA2_Stream4_IRQHandler
|
||||||
|
ETH_IRQHandler
|
||||||
|
ETH_WKUP_IRQHandler
|
||||||
|
FDCAN_CAL_IRQHandler
|
||||||
|
CM7_SEV_IRQHandler
|
||||||
|
CM4_SEV_IRQHandler
|
||||||
|
DMA2_Stream5_IRQHandler
|
||||||
|
DMA2_Stream6_IRQHandler
|
||||||
|
DMA2_Stream7_IRQHandler
|
||||||
|
USART6_IRQHandler
|
||||||
|
I2C3_EV_IRQHandler
|
||||||
|
I2C3_ER_IRQHandler
|
||||||
|
OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
OTG_HS_EP1_IN_IRQHandler
|
||||||
|
OTG_HS_WKUP_IRQHandler
|
||||||
|
OTG_HS_IRQHandler
|
||||||
|
DCMI_IRQHandler
|
||||||
|
CRYP_IRQHandler
|
||||||
|
HASH_RNG_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
UART7_IRQHandler
|
||||||
|
UART8_IRQHandler
|
||||||
|
SPI4_IRQHandler
|
||||||
|
SPI5_IRQHandler
|
||||||
|
SPI6_IRQHandler
|
||||||
|
SAI1_IRQHandler
|
||||||
|
LTDC_IRQHandler
|
||||||
|
LTDC_ER_IRQHandler
|
||||||
|
DMA2D_IRQHandler
|
||||||
|
SAI2_IRQHandler
|
||||||
|
QUADSPI_IRQHandler
|
||||||
|
LPTIM1_IRQHandler
|
||||||
|
CEC_IRQHandler
|
||||||
|
I2C4_EV_IRQHandler
|
||||||
|
I2C4_ER_IRQHandler
|
||||||
|
SPDIF_RX_IRQHandler
|
||||||
|
OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
OTG_FS_EP1_IN_IRQHandler
|
||||||
|
OTG_FS_WKUP_IRQHandler
|
||||||
|
OTG_FS_IRQHandler
|
||||||
|
DMAMUX1_OVR_IRQHandler
|
||||||
|
HRTIM1_Master_IRQHandler
|
||||||
|
HRTIM1_TIMA_IRQHandler
|
||||||
|
HRTIM1_TIMB_IRQHandler
|
||||||
|
HRTIM1_TIMC_IRQHandler
|
||||||
|
HRTIM1_TIMD_IRQHandler
|
||||||
|
HRTIM1_TIME_IRQHandler
|
||||||
|
HRTIM1_FLT_IRQHandler
|
||||||
|
DFSDM1_FLT0_IRQHandler
|
||||||
|
DFSDM1_FLT1_IRQHandler
|
||||||
|
DFSDM1_FLT2_IRQHandler
|
||||||
|
DFSDM1_FLT3_IRQHandler
|
||||||
|
SAI3_IRQHandler
|
||||||
|
SWPMI1_IRQHandler
|
||||||
|
TIM15_IRQHandler
|
||||||
|
TIM16_IRQHandler
|
||||||
|
TIM17_IRQHandler
|
||||||
|
MDIOS_WKUP_IRQHandler
|
||||||
|
MDIOS_IRQHandler
|
||||||
|
JPEG_IRQHandler
|
||||||
|
MDMA_IRQHandler
|
||||||
|
SDMMC2_IRQHandler
|
||||||
|
HSEM1_IRQHandler
|
||||||
|
HSEM2_IRQHandler
|
||||||
|
ADC3_IRQHandler
|
||||||
|
DMAMUX2_OVR_IRQHandler
|
||||||
|
BDMA_Channel0_IRQHandler
|
||||||
|
BDMA_Channel1_IRQHandler
|
||||||
|
BDMA_Channel2_IRQHandler
|
||||||
|
BDMA_Channel3_IRQHandler
|
||||||
|
BDMA_Channel4_IRQHandler
|
||||||
|
BDMA_Channel5_IRQHandler
|
||||||
|
BDMA_Channel6_IRQHandler
|
||||||
|
BDMA_Channel7_IRQHandler
|
||||||
|
COMP1_IRQHandler
|
||||||
|
LPTIM2_IRQHandler
|
||||||
|
LPTIM3_IRQHandler
|
||||||
|
LPTIM4_IRQHandler
|
||||||
|
LPTIM5_IRQHandler
|
||||||
|
LPUART1_IRQHandler
|
||||||
|
WWDG_RST_IRQHandler
|
||||||
|
CRS_IRQHandler
|
||||||
|
ECC_IRQHandler
|
||||||
|
SAI4_IRQHandler
|
||||||
|
HOLD_CORE_IRQHandler
|
||||||
|
WAKEUP_PIN_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
@ -0,0 +1,625 @@
|
|||||||
|
;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32h757xx.s
|
||||||
|
;* @author MCD Application Team
|
||||||
|
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
;******************************************************************************
|
||||||
|
;* @attention
|
||||||
|
;*
|
||||||
|
;* Copyright (c) 2019 STMicroelectronics.
|
||||||
|
;* All rights reserved.
|
||||||
|
;*
|
||||||
|
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
;* the "License"; You may not use this file except in compliance with the
|
||||||
|
;* License. You may obtain a copy of the License at:
|
||||||
|
;* opensource.org/licenses/BSD-3-Clause
|
||||||
|
;*
|
||||||
|
;******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
|
||||||
|
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
|
||||||
|
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||||
|
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||||
|
DCD FLASH_IRQHandler ; FLASH
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||||
|
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||||
|
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||||
|
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||||
|
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||||
|
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||||
|
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||||
|
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||||
|
DCD ADC_IRQHandler ; ADC1, ADC2
|
||||||
|
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
|
||||||
|
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
|
||||||
|
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
|
||||||
|
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
|
||||||
|
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; External Line[15:10]
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
|
||||||
|
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
|
||||||
|
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
|
||||||
|
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
|
||||||
|
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||||
|
DCD FMC_IRQHandler ; FMC
|
||||||
|
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||||
|
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||||
|
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||||
|
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||||
|
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||||
|
DCD ETH_IRQHandler ; Ethernet
|
||||||
|
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||||
|
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
|
||||||
|
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
|
||||||
|
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||||
|
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||||
|
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||||
|
DCD USART6_IRQHandler ; USART6
|
||||||
|
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||||
|
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||||
|
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||||
|
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||||
|
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||||
|
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||||
|
DCD DCMI_IRQHandler ; DCMI
|
||||||
|
DCD CRYP_IRQHandler ; CRYP crypto
|
||||||
|
DCD HASH_RNG_IRQHandler ; Hash and Rng
|
||||||
|
DCD FPU_IRQHandler ; FPU
|
||||||
|
DCD UART7_IRQHandler ; UART7
|
||||||
|
DCD UART8_IRQHandler ; UART8
|
||||||
|
DCD SPI4_IRQHandler ; SPI4
|
||||||
|
DCD SPI5_IRQHandler ; SPI5
|
||||||
|
DCD SPI6_IRQHandler ; SPI6
|
||||||
|
DCD SAI1_IRQHandler ; SAI1
|
||||||
|
DCD LTDC_IRQHandler ; LTDC
|
||||||
|
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||||
|
DCD DMA2D_IRQHandler ; DMA2D
|
||||||
|
DCD SAI2_IRQHandler ; SAI2
|
||||||
|
DCD QUADSPI_IRQHandler ; QUADSPI
|
||||||
|
DCD LPTIM1_IRQHandler ; LPTIM1
|
||||||
|
DCD CEC_IRQHandler ; HDMI_CEC
|
||||||
|
DCD I2C4_EV_IRQHandler ; I2C4 Event
|
||||||
|
DCD I2C4_ER_IRQHandler ; I2C4 Error
|
||||||
|
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||||
|
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
|
||||||
|
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
|
||||||
|
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
|
||||||
|
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||||
|
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
|
||||||
|
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
|
||||||
|
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
|
||||||
|
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
|
||||||
|
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
|
||||||
|
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
|
||||||
|
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
|
||||||
|
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
|
||||||
|
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
|
||||||
|
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
|
||||||
|
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
|
||||||
|
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
|
||||||
|
DCD SAI3_IRQHandler ; SAI3 global Interrupt
|
||||||
|
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
|
||||||
|
DCD TIM15_IRQHandler ; TIM15 global Interrupt
|
||||||
|
DCD TIM16_IRQHandler ; TIM16 global Interrupt
|
||||||
|
DCD TIM17_IRQHandler ; TIM17 global Interrupt
|
||||||
|
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
|
||||||
|
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
|
||||||
|
DCD JPEG_IRQHandler ; JPEG global Interrupt
|
||||||
|
DCD MDMA_IRQHandler ; MDMA global Interrupt
|
||||||
|
DCD DSI_IRQHandler ; DSI global Interrupt
|
||||||
|
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
|
||||||
|
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
|
||||||
|
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
|
||||||
|
DCD ADC3_IRQHandler ; ADC3 global Interrupt
|
||||||
|
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
|
||||||
|
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
|
||||||
|
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
|
||||||
|
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
|
||||||
|
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
|
||||||
|
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
|
||||||
|
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
|
||||||
|
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
|
||||||
|
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
|
||||||
|
DCD COMP1_IRQHandler ; COMP1 global Interrupt
|
||||||
|
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
|
||||||
|
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
|
||||||
|
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
|
||||||
|
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
|
||||||
|
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||||
|
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
|
||||||
|
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||||
|
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||||
|
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
|
||||||
|
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
|
||||||
|
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_AVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT FMC_IRQHandler [WEAK]
|
||||||
|
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||||
|
EXPORT ETH_IRQHandler [WEAK]
|
||||||
|
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FDCAN_CAL_IRQHandler [WEAK]
|
||||||
|
EXPORT CM7_SEV_IRQHandler [WEAK]
|
||||||
|
EXPORT CM4_SEV_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART6_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||||
|
EXPORT DCMI_IRQHandler [WEAK]
|
||||||
|
EXPORT CRYP_IRQHandler [WEAK]
|
||||||
|
EXPORT HASH_RNG_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
EXPORT UART7_IRQHandler [WEAK]
|
||||||
|
EXPORT UART8_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI6_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI1_IRQHandler [WEAK]
|
||||||
|
EXPORT LTDC_IRQHandler [WEAK]
|
||||||
|
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2D_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI2_IRQHandler [WEAK]
|
||||||
|
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||||
|
EXPORT CEC_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_Master_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
|
||||||
|
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
|
||||||
|
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI3_IRQHandler [WEAK]
|
||||||
|
EXPORT SWPMI1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM15_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM16_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM17_IRQHandler [WEAK]
|
||||||
|
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT MDIOS_IRQHandler [WEAK]
|
||||||
|
EXPORT JPEG_IRQHandler [WEAK]
|
||||||
|
EXPORT MDMA_IRQHandler [WEAK]
|
||||||
|
EXPORT DSI_IRQHandler [WEAK]
|
||||||
|
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||||
|
EXPORT HSEM1_IRQHandler [WEAK]
|
||||||
|
EXPORT HSEM2_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT BDMA_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT COMP1_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT LPUART1_IRQHandler [WEAK]
|
||||||
|
EXPORT WWDG_RST_IRQHandler [WEAK]
|
||||||
|
EXPORT CRS_IRQHandler [WEAK]
|
||||||
|
EXPORT ECC_IRQHandler [WEAK]
|
||||||
|
EXPORT SAI4_IRQHandler [WEAK]
|
||||||
|
EXPORT HOLD_CORE_IRQHandler [WEAK]
|
||||||
|
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_AVD_IRQHandler
|
||||||
|
TAMP_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Stream0_IRQHandler
|
||||||
|
DMA1_Stream1_IRQHandler
|
||||||
|
DMA1_Stream2_IRQHandler
|
||||||
|
DMA1_Stream3_IRQHandler
|
||||||
|
DMA1_Stream4_IRQHandler
|
||||||
|
DMA1_Stream5_IRQHandler
|
||||||
|
DMA1_Stream6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
FDCAN1_IT0_IRQHandler
|
||||||
|
FDCAN2_IT0_IRQHandler
|
||||||
|
FDCAN1_IT1_IRQHandler
|
||||||
|
FDCAN2_IT1_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
TIM8_BRK_TIM12_IRQHandler
|
||||||
|
TIM8_UP_TIM13_IRQHandler
|
||||||
|
TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
TIM8_CC_IRQHandler
|
||||||
|
DMA1_Stream7_IRQHandler
|
||||||
|
FMC_IRQHandler
|
||||||
|
SDMMC1_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
UART5_IRQHandler
|
||||||
|
TIM6_DAC_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
DMA2_Stream0_IRQHandler
|
||||||
|
DMA2_Stream1_IRQHandler
|
||||||
|
DMA2_Stream2_IRQHandler
|
||||||
|
DMA2_Stream3_IRQHandler
|
||||||
|
DMA2_Stream4_IRQHandler
|
||||||
|
ETH_IRQHandler
|
||||||
|
ETH_WKUP_IRQHandler
|
||||||
|
FDCAN_CAL_IRQHandler
|
||||||
|
CM7_SEV_IRQHandler
|
||||||
|
CM4_SEV_IRQHandler
|
||||||
|
DMA2_Stream5_IRQHandler
|
||||||
|
DMA2_Stream6_IRQHandler
|
||||||
|
DMA2_Stream7_IRQHandler
|
||||||
|
USART6_IRQHandler
|
||||||
|
I2C3_EV_IRQHandler
|
||||||
|
I2C3_ER_IRQHandler
|
||||||
|
OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
OTG_HS_EP1_IN_IRQHandler
|
||||||
|
OTG_HS_WKUP_IRQHandler
|
||||||
|
OTG_HS_IRQHandler
|
||||||
|
DCMI_IRQHandler
|
||||||
|
CRYP_IRQHandler
|
||||||
|
HASH_RNG_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
UART7_IRQHandler
|
||||||
|
UART8_IRQHandler
|
||||||
|
SPI4_IRQHandler
|
||||||
|
SPI5_IRQHandler
|
||||||
|
SPI6_IRQHandler
|
||||||
|
SAI1_IRQHandler
|
||||||
|
LTDC_IRQHandler
|
||||||
|
LTDC_ER_IRQHandler
|
||||||
|
DMA2D_IRQHandler
|
||||||
|
SAI2_IRQHandler
|
||||||
|
QUADSPI_IRQHandler
|
||||||
|
LPTIM1_IRQHandler
|
||||||
|
CEC_IRQHandler
|
||||||
|
I2C4_EV_IRQHandler
|
||||||
|
I2C4_ER_IRQHandler
|
||||||
|
SPDIF_RX_IRQHandler
|
||||||
|
OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
OTG_FS_EP1_IN_IRQHandler
|
||||||
|
OTG_FS_WKUP_IRQHandler
|
||||||
|
OTG_FS_IRQHandler
|
||||||
|
DMAMUX1_OVR_IRQHandler
|
||||||
|
HRTIM1_Master_IRQHandler
|
||||||
|
HRTIM1_TIMA_IRQHandler
|
||||||
|
HRTIM1_TIMB_IRQHandler
|
||||||
|
HRTIM1_TIMC_IRQHandler
|
||||||
|
HRTIM1_TIMD_IRQHandler
|
||||||
|
HRTIM1_TIME_IRQHandler
|
||||||
|
HRTIM1_FLT_IRQHandler
|
||||||
|
DFSDM1_FLT0_IRQHandler
|
||||||
|
DFSDM1_FLT1_IRQHandler
|
||||||
|
DFSDM1_FLT2_IRQHandler
|
||||||
|
DFSDM1_FLT3_IRQHandler
|
||||||
|
SAI3_IRQHandler
|
||||||
|
SWPMI1_IRQHandler
|
||||||
|
TIM15_IRQHandler
|
||||||
|
TIM16_IRQHandler
|
||||||
|
TIM17_IRQHandler
|
||||||
|
MDIOS_WKUP_IRQHandler
|
||||||
|
MDIOS_IRQHandler
|
||||||
|
JPEG_IRQHandler
|
||||||
|
MDMA_IRQHandler
|
||||||
|
DSI_IRQHandler
|
||||||
|
SDMMC2_IRQHandler
|
||||||
|
HSEM1_IRQHandler
|
||||||
|
HSEM2_IRQHandler
|
||||||
|
ADC3_IRQHandler
|
||||||
|
DMAMUX2_OVR_IRQHandler
|
||||||
|
BDMA_Channel0_IRQHandler
|
||||||
|
BDMA_Channel1_IRQHandler
|
||||||
|
BDMA_Channel2_IRQHandler
|
||||||
|
BDMA_Channel3_IRQHandler
|
||||||
|
BDMA_Channel4_IRQHandler
|
||||||
|
BDMA_Channel5_IRQHandler
|
||||||
|
BDMA_Channel6_IRQHandler
|
||||||
|
BDMA_Channel7_IRQHandler
|
||||||
|
COMP1_IRQHandler
|
||||||
|
LPTIM2_IRQHandler
|
||||||
|
LPTIM3_IRQHandler
|
||||||
|
LPTIM4_IRQHandler
|
||||||
|
LPTIM5_IRQHandler
|
||||||
|
LPUART1_IRQHandler
|
||||||
|
WWDG_RST_IRQHandler
|
||||||
|
CRS_IRQHandler
|
||||||
|
ECC_IRQHandler
|
||||||
|
SAI4_IRQHandler
|
||||||
|
HOLD_CORE_IRQHandler
|
||||||
|
WAKEUP_PIN_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
@ -0,0 +1,189 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 1024Kbytes FLASH and 288Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x10048000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08100000, LENGTH = 1024K
|
||||||
|
RAM (xrw) : ORIGIN = 0x10000000, LENGTH = 288K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,190 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 1024Kbytes FLASH and 192Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20020000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,189 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 128Kbytes FLASH and 160Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x24080000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x24000000, LENGTH = 256K
|
||||||
|
RAM (xrw) : ORIGIN = 0x24040000, LENGTH = 256K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,189 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 128Kbytes FLASH and 160Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x10048000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 128K
|
||||||
|
RAM (xrw) : ORIGIN = 0x10020000, LENGTH = 160K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,189 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 1024Kbytes FLASH and 288Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x10048000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08100000, LENGTH = 1024K
|
||||||
|
RAM (xrw) : ORIGIN = 0x10000000, LENGTH = 288K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,190 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 1024Kbytes FLASH and 192Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20020000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,189 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 128Kbytes FLASH and 160Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x24080000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x24000000, LENGTH = 256K
|
||||||
|
RAM (xrw) : ORIGIN = 0x24040000, LENGTH = 256K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,189 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 128Kbytes FLASH and 160Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x10048000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 128K
|
||||||
|
RAM (xrw) : ORIGIN = 0x10020000, LENGTH = 160K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,189 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 1024Kbytes FLASH and 288Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x10048000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08100000, LENGTH = 1024K
|
||||||
|
RAM (xrw) : ORIGIN = 0x10000000, LENGTH = 288K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,190 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 1024Kbytes FLASH and 192Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20020000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,189 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 128Kbytes FLASH and 160Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x24080000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x24000000, LENGTH = 256K
|
||||||
|
RAM (xrw) : ORIGIN = 0x24040000, LENGTH = 256K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,189 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 128Kbytes FLASH and 160Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x10048000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 128K
|
||||||
|
RAM (xrw) : ORIGIN = 0x10020000, LENGTH = 160K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,189 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 1024Kbytes FLASH and 288Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x10048000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08100000, LENGTH = 1024K
|
||||||
|
RAM (xrw) : ORIGIN = 0x10000000, LENGTH = 288K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,190 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 1024Kbytes FLASH and 192Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20020000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,189 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 128Kbytes FLASH and 160Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x24080000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x24000000, LENGTH = 256K
|
||||||
|
RAM (xrw) : ORIGIN = 0x24040000, LENGTH = 256K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,189 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : Auto-generated by Ac6 System Workbench
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7 series
|
||||||
|
** 128Kbytes FLASH and 160Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed <20>as is,<2C> without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2014 Ac6</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x10048000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 128K
|
||||||
|
RAM (xrw) : ORIGIN = 0x10020000, LENGTH = 160K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,739 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file startup_stm32h742xx.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief STM32H742xx Devices vector table for GCC based toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m7
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
ldr sp, =_estack /* set stack pointer */
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
|
||||||
|
/* External Interrupts */
|
||||||
|
.word WWDG_IRQHandler /* Window WatchDog */
|
||||||
|
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
|
||||||
|
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||||
|
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||||
|
.word FLASH_IRQHandler /* FLASH */
|
||||||
|
.word RCC_IRQHandler /* RCC */
|
||||||
|
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||||
|
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||||
|
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||||
|
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||||
|
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||||
|
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||||
|
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||||
|
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||||
|
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||||
|
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||||
|
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||||
|
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||||
|
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||||
|
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
|
||||||
|
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
|
||||||
|
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
|
||||||
|
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
|
||||||
|
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||||
|
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
|
||||||
|
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
|
||||||
|
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
|
||||||
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
|
.word TIM4_IRQHandler /* TIM4 */
|
||||||
|
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
|
.word USART1_IRQHandler /* USART1 */
|
||||||
|
.word USART2_IRQHandler /* USART2 */
|
||||||
|
.word USART3_IRQHandler /* USART3 */
|
||||||
|
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||||
|
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||||
|
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||||
|
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||||
|
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||||
|
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||||
|
.word FMC_IRQHandler /* FMC */
|
||||||
|
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||||
|
.word TIM5_IRQHandler /* TIM5 */
|
||||||
|
.word SPI3_IRQHandler /* SPI3 */
|
||||||
|
.word UART4_IRQHandler /* UART4 */
|
||||||
|
.word UART5_IRQHandler /* UART5 */
|
||||||
|
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||||
|
.word TIM7_IRQHandler /* TIM7 */
|
||||||
|
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||||
|
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||||
|
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||||
|
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||||
|
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||||
|
.word ETH_IRQHandler /* Ethernet */
|
||||||
|
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||||
|
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||||
|
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||||
|
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||||
|
.word USART6_IRQHandler /* USART6 */
|
||||||
|
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||||
|
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||||
|
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||||
|
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||||
|
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||||
|
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||||
|
.word DCMI_IRQHandler /* DCMI */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word RNG_IRQHandler /* Rng */
|
||||||
|
.word FPU_IRQHandler /* FPU */
|
||||||
|
.word UART7_IRQHandler /* UART7 */
|
||||||
|
.word UART8_IRQHandler /* UART8 */
|
||||||
|
.word SPI4_IRQHandler /* SPI4 */
|
||||||
|
.word SPI5_IRQHandler /* SPI5 */
|
||||||
|
.word SPI6_IRQHandler /* SPI6 */
|
||||||
|
.word SAI1_IRQHandler /* SAI1 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DMA2D_IRQHandler /* DMA2D */
|
||||||
|
.word SAI2_IRQHandler /* SAI2 */
|
||||||
|
.word QUADSPI_IRQHandler /* QUADSPI */
|
||||||
|
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||||
|
.word CEC_IRQHandler /* HDMI_CEC */
|
||||||
|
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||||
|
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||||
|
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||||
|
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
|
||||||
|
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
|
||||||
|
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
|
||||||
|
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||||
|
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
|
||||||
|
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
|
||||||
|
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
|
||||||
|
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
|
||||||
|
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
|
||||||
|
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
|
||||||
|
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
|
||||||
|
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
|
||||||
|
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
|
||||||
|
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
|
||||||
|
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
|
||||||
|
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
|
||||||
|
.word SAI3_IRQHandler /* SAI3 global Interrupt */
|
||||||
|
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
|
||||||
|
.word TIM15_IRQHandler /* TIM15 global Interrupt */
|
||||||
|
.word TIM16_IRQHandler /* TIM16 global Interrupt */
|
||||||
|
.word TIM17_IRQHandler /* TIM17 global Interrupt */
|
||||||
|
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
|
||||||
|
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word MDMA_IRQHandler /* MDMA global Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
|
||||||
|
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word ADC3_IRQHandler /* ADC3 global Interrupt */
|
||||||
|
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
|
||||||
|
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
|
||||||
|
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
|
||||||
|
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
|
||||||
|
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
|
||||||
|
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
|
||||||
|
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
|
||||||
|
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
|
||||||
|
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
|
||||||
|
.word COMP1_IRQHandler /* COMP1 global Interrupt */
|
||||||
|
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
|
||||||
|
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
|
||||||
|
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
|
||||||
|
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
|
||||||
|
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||||
|
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||||
|
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_AVD_IRQHandler
|
||||||
|
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMP_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_IRQHandler
|
||||||
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_BRK_TIM12_IRQHandler
|
||||||
|
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_UP_TIM13_IRQHandler
|
||||||
|
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_CC_IRQHandler
|
||||||
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMC_IRQHandler
|
||||||
|
.thumb_set FMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC1_IRQHandler
|
||||||
|
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_IRQHandler
|
||||||
|
.thumb_set ETH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_WKUP_IRQHandler
|
||||||
|
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN_CAL_IRQHandler
|
||||||
|
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART6_IRQHandler
|
||||||
|
.thumb_set USART6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_EV_IRQHandler
|
||||||
|
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_ER_IRQHandler
|
||||||
|
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_IN_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_IRQHandler
|
||||||
|
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DCMI_IRQHandler
|
||||||
|
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RNG_IRQHandler
|
||||||
|
.thumb_set RNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART7_IRQHandler
|
||||||
|
.thumb_set UART7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART8_IRQHandler
|
||||||
|
.thumb_set UART8_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI4_IRQHandler
|
||||||
|
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI5_IRQHandler
|
||||||
|
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI6_IRQHandler
|
||||||
|
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI1_IRQHandler
|
||||||
|
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2D_IRQHandler
|
||||||
|
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI2_IRQHandler
|
||||||
|
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak QUADSPI_IRQHandler
|
||||||
|
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM1_IRQHandler
|
||||||
|
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CEC_IRQHandler
|
||||||
|
.thumb_set CEC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_EV_IRQHandler
|
||||||
|
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_ER_IRQHandler
|
||||||
|
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPDIF_RX_IRQHandler
|
||||||
|
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_EP1_IN_IRQHandler
|
||||||
|
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_IRQHandler
|
||||||
|
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX1_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_Master_IRQHandler
|
||||||
|
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMA_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMB_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMC_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMD_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIME_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_FLT_IRQHandler
|
||||||
|
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT0_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT1_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT2_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT3_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI3_IRQHandler
|
||||||
|
.thumb_set SAI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SWPMI1_IRQHandler
|
||||||
|
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM15_IRQHandler
|
||||||
|
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM16_IRQHandler
|
||||||
|
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM17_IRQHandler
|
||||||
|
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_WKUP_IRQHandler
|
||||||
|
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_IRQHandler
|
||||||
|
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDMA_IRQHandler
|
||||||
|
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC2_IRQHandler
|
||||||
|
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HSEM1_IRQHandler
|
||||||
|
.thumb_set HSEM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC3_IRQHandler
|
||||||
|
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX2_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel0_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel1_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel2_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel3_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel4_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel5_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel6_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel7_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP1_IRQHandler
|
||||||
|
.thumb_set COMP1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM2_IRQHandler
|
||||||
|
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM3_IRQHandler
|
||||||
|
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM4_IRQHandler
|
||||||
|
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM5_IRQHandler
|
||||||
|
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPUART1_IRQHandler
|
||||||
|
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CRS_IRQHandler
|
||||||
|
.thumb_set CRS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ECC_IRQHandler
|
||||||
|
.thumb_set ECC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI4_IRQHandler
|
||||||
|
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak WAKEUP_PIN_IRQHandler
|
||||||
|
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
@ -14,29 +14,13 @@
|
|||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
@ -303,7 +287,7 @@ g_pfnVectors:
|
|||||||
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||||
.word 0 /* Reserved */
|
.word 0 /* Reserved */
|
||||||
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||||
.word 0 /* Reserved */
|
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||||
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||||
.word 0 /* Reserved */
|
.word 0 /* Reserved */
|
||||||
.word 0 /* Reserved */
|
.word 0 /* Reserved */
|
||||||
@ -751,6 +735,9 @@ g_pfnVectors:
|
|||||||
.weak CRS_IRQHandler
|
.weak CRS_IRQHandler
|
||||||
.thumb_set CRS_IRQHandler,Default_Handler
|
.thumb_set CRS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ECC_IRQHandler
|
||||||
|
.thumb_set ECC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak SAI4_IRQHandler
|
.weak SAI4_IRQHandler
|
||||||
.thumb_set SAI4_IRQHandler,Default_Handler
|
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
|||||||
@ -0,0 +1,763 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file startup_stm32h745xx.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief STM32H745xx Devices vector table for GCC based toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m7
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
ldr sp, =_estack /* set stack pointer */
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
|
||||||
|
/* External Interrupts */
|
||||||
|
.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
|
||||||
|
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
|
||||||
|
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||||
|
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||||
|
.word FLASH_IRQHandler /* FLASH */
|
||||||
|
.word RCC_IRQHandler /* RCC */
|
||||||
|
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||||
|
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||||
|
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||||
|
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||||
|
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||||
|
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||||
|
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||||
|
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||||
|
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||||
|
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||||
|
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||||
|
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||||
|
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||||
|
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
|
||||||
|
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
|
||||||
|
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
|
||||||
|
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
|
||||||
|
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||||
|
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
|
||||||
|
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
|
||||||
|
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
|
||||||
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
|
.word TIM4_IRQHandler /* TIM4 */
|
||||||
|
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
|
.word USART1_IRQHandler /* USART1 */
|
||||||
|
.word USART2_IRQHandler /* USART2 */
|
||||||
|
.word USART3_IRQHandler /* USART3 */
|
||||||
|
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||||
|
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||||
|
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||||
|
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||||
|
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||||
|
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||||
|
.word FMC_IRQHandler /* FMC */
|
||||||
|
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||||
|
.word TIM5_IRQHandler /* TIM5 */
|
||||||
|
.word SPI3_IRQHandler /* SPI3 */
|
||||||
|
.word UART4_IRQHandler /* UART4 */
|
||||||
|
.word UART5_IRQHandler /* UART5 */
|
||||||
|
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||||
|
.word TIM7_IRQHandler /* TIM7 */
|
||||||
|
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||||
|
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||||
|
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||||
|
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||||
|
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||||
|
.word ETH_IRQHandler /* Ethernet */
|
||||||
|
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||||
|
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
|
||||||
|
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
|
||||||
|
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||||
|
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||||
|
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||||
|
.word USART6_IRQHandler /* USART6 */
|
||||||
|
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||||
|
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||||
|
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||||
|
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||||
|
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||||
|
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||||
|
.word DCMI_IRQHandler /* DCMI */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word RNG_IRQHandler /* Rng */
|
||||||
|
.word FPU_IRQHandler /* FPU */
|
||||||
|
.word UART7_IRQHandler /* UART7 */
|
||||||
|
.word UART8_IRQHandler /* UART8 */
|
||||||
|
.word SPI4_IRQHandler /* SPI4 */
|
||||||
|
.word SPI5_IRQHandler /* SPI5 */
|
||||||
|
.word SPI6_IRQHandler /* SPI6 */
|
||||||
|
.word SAI1_IRQHandler /* SAI1 */
|
||||||
|
.word LTDC_IRQHandler /* LTDC */
|
||||||
|
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||||
|
.word DMA2D_IRQHandler /* DMA2D */
|
||||||
|
.word SAI2_IRQHandler /* SAI2 */
|
||||||
|
.word QUADSPI_IRQHandler /* QUADSPI */
|
||||||
|
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||||
|
.word CEC_IRQHandler /* HDMI_CEC */
|
||||||
|
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||||
|
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||||
|
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||||
|
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
|
||||||
|
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
|
||||||
|
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
|
||||||
|
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||||
|
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
|
||||||
|
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
|
||||||
|
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
|
||||||
|
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
|
||||||
|
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
|
||||||
|
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
|
||||||
|
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
|
||||||
|
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
|
||||||
|
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
|
||||||
|
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
|
||||||
|
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
|
||||||
|
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
|
||||||
|
.word SAI3_IRQHandler /* SAI3 global Interrupt */
|
||||||
|
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
|
||||||
|
.word TIM15_IRQHandler /* TIM15 global Interrupt */
|
||||||
|
.word TIM16_IRQHandler /* TIM16 global Interrupt */
|
||||||
|
.word TIM17_IRQHandler /* TIM17 global Interrupt */
|
||||||
|
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
|
||||||
|
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
|
||||||
|
.word JPEG_IRQHandler /* JPEG global Interrupt */
|
||||||
|
.word MDMA_IRQHandler /* MDMA global Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
|
||||||
|
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
|
||||||
|
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
|
||||||
|
.word ADC3_IRQHandler /* ADC3 global Interrupt */
|
||||||
|
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
|
||||||
|
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
|
||||||
|
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
|
||||||
|
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
|
||||||
|
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
|
||||||
|
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
|
||||||
|
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
|
||||||
|
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
|
||||||
|
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
|
||||||
|
.word COMP1_IRQHandler /* COMP1 global Interrupt */
|
||||||
|
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
|
||||||
|
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
|
||||||
|
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
|
||||||
|
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
|
||||||
|
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||||
|
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
|
||||||
|
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||||
|
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||||
|
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||||
|
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_AVD_IRQHandler
|
||||||
|
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMP_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_IRQHandler
|
||||||
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_BRK_TIM12_IRQHandler
|
||||||
|
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_UP_TIM13_IRQHandler
|
||||||
|
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_CC_IRQHandler
|
||||||
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMC_IRQHandler
|
||||||
|
.thumb_set FMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC1_IRQHandler
|
||||||
|
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_IRQHandler
|
||||||
|
.thumb_set ETH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_WKUP_IRQHandler
|
||||||
|
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN_CAL_IRQHandler
|
||||||
|
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CM7_SEV_IRQHandler
|
||||||
|
.thumb_set CM7_SEV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CM4_SEV_IRQHandler
|
||||||
|
.thumb_set CM4_SEV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART6_IRQHandler
|
||||||
|
.thumb_set USART6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_EV_IRQHandler
|
||||||
|
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_ER_IRQHandler
|
||||||
|
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_IN_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_IRQHandler
|
||||||
|
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DCMI_IRQHandler
|
||||||
|
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RNG_IRQHandler
|
||||||
|
.thumb_set RNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART7_IRQHandler
|
||||||
|
.thumb_set UART7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART8_IRQHandler
|
||||||
|
.thumb_set UART8_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI4_IRQHandler
|
||||||
|
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI5_IRQHandler
|
||||||
|
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI6_IRQHandler
|
||||||
|
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI1_IRQHandler
|
||||||
|
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LTDC_IRQHandler
|
||||||
|
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LTDC_ER_IRQHandler
|
||||||
|
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2D_IRQHandler
|
||||||
|
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI2_IRQHandler
|
||||||
|
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak QUADSPI_IRQHandler
|
||||||
|
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM1_IRQHandler
|
||||||
|
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CEC_IRQHandler
|
||||||
|
.thumb_set CEC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_EV_IRQHandler
|
||||||
|
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_ER_IRQHandler
|
||||||
|
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPDIF_RX_IRQHandler
|
||||||
|
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_EP1_IN_IRQHandler
|
||||||
|
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_IRQHandler
|
||||||
|
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX1_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_Master_IRQHandler
|
||||||
|
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMA_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMB_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMC_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMD_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIME_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_FLT_IRQHandler
|
||||||
|
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT0_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT1_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT2_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT3_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI3_IRQHandler
|
||||||
|
.thumb_set SAI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SWPMI1_IRQHandler
|
||||||
|
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM15_IRQHandler
|
||||||
|
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM16_IRQHandler
|
||||||
|
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM17_IRQHandler
|
||||||
|
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_WKUP_IRQHandler
|
||||||
|
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_IRQHandler
|
||||||
|
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak JPEG_IRQHandler
|
||||||
|
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDMA_IRQHandler
|
||||||
|
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC2_IRQHandler
|
||||||
|
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HSEM1_IRQHandler
|
||||||
|
.thumb_set HSEM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HSEM2_IRQHandler
|
||||||
|
.thumb_set HSEM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC3_IRQHandler
|
||||||
|
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX2_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel0_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel1_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel2_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel3_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel4_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel5_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel6_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel7_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP1_IRQHandler
|
||||||
|
.thumb_set COMP1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM2_IRQHandler
|
||||||
|
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM3_IRQHandler
|
||||||
|
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM4_IRQHandler
|
||||||
|
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM5_IRQHandler
|
||||||
|
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPUART1_IRQHandler
|
||||||
|
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_RST_IRQHandler
|
||||||
|
.thumb_set WWDG_RST_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CRS_IRQHandler
|
||||||
|
.thumb_set CRS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ECC_IRQHandler
|
||||||
|
.thumb_set ECC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI4_IRQHandler
|
||||||
|
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HOLD_CORE_IRQHandler
|
||||||
|
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak WAKEUP_PIN_IRQHandler
|
||||||
|
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
@ -0,0 +1,766 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file startup_stm32h747xx.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief STM32H747xx Devices vector table for GCC based toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m7
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
ldr sp, =_estack /* set stack pointer */
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
|
||||||
|
/* External Interrupts */
|
||||||
|
.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
|
||||||
|
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
|
||||||
|
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||||
|
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||||
|
.word FLASH_IRQHandler /* FLASH */
|
||||||
|
.word RCC_IRQHandler /* RCC */
|
||||||
|
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||||
|
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||||
|
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||||
|
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||||
|
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||||
|
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||||
|
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||||
|
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||||
|
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||||
|
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||||
|
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||||
|
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||||
|
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||||
|
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
|
||||||
|
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
|
||||||
|
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
|
||||||
|
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
|
||||||
|
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||||
|
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
|
||||||
|
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
|
||||||
|
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
|
||||||
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
|
.word TIM4_IRQHandler /* TIM4 */
|
||||||
|
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
|
.word USART1_IRQHandler /* USART1 */
|
||||||
|
.word USART2_IRQHandler /* USART2 */
|
||||||
|
.word USART3_IRQHandler /* USART3 */
|
||||||
|
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||||
|
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||||
|
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||||
|
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||||
|
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||||
|
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||||
|
.word FMC_IRQHandler /* FMC */
|
||||||
|
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||||
|
.word TIM5_IRQHandler /* TIM5 */
|
||||||
|
.word SPI3_IRQHandler /* SPI3 */
|
||||||
|
.word UART4_IRQHandler /* UART4 */
|
||||||
|
.word UART5_IRQHandler /* UART5 */
|
||||||
|
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||||
|
.word TIM7_IRQHandler /* TIM7 */
|
||||||
|
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||||
|
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||||
|
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||||
|
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||||
|
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||||
|
.word ETH_IRQHandler /* Ethernet */
|
||||||
|
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||||
|
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
|
||||||
|
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
|
||||||
|
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||||
|
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||||
|
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||||
|
.word USART6_IRQHandler /* USART6 */
|
||||||
|
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||||
|
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||||
|
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||||
|
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||||
|
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||||
|
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||||
|
.word DCMI_IRQHandler /* DCMI */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word RNG_IRQHandler /* Rng */
|
||||||
|
.word FPU_IRQHandler /* FPU */
|
||||||
|
.word UART7_IRQHandler /* UART7 */
|
||||||
|
.word UART8_IRQHandler /* UART8 */
|
||||||
|
.word SPI4_IRQHandler /* SPI4 */
|
||||||
|
.word SPI5_IRQHandler /* SPI5 */
|
||||||
|
.word SPI6_IRQHandler /* SPI6 */
|
||||||
|
.word SAI1_IRQHandler /* SAI1 */
|
||||||
|
.word LTDC_IRQHandler /* LTDC */
|
||||||
|
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||||
|
.word DMA2D_IRQHandler /* DMA2D */
|
||||||
|
.word SAI2_IRQHandler /* SAI2 */
|
||||||
|
.word QUADSPI_IRQHandler /* QUADSPI */
|
||||||
|
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||||
|
.word CEC_IRQHandler /* HDMI_CEC */
|
||||||
|
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||||
|
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||||
|
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||||
|
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
|
||||||
|
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
|
||||||
|
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
|
||||||
|
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||||
|
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
|
||||||
|
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
|
||||||
|
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
|
||||||
|
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
|
||||||
|
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
|
||||||
|
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
|
||||||
|
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
|
||||||
|
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
|
||||||
|
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
|
||||||
|
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
|
||||||
|
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
|
||||||
|
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
|
||||||
|
.word SAI3_IRQHandler /* SAI3 global Interrupt */
|
||||||
|
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
|
||||||
|
.word TIM15_IRQHandler /* TIM15 global Interrupt */
|
||||||
|
.word TIM16_IRQHandler /* TIM16 global Interrupt */
|
||||||
|
.word TIM17_IRQHandler /* TIM17 global Interrupt */
|
||||||
|
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
|
||||||
|
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
|
||||||
|
.word JPEG_IRQHandler /* JPEG global Interrupt */
|
||||||
|
.word MDMA_IRQHandler /* MDMA global Interrupt */
|
||||||
|
.word DSI_IRQHandler /* DSI global Interrupt */
|
||||||
|
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
|
||||||
|
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
|
||||||
|
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
|
||||||
|
.word ADC3_IRQHandler /* ADC3 global Interrupt */
|
||||||
|
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
|
||||||
|
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
|
||||||
|
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
|
||||||
|
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
|
||||||
|
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
|
||||||
|
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
|
||||||
|
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
|
||||||
|
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
|
||||||
|
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
|
||||||
|
.word COMP1_IRQHandler /* COMP1 global Interrupt */
|
||||||
|
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
|
||||||
|
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
|
||||||
|
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
|
||||||
|
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
|
||||||
|
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||||
|
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
|
||||||
|
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||||
|
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||||
|
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||||
|
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_AVD_IRQHandler
|
||||||
|
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMP_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_IRQHandler
|
||||||
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_BRK_TIM12_IRQHandler
|
||||||
|
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_UP_TIM13_IRQHandler
|
||||||
|
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_CC_IRQHandler
|
||||||
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMC_IRQHandler
|
||||||
|
.thumb_set FMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC1_IRQHandler
|
||||||
|
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_IRQHandler
|
||||||
|
.thumb_set ETH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_WKUP_IRQHandler
|
||||||
|
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN_CAL_IRQHandler
|
||||||
|
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CM7_SEV_IRQHandler
|
||||||
|
.thumb_set CM7_SEV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CM4_SEV_IRQHandler
|
||||||
|
.thumb_set CM4_SEV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART6_IRQHandler
|
||||||
|
.thumb_set USART6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_EV_IRQHandler
|
||||||
|
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_ER_IRQHandler
|
||||||
|
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_IN_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_IRQHandler
|
||||||
|
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DCMI_IRQHandler
|
||||||
|
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RNG_IRQHandler
|
||||||
|
.thumb_set RNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART7_IRQHandler
|
||||||
|
.thumb_set UART7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART8_IRQHandler
|
||||||
|
.thumb_set UART8_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI4_IRQHandler
|
||||||
|
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI5_IRQHandler
|
||||||
|
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI6_IRQHandler
|
||||||
|
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI1_IRQHandler
|
||||||
|
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LTDC_IRQHandler
|
||||||
|
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LTDC_ER_IRQHandler
|
||||||
|
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2D_IRQHandler
|
||||||
|
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI2_IRQHandler
|
||||||
|
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak QUADSPI_IRQHandler
|
||||||
|
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM1_IRQHandler
|
||||||
|
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CEC_IRQHandler
|
||||||
|
.thumb_set CEC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_EV_IRQHandler
|
||||||
|
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_ER_IRQHandler
|
||||||
|
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPDIF_RX_IRQHandler
|
||||||
|
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_EP1_IN_IRQHandler
|
||||||
|
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_IRQHandler
|
||||||
|
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX1_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_Master_IRQHandler
|
||||||
|
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMA_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMB_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMC_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMD_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIME_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_FLT_IRQHandler
|
||||||
|
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT0_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT1_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT2_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT3_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI3_IRQHandler
|
||||||
|
.thumb_set SAI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SWPMI1_IRQHandler
|
||||||
|
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM15_IRQHandler
|
||||||
|
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM16_IRQHandler
|
||||||
|
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM17_IRQHandler
|
||||||
|
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_WKUP_IRQHandler
|
||||||
|
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_IRQHandler
|
||||||
|
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak JPEG_IRQHandler
|
||||||
|
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDMA_IRQHandler
|
||||||
|
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DSI_IRQHandler
|
||||||
|
.thumb_set DSI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC2_IRQHandler
|
||||||
|
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HSEM1_IRQHandler
|
||||||
|
.thumb_set HSEM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HSEM2_IRQHandler
|
||||||
|
.thumb_set HSEM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC3_IRQHandler
|
||||||
|
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX2_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel0_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel1_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel2_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel3_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel4_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel5_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel6_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel7_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP1_IRQHandler
|
||||||
|
.thumb_set COMP1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM2_IRQHandler
|
||||||
|
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM3_IRQHandler
|
||||||
|
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM4_IRQHandler
|
||||||
|
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM5_IRQHandler
|
||||||
|
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPUART1_IRQHandler
|
||||||
|
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_RST_IRQHandler
|
||||||
|
.thumb_set WWDG_RST_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CRS_IRQHandler
|
||||||
|
.thumb_set CRS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ECC_IRQHandler
|
||||||
|
.thumb_set ECC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI4_IRQHandler
|
||||||
|
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HOLD_CORE_IRQHandler
|
||||||
|
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak WAKEUP_PIN_IRQHandler
|
||||||
|
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
@ -14,29 +14,13 @@
|
|||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT 2018 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
@ -303,7 +287,7 @@ g_pfnVectors:
|
|||||||
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||||
.word 0 /* Reserved */
|
.word 0 /* Reserved */
|
||||||
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||||
.word 0 /* Reserved */
|
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||||
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||||
.word 0 /* Reserved */
|
.word 0 /* Reserved */
|
||||||
.word 0 /* Reserved */
|
.word 0 /* Reserved */
|
||||||
@ -754,6 +738,9 @@ g_pfnVectors:
|
|||||||
.weak CRS_IRQHandler
|
.weak CRS_IRQHandler
|
||||||
.thumb_set CRS_IRQHandler,Default_Handler
|
.thumb_set CRS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ECC_IRQHandler
|
||||||
|
.thumb_set ECC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak SAI4_IRQHandler
|
.weak SAI4_IRQHandler
|
||||||
.thumb_set SAI4_IRQHandler,Default_Handler
|
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
|||||||
@ -14,29 +14,13 @@
|
|||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
@ -303,7 +287,7 @@ g_pfnVectors:
|
|||||||
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||||
.word 0 /* Reserved */
|
.word 0 /* Reserved */
|
||||||
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||||
.word 0 /* Reserved */
|
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||||
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||||
.word 0 /* Reserved */
|
.word 0 /* Reserved */
|
||||||
.word 0 /* Reserved */
|
.word 0 /* Reserved */
|
||||||
@ -754,6 +738,9 @@ g_pfnVectors:
|
|||||||
.weak CRS_IRQHandler
|
.weak CRS_IRQHandler
|
||||||
.thumb_set CRS_IRQHandler,Default_Handler
|
.thumb_set CRS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ECC_IRQHandler
|
||||||
|
.thumb_set ECC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak SAI4_IRQHandler
|
.weak SAI4_IRQHandler
|
||||||
.thumb_set SAI4_IRQHandler,Default_Handler
|
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
|||||||
@ -0,0 +1,766 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file startup_stm32h755xx.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief STM32H755xx Devices vector table for GCC based toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m7
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
ldr sp, =_estack /* set stack pointer */
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
|
||||||
|
/* External Interrupts */
|
||||||
|
.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
|
||||||
|
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
|
||||||
|
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||||
|
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||||
|
.word FLASH_IRQHandler /* FLASH */
|
||||||
|
.word RCC_IRQHandler /* RCC */
|
||||||
|
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||||
|
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||||
|
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||||
|
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||||
|
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||||
|
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||||
|
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||||
|
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||||
|
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||||
|
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||||
|
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||||
|
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||||
|
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||||
|
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
|
||||||
|
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
|
||||||
|
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
|
||||||
|
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
|
||||||
|
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||||
|
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
|
||||||
|
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
|
||||||
|
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
|
||||||
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
|
.word TIM4_IRQHandler /* TIM4 */
|
||||||
|
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
|
.word USART1_IRQHandler /* USART1 */
|
||||||
|
.word USART2_IRQHandler /* USART2 */
|
||||||
|
.word USART3_IRQHandler /* USART3 */
|
||||||
|
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||||
|
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||||
|
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||||
|
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||||
|
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||||
|
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||||
|
.word FMC_IRQHandler /* FMC */
|
||||||
|
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||||
|
.word TIM5_IRQHandler /* TIM5 */
|
||||||
|
.word SPI3_IRQHandler /* SPI3 */
|
||||||
|
.word UART4_IRQHandler /* UART4 */
|
||||||
|
.word UART5_IRQHandler /* UART5 */
|
||||||
|
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||||
|
.word TIM7_IRQHandler /* TIM7 */
|
||||||
|
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||||
|
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||||
|
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||||
|
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||||
|
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||||
|
.word ETH_IRQHandler /* Ethernet */
|
||||||
|
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||||
|
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
|
||||||
|
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
|
||||||
|
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||||
|
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||||
|
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||||
|
.word USART6_IRQHandler /* USART6 */
|
||||||
|
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||||
|
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||||
|
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||||
|
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||||
|
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||||
|
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||||
|
.word DCMI_IRQHandler /* DCMI */
|
||||||
|
.word CRYP_IRQHandler /* Crypto */
|
||||||
|
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||||
|
.word FPU_IRQHandler /* FPU */
|
||||||
|
.word UART7_IRQHandler /* UART7 */
|
||||||
|
.word UART8_IRQHandler /* UART8 */
|
||||||
|
.word SPI4_IRQHandler /* SPI4 */
|
||||||
|
.word SPI5_IRQHandler /* SPI5 */
|
||||||
|
.word SPI6_IRQHandler /* SPI6 */
|
||||||
|
.word SAI1_IRQHandler /* SAI1 */
|
||||||
|
.word LTDC_IRQHandler /* LTDC */
|
||||||
|
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||||
|
.word DMA2D_IRQHandler /* DMA2D */
|
||||||
|
.word SAI2_IRQHandler /* SAI2 */
|
||||||
|
.word QUADSPI_IRQHandler /* QUADSPI */
|
||||||
|
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||||
|
.word CEC_IRQHandler /* HDMI_CEC */
|
||||||
|
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||||
|
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||||
|
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||||
|
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
|
||||||
|
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
|
||||||
|
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
|
||||||
|
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||||
|
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
|
||||||
|
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
|
||||||
|
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
|
||||||
|
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
|
||||||
|
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
|
||||||
|
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
|
||||||
|
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
|
||||||
|
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
|
||||||
|
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
|
||||||
|
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
|
||||||
|
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
|
||||||
|
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
|
||||||
|
.word SAI3_IRQHandler /* SAI3 global Interrupt */
|
||||||
|
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
|
||||||
|
.word TIM15_IRQHandler /* TIM15 global Interrupt */
|
||||||
|
.word TIM16_IRQHandler /* TIM16 global Interrupt */
|
||||||
|
.word TIM17_IRQHandler /* TIM17 global Interrupt */
|
||||||
|
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
|
||||||
|
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
|
||||||
|
.word JPEG_IRQHandler /* JPEG global Interrupt */
|
||||||
|
.word MDMA_IRQHandler /* MDMA global Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
|
||||||
|
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
|
||||||
|
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
|
||||||
|
.word ADC3_IRQHandler /* ADC3 global Interrupt */
|
||||||
|
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
|
||||||
|
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
|
||||||
|
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
|
||||||
|
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
|
||||||
|
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
|
||||||
|
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
|
||||||
|
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
|
||||||
|
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
|
||||||
|
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
|
||||||
|
.word COMP1_IRQHandler /* COMP1 global Interrupt */
|
||||||
|
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
|
||||||
|
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
|
||||||
|
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
|
||||||
|
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
|
||||||
|
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||||
|
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
|
||||||
|
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||||
|
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||||
|
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||||
|
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_AVD_IRQHandler
|
||||||
|
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMP_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_IRQHandler
|
||||||
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_BRK_TIM12_IRQHandler
|
||||||
|
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_UP_TIM13_IRQHandler
|
||||||
|
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_CC_IRQHandler
|
||||||
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMC_IRQHandler
|
||||||
|
.thumb_set FMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC1_IRQHandler
|
||||||
|
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_IRQHandler
|
||||||
|
.thumb_set ETH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_WKUP_IRQHandler
|
||||||
|
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN_CAL_IRQHandler
|
||||||
|
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CM7_SEV_IRQHandler
|
||||||
|
.thumb_set CM7_SEV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CM4_SEV_IRQHandler
|
||||||
|
.thumb_set CM4_SEV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART6_IRQHandler
|
||||||
|
.thumb_set USART6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_EV_IRQHandler
|
||||||
|
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_ER_IRQHandler
|
||||||
|
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_IN_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_IRQHandler
|
||||||
|
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DCMI_IRQHandler
|
||||||
|
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CRYP_IRQHandler
|
||||||
|
.thumb_set CRYP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HASH_RNG_IRQHandler
|
||||||
|
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART7_IRQHandler
|
||||||
|
.thumb_set UART7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART8_IRQHandler
|
||||||
|
.thumb_set UART8_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI4_IRQHandler
|
||||||
|
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI5_IRQHandler
|
||||||
|
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI6_IRQHandler
|
||||||
|
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI1_IRQHandler
|
||||||
|
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LTDC_IRQHandler
|
||||||
|
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LTDC_ER_IRQHandler
|
||||||
|
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2D_IRQHandler
|
||||||
|
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI2_IRQHandler
|
||||||
|
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak QUADSPI_IRQHandler
|
||||||
|
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM1_IRQHandler
|
||||||
|
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CEC_IRQHandler
|
||||||
|
.thumb_set CEC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_EV_IRQHandler
|
||||||
|
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_ER_IRQHandler
|
||||||
|
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPDIF_RX_IRQHandler
|
||||||
|
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_EP1_IN_IRQHandler
|
||||||
|
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_IRQHandler
|
||||||
|
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX1_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_Master_IRQHandler
|
||||||
|
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMA_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMB_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMC_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMD_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIME_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_FLT_IRQHandler
|
||||||
|
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT0_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT1_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT2_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT3_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI3_IRQHandler
|
||||||
|
.thumb_set SAI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SWPMI1_IRQHandler
|
||||||
|
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM15_IRQHandler
|
||||||
|
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM16_IRQHandler
|
||||||
|
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM17_IRQHandler
|
||||||
|
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_WKUP_IRQHandler
|
||||||
|
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_IRQHandler
|
||||||
|
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak JPEG_IRQHandler
|
||||||
|
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDMA_IRQHandler
|
||||||
|
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC2_IRQHandler
|
||||||
|
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HSEM1_IRQHandler
|
||||||
|
.thumb_set HSEM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HSEM2_IRQHandler
|
||||||
|
.thumb_set HSEM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC3_IRQHandler
|
||||||
|
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX2_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel0_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel1_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel2_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel3_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel4_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel5_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel6_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel7_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP1_IRQHandler
|
||||||
|
.thumb_set COMP1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM2_IRQHandler
|
||||||
|
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM3_IRQHandler
|
||||||
|
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM4_IRQHandler
|
||||||
|
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM5_IRQHandler
|
||||||
|
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPUART1_IRQHandler
|
||||||
|
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_RST_IRQHandler
|
||||||
|
.thumb_set WWDG_RST_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CRS_IRQHandler
|
||||||
|
.thumb_set CRS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ECC_IRQHandler
|
||||||
|
.thumb_set ECC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI4_IRQHandler
|
||||||
|
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HOLD_CORE_IRQHandler
|
||||||
|
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak WAKEUP_PIN_IRQHandler
|
||||||
|
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
@ -0,0 +1,769 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file startup_stm32h757xx.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief STM32H757xx Devices vector table for GCC based toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m7
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
ldr sp, =_estack /* set stack pointer */
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
|
||||||
|
/* External Interrupts */
|
||||||
|
.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
|
||||||
|
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
|
||||||
|
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||||
|
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||||
|
.word FLASH_IRQHandler /* FLASH */
|
||||||
|
.word RCC_IRQHandler /* RCC */
|
||||||
|
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||||
|
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||||
|
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||||
|
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||||
|
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||||
|
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||||
|
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||||
|
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||||
|
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||||
|
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||||
|
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||||
|
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||||
|
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||||
|
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
|
||||||
|
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
|
||||||
|
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
|
||||||
|
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
|
||||||
|
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||||
|
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
|
||||||
|
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
|
||||||
|
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
|
||||||
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
|
.word TIM4_IRQHandler /* TIM4 */
|
||||||
|
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
|
.word USART1_IRQHandler /* USART1 */
|
||||||
|
.word USART2_IRQHandler /* USART2 */
|
||||||
|
.word USART3_IRQHandler /* USART3 */
|
||||||
|
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||||
|
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||||
|
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||||
|
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||||
|
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||||
|
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||||
|
.word FMC_IRQHandler /* FMC */
|
||||||
|
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||||
|
.word TIM5_IRQHandler /* TIM5 */
|
||||||
|
.word SPI3_IRQHandler /* SPI3 */
|
||||||
|
.word UART4_IRQHandler /* UART4 */
|
||||||
|
.word UART5_IRQHandler /* UART5 */
|
||||||
|
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||||
|
.word TIM7_IRQHandler /* TIM7 */
|
||||||
|
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||||
|
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||||
|
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||||
|
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||||
|
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||||
|
.word ETH_IRQHandler /* Ethernet */
|
||||||
|
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||||
|
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
|
||||||
|
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
|
||||||
|
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||||
|
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||||
|
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||||
|
.word USART6_IRQHandler /* USART6 */
|
||||||
|
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||||
|
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||||
|
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||||
|
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||||
|
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||||
|
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||||
|
.word DCMI_IRQHandler /* DCMI */
|
||||||
|
.word CRYP_IRQHandler /* Crypto */
|
||||||
|
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||||
|
.word FPU_IRQHandler /* FPU */
|
||||||
|
.word UART7_IRQHandler /* UART7 */
|
||||||
|
.word UART8_IRQHandler /* UART8 */
|
||||||
|
.word SPI4_IRQHandler /* SPI4 */
|
||||||
|
.word SPI5_IRQHandler /* SPI5 */
|
||||||
|
.word SPI6_IRQHandler /* SPI6 */
|
||||||
|
.word SAI1_IRQHandler /* SAI1 */
|
||||||
|
.word LTDC_IRQHandler /* LTDC */
|
||||||
|
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||||
|
.word DMA2D_IRQHandler /* DMA2D */
|
||||||
|
.word SAI2_IRQHandler /* SAI2 */
|
||||||
|
.word QUADSPI_IRQHandler /* QUADSPI */
|
||||||
|
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||||
|
.word CEC_IRQHandler /* HDMI_CEC */
|
||||||
|
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||||
|
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||||
|
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||||
|
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
|
||||||
|
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
|
||||||
|
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
|
||||||
|
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||||
|
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
|
||||||
|
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
|
||||||
|
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
|
||||||
|
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
|
||||||
|
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
|
||||||
|
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
|
||||||
|
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
|
||||||
|
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
|
||||||
|
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
|
||||||
|
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
|
||||||
|
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
|
||||||
|
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
|
||||||
|
.word SAI3_IRQHandler /* SAI3 global Interrupt */
|
||||||
|
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
|
||||||
|
.word TIM15_IRQHandler /* TIM15 global Interrupt */
|
||||||
|
.word TIM16_IRQHandler /* TIM16 global Interrupt */
|
||||||
|
.word TIM17_IRQHandler /* TIM17 global Interrupt */
|
||||||
|
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
|
||||||
|
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
|
||||||
|
.word JPEG_IRQHandler /* JPEG global Interrupt */
|
||||||
|
.word MDMA_IRQHandler /* MDMA global Interrupt */
|
||||||
|
.word DSI_IRQHandler /* DSI global Interrupt */
|
||||||
|
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
|
||||||
|
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
|
||||||
|
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
|
||||||
|
.word ADC3_IRQHandler /* ADC3 global Interrupt */
|
||||||
|
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
|
||||||
|
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
|
||||||
|
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
|
||||||
|
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
|
||||||
|
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
|
||||||
|
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
|
||||||
|
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
|
||||||
|
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
|
||||||
|
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
|
||||||
|
.word COMP1_IRQHandler /* COMP1 global Interrupt */
|
||||||
|
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
|
||||||
|
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
|
||||||
|
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
|
||||||
|
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
|
||||||
|
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||||
|
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
|
||||||
|
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||||
|
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||||
|
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||||
|
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_AVD_IRQHandler
|
||||||
|
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMP_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_IRQHandler
|
||||||
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_BRK_TIM12_IRQHandler
|
||||||
|
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_UP_TIM13_IRQHandler
|
||||||
|
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_CC_IRQHandler
|
||||||
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMC_IRQHandler
|
||||||
|
.thumb_set FMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC1_IRQHandler
|
||||||
|
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_IRQHandler
|
||||||
|
.thumb_set ETH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_WKUP_IRQHandler
|
||||||
|
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN_CAL_IRQHandler
|
||||||
|
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CM7_SEV_IRQHandler
|
||||||
|
.thumb_set CM7_SEV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CM4_SEV_IRQHandler
|
||||||
|
.thumb_set CM4_SEV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART6_IRQHandler
|
||||||
|
.thumb_set USART6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_EV_IRQHandler
|
||||||
|
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_ER_IRQHandler
|
||||||
|
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_IN_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_IRQHandler
|
||||||
|
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DCMI_IRQHandler
|
||||||
|
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CRYP_IRQHandler
|
||||||
|
.thumb_set CRYP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HASH_RNG_IRQHandler
|
||||||
|
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART7_IRQHandler
|
||||||
|
.thumb_set UART7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART8_IRQHandler
|
||||||
|
.thumb_set UART8_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI4_IRQHandler
|
||||||
|
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI5_IRQHandler
|
||||||
|
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI6_IRQHandler
|
||||||
|
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI1_IRQHandler
|
||||||
|
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LTDC_IRQHandler
|
||||||
|
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LTDC_ER_IRQHandler
|
||||||
|
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2D_IRQHandler
|
||||||
|
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI2_IRQHandler
|
||||||
|
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak QUADSPI_IRQHandler
|
||||||
|
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM1_IRQHandler
|
||||||
|
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CEC_IRQHandler
|
||||||
|
.thumb_set CEC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_EV_IRQHandler
|
||||||
|
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_ER_IRQHandler
|
||||||
|
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPDIF_RX_IRQHandler
|
||||||
|
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_EP1_IN_IRQHandler
|
||||||
|
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_IRQHandler
|
||||||
|
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX1_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_Master_IRQHandler
|
||||||
|
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMA_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMB_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMC_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIMD_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_TIME_IRQHandler
|
||||||
|
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HRTIM1_FLT_IRQHandler
|
||||||
|
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT0_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT1_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT2_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT3_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI3_IRQHandler
|
||||||
|
.thumb_set SAI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SWPMI1_IRQHandler
|
||||||
|
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM15_IRQHandler
|
||||||
|
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM16_IRQHandler
|
||||||
|
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM17_IRQHandler
|
||||||
|
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_WKUP_IRQHandler
|
||||||
|
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_IRQHandler
|
||||||
|
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak JPEG_IRQHandler
|
||||||
|
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDMA_IRQHandler
|
||||||
|
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DSI_IRQHandler
|
||||||
|
.thumb_set DSI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC2_IRQHandler
|
||||||
|
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HSEM1_IRQHandler
|
||||||
|
.thumb_set HSEM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HSEM2_IRQHandler
|
||||||
|
.thumb_set HSEM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC3_IRQHandler
|
||||||
|
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX2_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel0_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel1_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel2_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel3_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel4_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel5_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel6_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA_Channel7_IRQHandler
|
||||||
|
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP1_IRQHandler
|
||||||
|
.thumb_set COMP1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM2_IRQHandler
|
||||||
|
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM3_IRQHandler
|
||||||
|
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM4_IRQHandler
|
||||||
|
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM5_IRQHandler
|
||||||
|
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPUART1_IRQHandler
|
||||||
|
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_RST_IRQHandler
|
||||||
|
.thumb_set WWDG_RST_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CRS_IRQHandler
|
||||||
|
.thumb_set CRS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ECC_IRQHandler
|
||||||
|
.thumb_set ECC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI4_IRQHandler
|
||||||
|
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HOLD_CORE_IRQHandler
|
||||||
|
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak WAKEUP_PIN_IRQHandler
|
||||||
|
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2405FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10007FFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x24000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x2402FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x24030000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2405FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x24000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x10000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x1001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10020000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x24000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x10000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x1001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10020000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x24000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x10000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x1001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10020000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,34 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x24000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x10000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x10000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x1001FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x10020000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
@ -0,0 +1,964 @@
|
|||||||
|
;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32h742xx.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Description : STM32H742xx devices vector table for EWARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == _iar_program_start,
|
||||||
|
;* - Set the vector table entries with the exceptions ISR
|
||||||
|
;* address.
|
||||||
|
;* - Branches to main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;*******************************************************************************
|
||||||
|
;* @attention
|
||||||
|
;*
|
||||||
|
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||||
|
;* All rights reserved.</center></h2>
|
||||||
|
;*
|
||||||
|
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
;* the "License"; You may not use this file except in compliance with the
|
||||||
|
;* License. You may obtain a copy of the License at:
|
||||||
|
;* opensource.org/licenses/BSD-3-Clause
|
||||||
|
;*
|
||||||
|
;*******************************************************************************
|
||||||
|
;
|
||||||
|
;
|
||||||
|
; The modules in this file are included in the libraries, and may be replaced
|
||||||
|
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||||
|
; a user defined start symbol.
|
||||||
|
; To override the cstartup defined in the library, simply add your modified
|
||||||
|
; version to the workbench project.
|
||||||
|
;
|
||||||
|
; The vector table is normally located at address 0.
|
||||||
|
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||||
|
; The name "__vector_table" has special meaning for C-SPY:
|
||||||
|
; it is where the SP start value is found, and the NVIC vector
|
||||||
|
; table register (VTOR) is initialized to this address if != 0.
|
||||||
|
;
|
||||||
|
; Cortex-M version
|
||||||
|
;
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
EXTERN SystemInit
|
||||||
|
PUBLIC __vector_table
|
||||||
|
|
||||||
|
DATA
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK)
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
|
||||||
|
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
|
||||||
|
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||||
|
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||||
|
DCD FLASH_IRQHandler ; FLASH
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||||
|
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||||
|
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||||
|
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||||
|
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||||
|
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||||
|
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||||
|
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||||
|
DCD ADC_IRQHandler ; ADC1, ADC2
|
||||||
|
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
|
||||||
|
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
|
||||||
|
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
|
||||||
|
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
|
||||||
|
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; External Line[15:10]
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
|
||||||
|
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
|
||||||
|
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
|
||||||
|
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
|
||||||
|
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||||
|
DCD FMC_IRQHandler ; FMC
|
||||||
|
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||||
|
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||||
|
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||||
|
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||||
|
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||||
|
DCD ETH_IRQHandler ; Ethernet
|
||||||
|
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||||
|
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||||
|
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||||
|
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||||
|
DCD USART6_IRQHandler ; USART6
|
||||||
|
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||||
|
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||||
|
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||||
|
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||||
|
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||||
|
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||||
|
DCD DCMI_IRQHandler ; DCMI
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD RNG_IRQHandler ; Rng
|
||||||
|
DCD FPU_IRQHandler ; FPU
|
||||||
|
DCD UART7_IRQHandler ; UART7
|
||||||
|
DCD UART8_IRQHandler ; UART8
|
||||||
|
DCD SPI4_IRQHandler ; SPI4
|
||||||
|
DCD SPI5_IRQHandler ; SPI5
|
||||||
|
DCD SPI6_IRQHandler ; SPI6
|
||||||
|
DCD SAI1_IRQHandler ; SAI1
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD DMA2D_IRQHandler ; DMA2D
|
||||||
|
DCD SAI2_IRQHandler ; SAI2
|
||||||
|
DCD QUADSPI_IRQHandler ; QUADSPI
|
||||||
|
DCD LPTIM1_IRQHandler ; LPTIM1
|
||||||
|
DCD CEC_IRQHandler ; HDMI_CEC
|
||||||
|
DCD I2C4_EV_IRQHandler ; I2C4 Event
|
||||||
|
DCD I2C4_ER_IRQHandler ; I2C4 Error
|
||||||
|
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||||
|
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
|
||||||
|
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
|
||||||
|
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
|
||||||
|
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||||
|
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
|
||||||
|
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
|
||||||
|
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
|
||||||
|
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
|
||||||
|
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
|
||||||
|
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
|
||||||
|
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
|
||||||
|
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
|
||||||
|
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
|
||||||
|
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
|
||||||
|
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
|
||||||
|
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
|
||||||
|
DCD SAI3_IRQHandler ; SAI3 global Interrupt
|
||||||
|
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
|
||||||
|
DCD TIM15_IRQHandler ; TIM15 global Interrupt
|
||||||
|
DCD TIM16_IRQHandler ; TIM16 global Interrupt
|
||||||
|
DCD TIM17_IRQHandler ; TIM17 global Interrupt
|
||||||
|
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
|
||||||
|
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD MDMA_IRQHandler ; MDMA global Interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
|
||||||
|
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD ADC3_IRQHandler ; ADC3 global Interrupt
|
||||||
|
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
|
||||||
|
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
|
||||||
|
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
|
||||||
|
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
|
||||||
|
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
|
||||||
|
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
|
||||||
|
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
|
||||||
|
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
|
||||||
|
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
|
||||||
|
DCD COMP1_IRQHandler ; COMP1 global Interrupt
|
||||||
|
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
|
||||||
|
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
|
||||||
|
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
|
||||||
|
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
|
||||||
|
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||||
|
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||||
|
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
THUMB
|
||||||
|
PUBWEAK Reset_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||||
|
Reset_Handler
|
||||||
|
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__iar_program_start
|
||||||
|
BX R0
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HardFault_Handler
|
||||||
|
B HardFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
PendSV_Handler
|
||||||
|
B PendSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SysTick_Handler
|
||||||
|
B SysTick_Handler
|
||||||
|
|
||||||
|
PUBWEAK WWDG_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
WWDG_IRQHandler
|
||||||
|
B WWDG_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PVD_AVD_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
PVD_AVD_IRQHandler
|
||||||
|
B PVD_AVD_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TAMP_STAMP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TAMP_STAMP_IRQHandler
|
||||||
|
B TAMP_STAMP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
B RTC_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FLASH_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FLASH_IRQHandler
|
||||||
|
B FLASH_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RCC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RCC_IRQHandler
|
||||||
|
B RCC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
B EXTI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
B EXTI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
B EXTI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
B EXTI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
B EXTI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Stream0_IRQHandler
|
||||||
|
B DMA1_Stream0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Stream1_IRQHandler
|
||||||
|
B DMA1_Stream1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Stream2_IRQHandler
|
||||||
|
B DMA1_Stream2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Stream3_IRQHandler
|
||||||
|
B DMA1_Stream3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Stream4_IRQHandler
|
||||||
|
B DMA1_Stream4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Stream5_IRQHandler
|
||||||
|
B DMA1_Stream5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Stream6_IRQHandler
|
||||||
|
B DMA1_Stream6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ADC_IRQHandler
|
||||||
|
B ADC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FDCAN1_IT0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FDCAN1_IT0_IRQHandler
|
||||||
|
B FDCAN1_IT0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FDCAN2_IT0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FDCAN2_IT0_IRQHandler
|
||||||
|
B FDCAN2_IT0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FDCAN1_IT1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FDCAN1_IT1_IRQHandler
|
||||||
|
B FDCAN1_IT1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FDCAN2_IT1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FDCAN2_IT1_IRQHandler
|
||||||
|
B FDCAN2_IT1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI9_5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
B EXTI9_5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM1_BRK_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
B TIM1_BRK_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM1_UP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
B TIM1_UP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
B TIM1_TRG_COM_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM1_CC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
B TIM1_CC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM2_IRQHandler
|
||||||
|
B TIM2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM3_IRQHandler
|
||||||
|
B TIM3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM4_IRQHandler
|
||||||
|
B TIM4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
B I2C1_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
B I2C1_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
B I2C2_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
B I2C2_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI1_IRQHandler
|
||||||
|
B SPI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI2_IRQHandler
|
||||||
|
B SPI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART1_IRQHandler
|
||||||
|
B USART1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART2_IRQHandler
|
||||||
|
B USART2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART3_IRQHandler
|
||||||
|
B USART3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI15_10_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
B EXTI15_10_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_Alarm_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
B RTC_Alarm_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM8_BRK_TIM12_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM8_BRK_TIM12_IRQHandler
|
||||||
|
B TIM8_BRK_TIM12_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM8_UP_TIM13_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM8_UP_TIM13_IRQHandler
|
||||||
|
B TIM8_UP_TIM13_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
B TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM8_CC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM8_CC_IRQHandler
|
||||||
|
B TIM8_CC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Stream7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Stream7_IRQHandler
|
||||||
|
B DMA1_Stream7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FMC_IRQHandler
|
||||||
|
B FMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SDMMC1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SDMMC1_IRQHandler
|
||||||
|
B SDMMC1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM5_IRQHandler
|
||||||
|
B TIM5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI3_IRQHandler
|
||||||
|
B SPI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART4_IRQHandler
|
||||||
|
B UART4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART5_IRQHandler
|
||||||
|
B UART5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM6_DAC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM6_DAC_IRQHandler
|
||||||
|
B TIM6_DAC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM7_IRQHandler
|
||||||
|
B TIM7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA2_Stream0_IRQHandler
|
||||||
|
B DMA2_Stream0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA2_Stream1_IRQHandler
|
||||||
|
B DMA2_Stream1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA2_Stream2_IRQHandler
|
||||||
|
B DMA2_Stream2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA2_Stream3_IRQHandler
|
||||||
|
B DMA2_Stream3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA2_Stream4_IRQHandler
|
||||||
|
B DMA2_Stream4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ETH_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ETH_IRQHandler
|
||||||
|
B ETH_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ETH_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ETH_WKUP_IRQHandler
|
||||||
|
B ETH_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FDCAN_CAL_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FDCAN_CAL_IRQHandler
|
||||||
|
B FDCAN_CAL_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA2_Stream5_IRQHandler
|
||||||
|
B DMA2_Stream5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA2_Stream6_IRQHandler
|
||||||
|
B DMA2_Stream6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2_Stream7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA2_Stream7_IRQHandler
|
||||||
|
B DMA2_Stream7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART6_IRQHandler
|
||||||
|
B USART6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C3_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C3_EV_IRQHandler
|
||||||
|
B I2C3_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C3_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C3_ER_IRQHandler
|
||||||
|
B I2C3_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
B OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_HS_EP1_IN_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
OTG_HS_EP1_IN_IRQHandler
|
||||||
|
B OTG_HS_EP1_IN_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_HS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
OTG_HS_WKUP_IRQHandler
|
||||||
|
B OTG_HS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_HS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
OTG_HS_IRQHandler
|
||||||
|
B OTG_HS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DCMI_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DCMI_IRQHandler
|
||||||
|
B DCMI_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RNG_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RNG_IRQHandler
|
||||||
|
B RNG_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FPU_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FPU_IRQHandler
|
||||||
|
B FPU_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART7_IRQHandler
|
||||||
|
B UART7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART8_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART8_IRQHandler
|
||||||
|
B UART8_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI4_IRQHandler
|
||||||
|
B SPI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI5_IRQHandler
|
||||||
|
B SPI5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI6_IRQHandler
|
||||||
|
B SPI6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SAI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SAI1_IRQHandler
|
||||||
|
B SAI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA2D_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA2D_IRQHandler
|
||||||
|
B DMA2D_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SAI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SAI2_IRQHandler
|
||||||
|
B SAI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK QUADSPI_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
QUADSPI_IRQHandler
|
||||||
|
B QUADSPI_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK LPTIM1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
LPTIM1_IRQHandler
|
||||||
|
B LPTIM1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CEC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CEC_IRQHandler
|
||||||
|
B CEC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C4_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C4_EV_IRQHandler
|
||||||
|
B I2C4_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C4_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C4_ER_IRQHandler
|
||||||
|
B I2C4_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPDIF_RX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPDIF_RX_IRQHandler
|
||||||
|
B SPDIF_RX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
B OTG_FS_EP1_OUT_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_FS_EP1_IN_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
OTG_FS_EP1_IN_IRQHandler
|
||||||
|
B OTG_FS_EP1_IN_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_FS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
OTG_FS_WKUP_IRQHandler
|
||||||
|
B OTG_FS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK OTG_FS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
OTG_FS_IRQHandler
|
||||||
|
B OTG_FS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMAMUX1_OVR_IRQHandler
|
||||||
|
B DMAMUX1_OVR_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK HRTIM1_Master_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HRTIM1_Master_IRQHandler
|
||||||
|
B HRTIM1_Master_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK HRTIM1_TIMA_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HRTIM1_TIMA_IRQHandler
|
||||||
|
B HRTIM1_TIMA_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK HRTIM1_TIMB_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HRTIM1_TIMB_IRQHandler
|
||||||
|
B HRTIM1_TIMB_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK HRTIM1_TIMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HRTIM1_TIMC_IRQHandler
|
||||||
|
B HRTIM1_TIMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK HRTIM1_TIMD_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HRTIM1_TIMD_IRQHandler
|
||||||
|
B HRTIM1_TIMD_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK HRTIM1_TIME_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HRTIM1_TIME_IRQHandler
|
||||||
|
B HRTIM1_TIME_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK HRTIM1_FLT_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HRTIM1_FLT_IRQHandler
|
||||||
|
B HRTIM1_FLT_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DFSDM1_FLT0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DFSDM1_FLT0_IRQHandler
|
||||||
|
B DFSDM1_FLT0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DFSDM1_FLT1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DFSDM1_FLT1_IRQHandler
|
||||||
|
B DFSDM1_FLT1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DFSDM1_FLT2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DFSDM1_FLT2_IRQHandler
|
||||||
|
B DFSDM1_FLT2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DFSDM1_FLT3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DFSDM1_FLT3_IRQHandler
|
||||||
|
B DFSDM1_FLT3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SAI3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SAI3_IRQHandler
|
||||||
|
B SAI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SWPMI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SWPMI1_IRQHandler
|
||||||
|
B SWPMI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM15_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM15_IRQHandler
|
||||||
|
B TIM15_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM16_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM16_IRQHandler
|
||||||
|
B TIM16_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIM17_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIM17_IRQHandler
|
||||||
|
B TIM17_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MDIOS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
MDIOS_WKUP_IRQHandler
|
||||||
|
B MDIOS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MDIOS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
MDIOS_IRQHandler
|
||||||
|
B MDIOS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MDMA_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
MDMA_IRQHandler
|
||||||
|
B MDMA_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SDMMC2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SDMMC2_IRQHandler
|
||||||
|
B SDMMC2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK HSEM1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HSEM1_IRQHandler
|
||||||
|
B HSEM1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ADC3_IRQHandler
|
||||||
|
B ADC3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMAMUX2_OVR_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMAMUX2_OVR_IRQHandler
|
||||||
|
B DMAMUX2_OVR_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK BDMA_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BDMA_Channel0_IRQHandler
|
||||||
|
B BDMA_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK BDMA_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BDMA_Channel1_IRQHandler
|
||||||
|
B BDMA_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK BDMA_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BDMA_Channel2_IRQHandler
|
||||||
|
B BDMA_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK BDMA_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BDMA_Channel3_IRQHandler
|
||||||
|
B BDMA_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK BDMA_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BDMA_Channel4_IRQHandler
|
||||||
|
B BDMA_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK BDMA_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BDMA_Channel5_IRQHandler
|
||||||
|
B BDMA_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK BDMA_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BDMA_Channel6_IRQHandler
|
||||||
|
B BDMA_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK BDMA_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BDMA_Channel7_IRQHandler
|
||||||
|
B BDMA_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK COMP1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
COMP1_IRQHandler
|
||||||
|
B COMP1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK LPTIM2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
LPTIM2_IRQHandler
|
||||||
|
B LPTIM2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK LPTIM3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
LPTIM3_IRQHandler
|
||||||
|
B LPTIM3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK LPTIM4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
LPTIM4_IRQHandler
|
||||||
|
B LPTIM4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK LPTIM5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
LPTIM5_IRQHandler
|
||||||
|
B LPTIM5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK LPUART1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
LPUART1_IRQHandler
|
||||||
|
B LPUART1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CRS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CRS_IRQHandler
|
||||||
|
B CRS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ECC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ECC_IRQHandler
|
||||||
|
B ECC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SAI4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SAI4_IRQHandler
|
||||||
|
B SAI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK WAKEUP_PIN_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
WAKEUP_PIN_IRQHandler
|
||||||
|
B WAKEUP_PIN_IRQHandler
|
||||||
|
END
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -11,30 +11,17 @@
|
|||||||
;* calls main()).
|
;* calls main()).
|
||||||
;* After Reset the Cortex-M processor is in Thread mode,
|
;* After Reset the Cortex-M processor is in Thread mode,
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
;********************************************************************************
|
;*******************************************************************************
|
||||||
;*
|
;* @attention
|
||||||
;* Redistribution and use in source and binary forms, with or without modification,
|
;*
|
||||||
;* are permitted provided that the following conditions are met:
|
;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
;* All rights reserved.</center></h2>
|
||||||
;* this list of conditions and the following disclaimer.
|
;*
|
||||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
;* this list of conditions and the following disclaimer in the documentation
|
;* the "License"; You may not use this file except in compliance with the
|
||||||
;* and/or other materials provided with the distribution.
|
;* License. You may obtain a copy of the License at:
|
||||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
;* opensource.org/licenses/BSD-3-Clause
|
||||||
;* may be used to endorse or promote products derived from this software
|
|
||||||
;* without specific prior written permission.
|
|
||||||
;*
|
;*
|
||||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
;*
|
|
||||||
;*******************************************************************************
|
;*******************************************************************************
|
||||||
;
|
;
|
||||||
;
|
;
|
||||||
@ -230,7 +217,7 @@ __vector_table
|
|||||||
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||||
DCD 0 ; Reserved
|
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||||
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
@ -974,6 +961,11 @@ LPUART1_IRQHandler
|
|||||||
CRS_IRQHandler
|
CRS_IRQHandler
|
||||||
B CRS_IRQHandler
|
B CRS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ECC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ECC_IRQHandler
|
||||||
|
B ECC_IRQHandler
|
||||||
|
|
||||||
PUBWEAK SAI4_IRQHandler
|
PUBWEAK SAI4_IRQHandler
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
SAI4_IRQHandler
|
SAI4_IRQHandler
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -11,30 +11,17 @@
|
|||||||
;* calls main()).
|
;* calls main()).
|
||||||
;* After Reset the Cortex-M processor is in Thread mode,
|
;* After Reset the Cortex-M processor is in Thread mode,
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
;********************************************************************************
|
;*******************************************************************************
|
||||||
;*
|
;* @attention
|
||||||
;* Redistribution and use in source and binary forms, with or without modification,
|
;*
|
||||||
;* are permitted provided that the following conditions are met:
|
;* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
;* All rights reserved.</center></h2>
|
||||||
;* this list of conditions and the following disclaimer.
|
;*
|
||||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
;* this list of conditions and the following disclaimer in the documentation
|
;* the "License"; You may not use this file except in compliance with the
|
||||||
;* and/or other materials provided with the distribution.
|
;* License. You may obtain a copy of the License at:
|
||||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
;* opensource.org/licenses/BSD-3-Clause
|
||||||
;* may be used to endorse or promote products derived from this software
|
|
||||||
;* without specific prior written permission.
|
|
||||||
;*
|
;*
|
||||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
;*
|
|
||||||
;*******************************************************************************
|
;*******************************************************************************
|
||||||
;
|
;
|
||||||
;
|
;
|
||||||
@ -230,7 +217,7 @@ __vector_table
|
|||||||
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||||
DCD 0 ; Reserved
|
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||||
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
@ -978,6 +965,11 @@ LPUART1_IRQHandler
|
|||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
CRS_IRQHandler
|
CRS_IRQHandler
|
||||||
B CRS_IRQHandler
|
B CRS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ECC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ECC_IRQHandler
|
||||||
|
B ECC_IRQHandler
|
||||||
|
|
||||||
PUBWEAK SAI4_IRQHandler
|
PUBWEAK SAI4_IRQHandler
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
|||||||
@ -11,30 +11,17 @@
|
|||||||
;* calls main()).
|
;* calls main()).
|
||||||
;* After Reset the Cortex-M processor is in Thread mode,
|
;* After Reset the Cortex-M processor is in Thread mode,
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
;********************************************************************************
|
;*******************************************************************************
|
||||||
;*
|
;* @attention
|
||||||
;* Redistribution and use in source and binary forms, with or without modification,
|
;*
|
||||||
;* are permitted provided that the following conditions are met:
|
;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
;* All rights reserved.</center></h2>
|
||||||
;* this list of conditions and the following disclaimer.
|
;*
|
||||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
;* this list of conditions and the following disclaimer in the documentation
|
;* the "License"; You may not use this file except in compliance with the
|
||||||
;* and/or other materials provided with the distribution.
|
;* License. You may obtain a copy of the License at:
|
||||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
;* opensource.org/licenses/BSD-3-Clause
|
||||||
;* may be used to endorse or promote products derived from this software
|
|
||||||
;* without specific prior written permission.
|
|
||||||
;*
|
;*
|
||||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
;*
|
|
||||||
;*******************************************************************************
|
;*******************************************************************************
|
||||||
;
|
;
|
||||||
;
|
;
|
||||||
@ -230,7 +217,7 @@ __vector_table
|
|||||||
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
DCD LPUART1_IRQHandler ; LP UART1 interrupt
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
|
||||||
DCD 0 ; Reserved
|
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
|
||||||
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
DCD SAI4_IRQHandler ; SAI4 global interrupt
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
DCD 0 ; Reserved
|
DCD 0 ; Reserved
|
||||||
@ -978,6 +965,11 @@ LPUART1_IRQHandler
|
|||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
CRS_IRQHandler
|
CRS_IRQHandler
|
||||||
B CRS_IRQHandler
|
B CRS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ECC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ECC_IRQHandler
|
||||||
|
B ECC_IRQHandler
|
||||||
|
|
||||||
PUBWEAK SAI4_IRQHandler
|
PUBWEAK SAI4_IRQHandler
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user