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https://github.com/elua/elua.git
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Add support for lm3s6965.
This commit is contained in:
Frédéric Thomas
parent
7d89c33c67
commit
05122bca58
@ -4,7 +4,7 @@ cputype = ARGUMENTS.get( 'cpu', 'at91sam7x256' ).lower()
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# List of platform/CPU combinations
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cpu_list = { 'at91sam7x' : [ 'at91sam7x256', 'at91sam7x512' ],
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'lm3s' : [ 'lm3s8962' ],
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'lm3s' : [ 'lm3s8962', 'lm3s6965' ],
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'str9' : [ 'str912fw44' ],
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'i386' : [ 'i386' ]
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}
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@ -52,13 +52,13 @@ To build, go to the directory where you unpacked your eLua distribution and
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invoke scons:
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$ scons [target=<lua|lualong>]
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[cpu=<at91sam7x256|at91sam7x512|i386|str912fw44|lm3s8962>]
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[cpu=<at91sam7x256|at91sam7x512|i386|str912fw44|lm3s8962|lm3s6965>]
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[prog]
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- target=lua | lualong: specify if you want to build full Lua (with floating point
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support) or integer only Lua (lualong). The default is "lua".
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- cpu=at91sam7x256 | at91sam7x512 | i386 | str912fw44 | lm3s8962: specify what
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CPU to build for.
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- cpu=at91sam7x256 | at91sam7x512 | i386 | str912fw44 | lm3s8962 | lm3s6965:
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specify what CPU to build for.
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- prog: by default, the above 'scons' command will build only the 'elf' file.
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Specify "prog" to build also the platform-specific programming file where
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appropriate (for example, on a AT91SAM7X256 this results in a .bin file that
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@ -38,44 +38,28 @@ static int uart_recv()
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// ****************************************************************************
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// Platform initialization
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static const u32 timer_base[] = { TIMER0_BASE, TIMER1_BASE, TIMER2_BASE, TIMER3_BASE };
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// forward
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void timers_init();
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void uarts_init();
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void spis_init();
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void pios_init();
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int platform_init()
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{
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unsigned i;
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// Set the clocking to run directly from the crystal.
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SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ);
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// Enable peripherals
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
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// Setup PIO
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pios_init();
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// Configure the UART for 115,200, 8-N-1 operation.
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// (this also enables the UART)
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GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
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UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200,
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(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
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UART_CONFIG_PAR_NONE));
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// Setup SSIs
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spis_init();
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// Setup UARTs
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uarts_init();
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// Setup timers
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SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER2);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER3);
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for( i = 0; i < 4; i ++ )
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{
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TimerConfigure(timer_base[ i ], TIMER_CFG_32_BIT_PER);
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TimerEnable(timer_base[ i ], TIMER_A);
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}
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timers_init();
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// Set the send/recv functions
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std_set_send_func( uart_send );
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@ -88,9 +72,39 @@ int platform_init()
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// ****************************************************************************
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// PIO
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static const u32 pio_base[] = { GPIO_PORTA_BASE, GPIO_PORTB_BASE, GPIO_PORTC_BASE, GPIO_PORTD_BASE,
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GPIO_PORTE_BASE, GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTH_BASE };
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static const u32 pio_sysctl[] = { SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD,
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SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH };
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#ifdef lm3s8962
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#define PIOS_COUNT 42
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#define PIOS_PORT_COUNT 7
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static const u8 pio_port_pins[] = { 8, 8, 8, 8,
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4, 4, 2, 0 };
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#endif
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#ifdef lm3s6965
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#define PIOS_COUNT 42
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#define PIOS_PORT_COUNT 7
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static const u8 pio_port_pins[] = { 8, 8, 8, 8,
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4, 4, 2, 0 };
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#endif
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void pios_init()
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{
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unsigned i;
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for( i = 0; i < PIOS_PORT_COUNT; i ++ )
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{
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SysCtlPeripheralEnable(pio_sysctl[ i ]);
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}
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}
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int platform_pio_has_port( unsigned port )
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{
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return port <= 6;
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return port < PIOS_PORT_COUNT;
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}
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const char* platform_pio_get_prefix( unsigned port )
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@ -103,21 +117,12 @@ const char* platform_pio_get_prefix( unsigned port )
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int platform_pio_has_pin( unsigned port, unsigned pin )
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{
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if( port <= 3 )
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return pin <= 7;
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else if( ( port == 4 ) || ( port == 5 ) )
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return pin <= 3;
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else if( port == 6 )
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return pin <= 1;
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return 0;
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return pin < pio_port_pins[ port ];
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}
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static const pio_type port_base[] = { GPIO_PORTA_BASE, GPIO_PORTB_BASE, GPIO_PORTC_BASE, GPIO_PORTD_BASE, GPIO_PORTE_BASE,
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GPIO_PORTF_BASE, GPIO_PORTG_BASE };
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pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
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{
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pio_type retval = 0, base = port_base[ port ];
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pio_type retval = 0, base = pio_base[ port ];
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switch( op )
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{
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@ -159,38 +164,65 @@ pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
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// ****************************************************************************
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// SPI
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#define SSI_CLK GPIO_PIN_2
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#define SSI_TX GPIO_PIN_5
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#define SSI_RX GPIO_PIN_4
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#ifdef lm3s8962
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#define SPIS_COUNT 1
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#endif
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#ifdef lm3s6965
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#define SPIS_COUNT 1
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#endif
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// All possible LM3S uarts defs
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// FIXME this anticipates support for a platform with 2 SPI port
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// PIN info extracted from LM3S6950 and 5769 datasheets
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static const u32 spi_base[] = { SSI0_BASE, SSI1_BASE };
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static const u32 spi_sysctl[] = { SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1 };
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static const u32 spi_gpio_base[] = { GPIO_PORTA_BASE | GPIO_PORTE_BASE };
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static const u8 spi_gpio_pins[] = { GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5,
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GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 };
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// SSIxClk SSIxFss SSIxRx SSIxTx
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static const u8 spi_gpio_clk_pin[] = { GPIO_PIN_2, GPIO_PIN_0 };
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void spis_init()
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{
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unsigned i;
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for( i = 0; i < SPIS_COUNT; i ++ )
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{
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SysCtlPeripheralEnable(spi_sysctl[ i ]);
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}
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}
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int platform_spi_exists( unsigned id )
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{
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return id < 1;
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return id < SPIS_COUNT;
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}
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u32 platform_spi_setup( unsigned id, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits )
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{
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unsigned protocol;
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id = id;
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if( cpol == 0 )
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protocol = cpha ? SSI_FRF_MOTO_MODE_1 : SSI_FRF_MOTO_MODE_0;
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else
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protocol = cpha ? SSI_FRF_MOTO_MODE_3 : SSI_FRF_MOTO_MODE_2;
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mode = mode == PLATFORM_SPI_MASTER ? SSI_MODE_MASTER : SSI_MODE_SLAVE;
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SSIDisable( SSI0_BASE );
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GPIOPinTypeSSI(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX);
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GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
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SSIConfigSetExpClk( SSI0_BASE, SysCtlClockGet(), protocol, mode, clock, databits );
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SSIEnable( SSI0_BASE );
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SSIDisable( spi_base[ id ] );
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GPIOPinTypeSSI( spi_gpio_base[ id ], spi_gpio_pins[ id ] );
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// FIXME: not sure this is always "right"
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GPIOPadConfigSet(spi_gpio_base[ id ], spi_gpio_clk_pin[ id ], GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
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SSIConfigSetExpClk( spi_base[ id ], SysCtlClockGet(), protocol, mode, clock, databits );
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SSIEnable( spi_base[ id ] );
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return clock;
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}
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spi_data_type platform_spi_send_recv( unsigned id, spi_data_type data )
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{
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id = id;
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SSIDataPut( SSI0_BASE, data );
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SSIDataGet( SSI0_BASE, &data );
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SSIDataPut( spi_base[ id ], data );
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SSIDataGet( spi_base[ id ], &data );
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return data;
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}
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@ -204,19 +236,48 @@ void platform_spi_select( unsigned id, int is_select )
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// ****************************************************************************
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// UART
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#ifdef lm3s8962
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#define UARTS_COUNT 2
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#endif
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#ifdef lm3s6965
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#define UARTS_COUNT 3
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#endif
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// All possible LM3S uarts defs
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static const u32 uart_base[] = { UART0_BASE, UART1_BASE, UART2_BASE };
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static const u32 uart_sysctl[] = { SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYSCTL_PERIPH_UART2 };
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static const u32 uart_gpio_base[] = { GPIO_PORTA_BASE, GPIO_PORTD_BASE, GPIO_PORTG_BASE };
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static const u8 uart_gpio_pins[] = { GPIO_PIN_0 | GPIO_PIN_1, GPIO_PIN_2 | GPIO_PIN_3, GPIO_PIN_0 | GPIO_PIN_1 };
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void uarts_init()
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{
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unsigned i;
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for( i = 0; i < UARTS_COUNT; i ++ )
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{
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SysCtlPeripheralEnable(uart_sysctl[ i ]);
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}
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// Special case for UART 0
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// Configure the UART for 115,200, 8-N-1 operation.
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GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
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UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), 115200,
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(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
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UART_CONFIG_PAR_NONE));
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}
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int platform_uart_exists( unsigned id )
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{
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return id <= 1;
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return id < UARTS_COUNT;
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}
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u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int stopbits )
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{
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u32 config;
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if( id == 0 )
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GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
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else
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GPIOPinTypeUART(GPIO_PORTD_BASE, GPIO_PIN_2 | GPIO_PIN_3);
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GPIOPinTypeUART(uart_gpio_base [ id ], uart_gpio_pins[ id ]);
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switch( databits )
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{
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case 5:
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@ -239,17 +300,18 @@ u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int st
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config |= UART_CONFIG_PAR_ODD;
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else
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config |= UART_CONFIG_PAR_NONE;
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return UARTConfigSetExpClk(id == 0 ? UART0_BASE : UART1_BASE, SysCtlClockGet(), baud, config);
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return UARTConfigSetExpClk(uart_base[ id ], SysCtlClockGet(), baud, config);
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}
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void platform_uart_send( unsigned id, u8 data )
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{
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UARTCharPut( id == 0 ? UART0_BASE : UART1_BASE, data );
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UARTCharPut( uart_base[ id ], data );
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}
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int platform_uart_recv( unsigned id, unsigned timer_id, int timeout )
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{
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u32 base = id == 0 ? UART0_BASE : UART1_BASE;
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u32 base = uart_base[ id ];
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timer_data_type tmr_start, tmr_crt;
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int res;
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@ -279,11 +341,35 @@ int platform_uart_recv( unsigned id, unsigned timer_id, int timeout )
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}
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// ****************************************************************************
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// Timer
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// Timers
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#ifdef lm3s8962
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#define TIMERS_COUNT 4
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#endif
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#ifdef lm3s6965
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#define TIMERS_COUNT 4
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#endif
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// All possible LM3S timers defs
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static const u32 timer_base[] = { TIMER0_BASE, TIMER1_BASE, TIMER2_BASE, TIMER3_BASE };
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static const u32 timer_sysctl[] = { SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3 };
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void timers_init()
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{
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unsigned i;
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for( i = 0; i < TIMERS_COUNT; i ++ )
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{
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SysCtlPeripheralEnable(timer_sysctl[ i ]);
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TimerConfigure(timer_base[ i ], TIMER_CFG_32_BIT_PER);
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TimerEnable(timer_base[ i ], TIMER_A);
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}
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}
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int platform_timer_exists( unsigned id )
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{
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return id <= 3;
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return id < TIMERS_COUNT;
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}
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void platform_timer_delay( unsigned id, u32 delay_us )
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@ -354,7 +440,12 @@ const char* platform_pd_get_platform_name()
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const char* platform_pd_get_cpu_name()
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{
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#ifdef lm3s8962
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return "LM3S8962";
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#endif
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#ifdef lm3s6965
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return "LM3S6965";
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#endif
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}
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u32 platform_pd_get_cpu_frequency()
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