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Updated library to STM32 FWlib 3.1.

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PWM support integrated, but not fully working.
This commit is contained in:
James Snyder 2009-07-08 23:39:34 +00:00
parent ed31980cb8
commit 05233f2dd2
93 changed files with 25894 additions and 29184 deletions
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src/platform/stm32/FWLib/library/.DS_Store vendored Normal file
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src/platform/stm32/FWLib/library/inc/cortexm3_macro.h
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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : cortexm3_macro.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : Header file for cortexm3_macro.s.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __CORTEXM3_MACRO_H
#define __CORTEXM3_MACRO_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_type.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void __WFI(void);
void __WFE(void);
void __SEV(void);
void __ISB(void);
void __DSB(void);
void __DMB(void);
void __SVC(void);
u32 __MRS_CONTROL(void);
void __MSR_CONTROL(u32 Control);
u32 __MRS_PSP(void);
void __MSR_PSP(u32 TopOfProcessStack);
u32 __MRS_MSP(void);
void __MSR_MSP(u32 TopOfMainStack);
void __RESETPRIMASK(void);
void __SETPRIMASK(void);
u32 __READ_PRIMASK(void);
void __RESETFAULTMASK(void);
void __SETFAULTMASK(void);
u32 __READ_FAULTMASK(void);
void __BASEPRICONFIG(u32 NewPriority);
u32 __GetBASEPRI(void);
u16 __REV_HalfWord(u16 Data);
u32 __REV_Word(u32 Data);
#endif /* __CORTEXM3_MACRO_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

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src/platform/stm32/FWLib/library/inc/misc.h Executable file
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/**
******************************************************************************
* @file misc.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MISC_H
#define __MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/** @defgroup MISC_Exported_Types
* @{
*/
/**
* @brief NVIC Init Structure definition
*/
typedef struct
{
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type
(For the complete STM32 Devices IRQ Channels list, please
refer to stm32f10x.h file) */
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitTypeDef;
/**
* @}
*/
/** @defgroup NVIC_Priority_Table
* @{
*/
/**
@code
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
============================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
============================================================================================================================
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
| | | 4 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
| | | 3 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bits for subpriority
============================================================================================================================
@endcode
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Constants
* @{
*/
/** @defgroup Vector_Table_Base
* @{
*/
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
*/
/** @defgroup System_Low_Power
* @{
*/
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/**
* @}
*/
/** @defgroup Preemption_Priority_Group
* @{
*/
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
/**
* @}
*/
/** @defgroup SysTick_clock_source
* @{
*/
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
/**
* @}
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Functions
* @{
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
#ifdef __cplusplus
}
#endif
#endif /* __MISC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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src/platform/stm32/FWLib/library/inc/stm32f10x_adc.h
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@ -1,57 +1,105 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_adc.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* ADC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_adc.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_ADC_H
#define __STM32F10x_ADC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/** @defgroup ADC_Exported_Types
* @{
*/
/**
* @brief ADC Init structure definition
*/
/* Exported types ------------------------------------------------------------*/
/* ADC Init structure definition */
typedef struct
{
u32 ADC_Mode;
FunctionalState ADC_ScanConvMode;
FunctionalState ADC_ContinuousConvMode;
u32 ADC_ExternalTrigConv;
u32 ADC_DataAlign;
u8 ADC_NbrOfChannel;
uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
dual mode.
This parameter can be a value of @ref ADC_mode */
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
Scan (multichannels) or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
to digital conversion of regular channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align */
uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
using the sequencer for regular channel group.
This parameter must range from 1 to 16. */
}ADC_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
#define IS_ADC_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \
((*(u32*)&(PERIPH)) == ADC2_BASE) || \
((*(u32*)&(PERIPH)) == ADC3_BASE))
#define IS_ADC_DMA_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \
((*(u32*)&(PERIPH)) == ADC3_BASE))
/** @defgroup ADC_Exported_Constants
* @{
*/
/* ADC dual mode -------------------------------------------------------------*/
#define ADC_Mode_Independent ((u32)0x00000000)
#define ADC_Mode_RegInjecSimult ((u32)0x00010000)
#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)
#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)
#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)
#define ADC_Mode_InjecSimult ((u32)0x00050000)
#define ADC_Mode_RegSimult ((u32)0x00060000)
#define ADC_Mode_FastInterl ((u32)0x00070000)
#define ADC_Mode_SlowInterl ((u32)0x00080000)
#define ADC_Mode_AlterTrig ((u32)0x00090000)
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
((PERIPH) == ADC2) || \
((PERIPH) == ADC3))
#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
((PERIPH) == ADC3))
/** @defgroup ADC_mode
* @{
*/
#define ADC_Mode_Independent ((uint32_t)0x00000000)
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
((MODE) == ADC_Mode_RegInjecSimult) || \
@ -63,25 +111,30 @@ typedef struct
((MODE) == ADC_Mode_FastInterl) || \
((MODE) == ADC_Mode_SlowInterl) || \
((MODE) == ADC_Mode_AlterTrig))
/**
* @}
*/
/* ADC external trigger sources for regular channels conversion --------------*/
/* for ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)
#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)
#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)
#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((u32)0x000C0000)
/* for ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)
#define ADC_ExternalTrigConv_None ((u32)0x000E0000)
/* for ADC3 */
#define ADC_ExternalTrigConv_T3_CC1 ((u32)0x00000000)
#define ADC_ExternalTrigConv_T2_CC3 ((u32)0x00020000)
#define ADC_ExternalTrigConv_T8_CC1 ((u32)0x00060000)
#define ADC_ExternalTrigConv_T8_TRGO ((u32)0x00080000)
#define ADC_ExternalTrigConv_T5_CC1 ((u32)0x000A0000)
#define ADC_ExternalTrigConv_T5_CC3 ((u32)0x000C0000)
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
* @{
*/
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
@ -97,33 +150,44 @@ typedef struct
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
/**
* @}
*/
/* ADC data align ------------------------------------------------------------*/
#define ADC_DataAlign_Right ((u32)0x00000000)
#define ADC_DataAlign_Left ((u32)0x00000800)
/** @defgroup ADC_data_align
* @{
*/
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
((ALIGN) == ADC_DataAlign_Left))
/**
* @}
*/
/* ADC channels --------------------------------------------------------------*/
#define ADC_Channel_0 ((u8)0x00)
#define ADC_Channel_1 ((u8)0x01)
#define ADC_Channel_2 ((u8)0x02)
#define ADC_Channel_3 ((u8)0x03)
#define ADC_Channel_4 ((u8)0x04)
#define ADC_Channel_5 ((u8)0x05)
#define ADC_Channel_6 ((u8)0x06)
#define ADC_Channel_7 ((u8)0x07)
#define ADC_Channel_8 ((u8)0x08)
#define ADC_Channel_9 ((u8)0x09)
#define ADC_Channel_10 ((u8)0x0A)
#define ADC_Channel_11 ((u8)0x0B)
#define ADC_Channel_12 ((u8)0x0C)
#define ADC_Channel_13 ((u8)0x0D)
#define ADC_Channel_14 ((u8)0x0E)
#define ADC_Channel_15 ((u8)0x0F)
#define ADC_Channel_16 ((u8)0x10)
#define ADC_Channel_17 ((u8)0x11)
/** @defgroup ADC_channels
* @{
*/
#define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_9 ((uint8_t)0x09)
#define ADC_Channel_10 ((uint8_t)0x0A)
#define ADC_Channel_11 ((uint8_t)0x0B)
#define ADC_Channel_12 ((uint8_t)0x0C)
#define ADC_Channel_13 ((uint8_t)0x0D)
#define ADC_Channel_14 ((uint8_t)0x0E)
#define ADC_Channel_15 ((uint8_t)0x0F)
#define ADC_Channel_16 ((uint8_t)0x10)
#define ADC_Channel_17 ((uint8_t)0x11)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
@ -134,17 +198,22 @@ typedef struct
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
/**
* @}
*/
/* ADC sampling times --------------------------------------------------------*/
#define ADC_SampleTime_1Cycles5 ((u8)0x00)
#define ADC_SampleTime_7Cycles5 ((u8)0x01)
#define ADC_SampleTime_13Cycles5 ((u8)0x02)
#define ADC_SampleTime_28Cycles5 ((u8)0x03)
#define ADC_SampleTime_41Cycles5 ((u8)0x04)
#define ADC_SampleTime_55Cycles5 ((u8)0x05)
#define ADC_SampleTime_71Cycles5 ((u8)0x06)
#define ADC_SampleTime_239Cycles5 ((u8)0x07)
/** @defgroup ADC_sampling_time
* @{
*/
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
((TIME) == ADC_SampleTime_7Cycles5) || \
((TIME) == ADC_SampleTime_13Cycles5) || \
@ -153,24 +222,29 @@ typedef struct
((TIME) == ADC_SampleTime_55Cycles5) || \
((TIME) == ADC_SampleTime_71Cycles5) || \
((TIME) == ADC_SampleTime_239Cycles5))
/**
* @}
*/
/* ADC extrenal trigger sources for injected channels conversion -------------*/
/* For ADC1 and ADC2 */
#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)
#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)
#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((u32)0x00006000)
/* For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)
#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)
/* For ADC3 */
#define ADC_ExternalTrigInjecConv_T4_CC3 ((u32)0x00002000)
#define ADC_ExternalTrigInjecConv_T8_CC2 ((u32)0x00003000)
#define ADC_ExternalTrigInjecConv_T8_CC4 ((u32)0x00004000)
#define ADC_ExternalTrigInjecConv_T5_TRGO ((u32)0x00005000)
#define ADC_ExternalTrigInjecConv_T5_CC4 ((u32)0x00006000)
/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
* @{
*/
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
@ -185,26 +259,37 @@ typedef struct
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
/**
* @}
*/
/* ADC injected channel selection --------------------------------------------*/
#define ADC_InjectedChannel_1 ((u8)0x14)
#define ADC_InjectedChannel_2 ((u8)0x18)
#define ADC_InjectedChannel_3 ((u8)0x1C)
#define ADC_InjectedChannel_4 ((u8)0x20)
/** @defgroup ADC_injected_channel_selection
* @{
*/
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
((CHANNEL) == ADC_InjectedChannel_2) || \
((CHANNEL) == ADC_InjectedChannel_3) || \
((CHANNEL) == ADC_InjectedChannel_4))
/**
* @}
*/
/* ADC analog watchdog selection ---------------------------------------------*/
#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)
#define ADC_AnalogWatchdog_None ((u32)0x00000000)
/** @defgroup ADC_analog_watchdog_selection
* @{
*/
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
@ -213,88 +298,182 @@ typedef struct
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_None))
/**
* @}
*/
/* ADC interrupts definition -------------------------------------------------*/
#define ADC_IT_EOC ((u16)0x0220)
#define ADC_IT_AWD ((u16)0x0140)
#define ADC_IT_JEOC ((u16)0x0480)
/** @defgroup ADC_interrupts_definition
* @{
*/
#define ADC_IT_EOC ((uint16_t)0x0220)
#define ADC_IT_AWD ((uint16_t)0x0140)
#define ADC_IT_JEOC ((uint16_t)0x0480)
#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
#define IS_ADC_IT(IT) ((((IT) & (u16)0xF81F) == 0x00) && ((IT) != 0x00))
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
((IT) == ADC_IT_JEOC))
/**
* @}
*/
/* ADC flags definition ------------------------------------------------------*/
#define ADC_FLAG_AWD ((u8)0x01)
#define ADC_FLAG_EOC ((u8)0x02)
#define ADC_FLAG_JEOC ((u8)0x04)
#define ADC_FLAG_JSTRT ((u8)0x08)
#define ADC_FLAG_STRT ((u8)0x10)
/** @defgroup ADC_flags_definition
* @{
*/
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (u8)0xE0) == 0x00) && ((FLAG) != 0x00))
#define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_JEOC ((uint8_t)0x04)
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
#define ADC_FLAG_STRT ((uint8_t)0x10)
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
((FLAG) == ADC_FLAG_STRT))
/**
* @}
*/
/** @defgroup ADC_thresholds
* @{
*/
/* ADC thresholds ------------------------------------------------------------*/
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
/* ADC injected offset -------------------------------------------------------*/
/**
* @}
*/
/** @defgroup ADC_injected_offset
* @{
*/
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
/* ADC injected length -------------------------------------------------------*/
/**
* @}
*/
/** @defgroup ADC_injected_length
* @{
*/
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
/* ADC injected rank ---------------------------------------------------------*/
/**
* @}
*/
/** @defgroup ADC_injected_rank
* @{
*/
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
/* ADC regular length --------------------------------------------------------*/
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_length
* @{
*/
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_rank
* @{
*/
/* ADC regular rank ----------------------------------------------------------*/
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
/* ADC regular discontinuous mode number -------------------------------------*/
/**
* @}
*/
/** @defgroup ADC_regular_discontinuous_mode_number
* @{
*/
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* @}
*/
/**
* @}
*/
/** @defgroup ADC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup ADC_Exported_Functions
* @{
*/
void ADC_DeInit(ADC_TypeDef* ADCx);
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_StartCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
u32 ADC_GetDualModeConversionValue(void);
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
uint32_t ADC_GetDualModeConversionValue(void);
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F10x_ADC_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

228
src/platform/stm32/FWLib/library/inc/stm32f10x_bkp.h
View File

@ -1,89 +1,129 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_bkp.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* BKP firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_bkp.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the BKP firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_BKP_H
#define __STM32F10x_BKP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#include "stm32f10x.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Tamper Pin active level */
#define BKP_TamperPinLevel_High ((u16)0x0000)
#define BKP_TamperPinLevel_Low ((u16)0x0001)
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup BKP
* @{
*/
/** @defgroup BKP_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Exported_Constants
* @{
*/
/** @defgroup Tamper_Pin_active_level
* @{
*/
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
((LEVEL) == BKP_TamperPinLevel_Low))
/**
* @}
*/
/* RTC output source to output on the Tamper pin */
#define BKP_RTCOutputSource_None ((u16)0x0000)
#define BKP_RTCOutputSource_CalibClock ((u16)0x0080)
#define BKP_RTCOutputSource_Alarm ((u16)0x0100)
#define BKP_RTCOutputSource_Second ((u16)0x0300)
/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
* @{
*/
#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
((SOURCE) == BKP_RTCOutputSource_Alarm) || \
((SOURCE) == BKP_RTCOutputSource_Second))
/**
* @}
*/
/* Data Backup Register */
#define BKP_DR1 ((u16)0x0004)
#define BKP_DR2 ((u16)0x0008)
#define BKP_DR3 ((u16)0x000C)
#define BKP_DR4 ((u16)0x0010)
#define BKP_DR5 ((u16)0x0014)
#define BKP_DR6 ((u16)0x0018)
#define BKP_DR7 ((u16)0x001C)
#define BKP_DR8 ((u16)0x0020)
#define BKP_DR9 ((u16)0x0024)
#define BKP_DR10 ((u16)0x0028)
#define BKP_DR11 ((u16)0x0040)
#define BKP_DR12 ((u16)0x0044)
#define BKP_DR13 ((u16)0x0048)
#define BKP_DR14 ((u16)0x004C)
#define BKP_DR15 ((u16)0x0050)
#define BKP_DR16 ((u16)0x0054)
#define BKP_DR17 ((u16)0x0058)
#define BKP_DR18 ((u16)0x005C)
#define BKP_DR19 ((u16)0x0060)
#define BKP_DR20 ((u16)0x0064)
#define BKP_DR21 ((u16)0x0068)
#define BKP_DR22 ((u16)0x006C)
#define BKP_DR23 ((u16)0x0070)
#define BKP_DR24 ((u16)0x0074)
#define BKP_DR25 ((u16)0x0078)
#define BKP_DR26 ((u16)0x007C)
#define BKP_DR27 ((u16)0x0080)
#define BKP_DR28 ((u16)0x0084)
#define BKP_DR29 ((u16)0x0088)
#define BKP_DR30 ((u16)0x008C)
#define BKP_DR31 ((u16)0x0090)
#define BKP_DR32 ((u16)0x0094)
#define BKP_DR33 ((u16)0x0098)
#define BKP_DR34 ((u16)0x009C)
#define BKP_DR35 ((u16)0x00A0)
#define BKP_DR36 ((u16)0x00A4)
#define BKP_DR37 ((u16)0x00A8)
#define BKP_DR38 ((u16)0x00AC)
#define BKP_DR39 ((u16)0x00B0)
#define BKP_DR40 ((u16)0x00B4)
#define BKP_DR41 ((u16)0x00B8)
#define BKP_DR42 ((u16)0x00BC)
/** @defgroup Data_Backup_Register
* @{
*/
#define BKP_DR1 ((uint16_t)0x0004)
#define BKP_DR2 ((uint16_t)0x0008)
#define BKP_DR3 ((uint16_t)0x000C)
#define BKP_DR4 ((uint16_t)0x0010)
#define BKP_DR5 ((uint16_t)0x0014)
#define BKP_DR6 ((uint16_t)0x0018)
#define BKP_DR7 ((uint16_t)0x001C)
#define BKP_DR8 ((uint16_t)0x0020)
#define BKP_DR9 ((uint16_t)0x0024)
#define BKP_DR10 ((uint16_t)0x0028)
#define BKP_DR11 ((uint16_t)0x0040)
#define BKP_DR12 ((uint16_t)0x0044)
#define BKP_DR13 ((uint16_t)0x0048)
#define BKP_DR14 ((uint16_t)0x004C)
#define BKP_DR15 ((uint16_t)0x0050)
#define BKP_DR16 ((uint16_t)0x0054)
#define BKP_DR17 ((uint16_t)0x0058)
#define BKP_DR18 ((uint16_t)0x005C)
#define BKP_DR19 ((uint16_t)0x0060)
#define BKP_DR20 ((uint16_t)0x0064)
#define BKP_DR21 ((uint16_t)0x0068)
#define BKP_DR22 ((uint16_t)0x006C)
#define BKP_DR23 ((uint16_t)0x0070)
#define BKP_DR24 ((uint16_t)0x0074)
#define BKP_DR25 ((uint16_t)0x0078)
#define BKP_DR26 ((uint16_t)0x007C)
#define BKP_DR27 ((uint16_t)0x0080)
#define BKP_DR28 ((uint16_t)0x0084)
#define BKP_DR29 ((uint16_t)0x0088)
#define BKP_DR30 ((uint16_t)0x008C)
#define BKP_DR31 ((uint16_t)0x0090)
#define BKP_DR32 ((uint16_t)0x0094)
#define BKP_DR33 ((uint16_t)0x0098)
#define BKP_DR34 ((uint16_t)0x009C)
#define BKP_DR35 ((uint16_t)0x00A0)
#define BKP_DR36 ((uint16_t)0x00A4)
#define BKP_DR37 ((uint16_t)0x00A8)
#define BKP_DR38 ((uint16_t)0x00AC)
#define BKP_DR39 ((uint16_t)0x00B0)
#define BKP_DR40 ((uint16_t)0x00B4)
#define BKP_DR41 ((uint16_t)0x00B8)
#define BKP_DR42 ((uint16_t)0x00BC)
#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
@ -101,22 +141,54 @@
((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
/**
* @}
*/
/**
* @}
*/
/** @defgroup BKP_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Exported_Functions
* @{
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void BKP_DeInit(void);
void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel);
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
void BKP_TamperPinCmd(FunctionalState NewState);
void BKP_ITConfig(FunctionalState NewState);
void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource);
void BKP_SetRTCCalibrationValue(u8 CalibrationValue);
void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data);
u16 BKP_ReadBackupRegister(u16 BKP_DR);
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
FlagStatus BKP_GetFlagStatus(void);
void BKP_ClearFlag(void);
ITStatus BKP_GetITStatus(void);
void BKP_ClearITPendingBit(void);
#endif /* __STM32F10x_BKP_H */
#ifdef __cplusplus
}
#endif
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
#endif /* __STM32F10x_BKP_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

616
src/platform/stm32/FWLib/library/inc/stm32f10x_can.h
View File

@ -1,227 +1,465 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_can.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* CAN firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_can.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the CAN firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CAN_H
#define __STM32F10x_CAN_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup CAN
* @{
*/
/** @defgroup CAN_Exported_Types
* @{
*/
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
((PERIPH) == CAN2))
/**
* @brief CAN init structure definition
*/
/* Exported types ------------------------------------------------------------*/
/* CAN init structure definition */
typedef struct
{
FunctionalState CAN_TTCM;
FunctionalState CAN_ABOM;
FunctionalState CAN_AWUM;
FunctionalState CAN_NART;
FunctionalState CAN_RFLM;
FunctionalState CAN_TXFP;
u8 CAN_Mode;
u8 CAN_SJW;
u8 CAN_BS1;
u8 CAN_BS2;
u16 CAN_Prescaler;
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of @ref CAN_operating_mode */
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware
is allowed to lengthen or shorten a bit to perform resynchronization.
This parameter can be a value of @ref CAN_synchronisation_jump_width */
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
This parameter can be set either to ENABLE or DISABLE. */
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
This parameter can be set either to ENABLE or DISABLE. */
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
This parameter can be set either to ENABLE or DISABLE. */
FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode.
This parameter can be set either to ENABLE or DISABLE. */
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
This parameter can be set either to ENABLE or DISABLE. */
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
This parameter can be set either to ENABLE or DISABLE. */
} CAN_InitTypeDef;
/* CAN filter init structure definition */
/**
* @brief CAN filter init structure definition
*/
typedef struct
{
u8 CAN_FilterNumber;
u8 CAN_FilterMode;
u8 CAN_FilterScale;
u16 CAN_FilterIdHigh;
u16 CAN_FilterIdLow;
u16 CAN_FilterMaskIdHigh;
u16 CAN_FilterMaskIdLow;
u16 CAN_FilterFIFOAssignment;
FunctionalState CAN_FilterActivation;
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
This parameter can be set either to ENABLE or DISABLE. */
} CAN_FilterInitTypeDef;
/* CAN Tx message structure definition */
/**
* @brief CAN Tx message structure definition
*/
typedef struct
{
u32 StdId;
u32 ExtId;
u8 IDE;
u8 RTR;
u8 DLC;
u8 Data[8];
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
This parameter can be a value of @ref CAN_identifier_type */
uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter can be a value between 0 to 8 */
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */
} CanTxMsg;
/* CAN Rx message structure definition */
/**
* @brief CAN Rx message structure definition
*/
typedef struct
{
u32 StdId;
u32 ExtId;
u8 IDE;
u8 RTR;
u8 DLC;
u8 Data[8];
u8 FMI;
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received.
This parameter can be a value of @ref CAN_identifier_type */
uint8_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter can be a value between 0 to 8 */
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */
uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
This parameter can be a value between 0 to 0xFF */
} CanRxMsg;
/* Exported constants --------------------------------------------------------*/
/**
* @}
*/
/* CAN sleep constants */
#define CANINITFAILED ((u8)0x00) /* CAN initialization failed */
#define CANINITOK ((u8)0x01) /* CAN initialization failed */
/** @defgroup CAN_Exported_Constants
* @{
*/
/* CAN operating mode */
#define CAN_Mode_Normal ((u8)0x00) /* normal mode */
#define CAN_Mode_LoopBack ((u8)0x01) /* loopback mode */
#define CAN_Mode_Silent ((u8)0x02) /* silent mode */
#define CAN_Mode_Silent_LoopBack ((u8)0x03) /* loopback combined with silent mode */
/** @defgroup CAN_sleep_constants
* @{
*/
#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */
#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */
/**
* @}
*/
/** @defgroup CAN_operating_mode
* @{
*/
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \
((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))
/**
* @}
*/
/* CAN synchronisation jump width */
#define CAN_SJW_1tq ((u8)0x00) /* 1 time quantum */
#define CAN_SJW_2tq ((u8)0x01) /* 2 time quantum */
#define CAN_SJW_3tq ((u8)0x02) /* 3 time quantum */
#define CAN_SJW_4tq ((u8)0x03) /* 4 time quantum */
/** @defgroup CAN_synchronisation_jump_width
* @{
*/
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
/**
* @}
*/
/* time quantum in bit segment 1 */
#define CAN_BS1_1tq ((u8)0x00) /* 1 time quantum */
#define CAN_BS1_2tq ((u8)0x01) /* 2 time quantum */
#define CAN_BS1_3tq ((u8)0x02) /* 3 time quantum */
#define CAN_BS1_4tq ((u8)0x03) /* 4 time quantum */
#define CAN_BS1_5tq ((u8)0x04) /* 5 time quantum */
#define CAN_BS1_6tq ((u8)0x05) /* 6 time quantum */
#define CAN_BS1_7tq ((u8)0x06) /* 7 time quantum */
#define CAN_BS1_8tq ((u8)0x07) /* 8 time quantum */
#define CAN_BS1_9tq ((u8)0x08) /* 9 time quantum */
#define CAN_BS1_10tq ((u8)0x09) /* 10 time quantum */
#define CAN_BS1_11tq ((u8)0x0A) /* 11 time quantum */
#define CAN_BS1_12tq ((u8)0x0B) /* 12 time quantum */
#define CAN_BS1_13tq ((u8)0x0C) /* 13 time quantum */
#define CAN_BS1_14tq ((u8)0x0D) /* 14 time quantum */
#define CAN_BS1_15tq ((u8)0x0E) /* 15 time quantum */
#define CAN_BS1_16tq ((u8)0x0F) /* 16 time quantum */
/** @defgroup CAN_time_quantum_in_bit_segment_1
* @{
*/
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
/**
* @}
*/
/* time quantum in bit segment 2 */
#define CAN_BS2_1tq ((u8)0x00) /* 1 time quantum */
#define CAN_BS2_2tq ((u8)0x01) /* 2 time quantum */
#define CAN_BS2_3tq ((u8)0x02) /* 3 time quantum */
#define CAN_BS2_4tq ((u8)0x03) /* 4 time quantum */
#define CAN_BS2_5tq ((u8)0x04) /* 5 time quantum */
#define CAN_BS2_6tq ((u8)0x05) /* 6 time quantum */
#define CAN_BS2_7tq ((u8)0x06) /* 7 time quantum */
#define CAN_BS2_8tq ((u8)0x07) /* 8 time quantum */
/** @defgroup CAN_time_quantum_in_bit_segment_2
* @{
*/
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
/* CAN clock prescaler */
/**
* @}
*/
/** @defgroup CAN_clock_prescaler
* @{
*/
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
/* CAN filter number */
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
/**
* @}
*/
/* CAN filter mode */
#define CAN_FilterMode_IdMask ((u8)0x00) /* id/mask mode */
#define CAN_FilterMode_IdList ((u8)0x01) /* identifier list mode */
/** @defgroup CAN_filter_number
* @{
*/
#ifndef STM32F10X_CL
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
#else
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
#endif /* STM32F10X_CL */
/**
* @}
*/
/** @defgroup CAN_filter_mode
* @{
*/
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
((MODE) == CAN_FilterMode_IdList))
/**
* @}
*/
/* CAN filter scale */
#define CAN_FilterScale_16bit ((u8)0x00) /* 16-bit filter scale */
#define CAN_FilterScale_32bit ((u8)0x01) /* 2-bit filter scale */
/** @defgroup CAN_filter_scale
* @{
*/
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
((SCALE) == CAN_FilterScale_32bit))
/* CAN filter FIFO assignation */
#define CAN_FilterFIFO0 ((u8)0x00) /* Filter FIFO 0 assignment for filter x */
#define CAN_FilterFIFO1 ((u8)0x01) /* Filter FIFO 1 assignment for filter x */
/**
* @}
*/
/** @defgroup CAN_filter_FIFO
* @{
*/
#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
((FIFO) == CAN_FilterFIFO1))
/* CAN Tx */
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((u8)0x02))
#define IS_CAN_STDID(STDID) ((STDID) <= ((u32)0x7FF))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((u32)0x1FFFFFFF))
#define IS_CAN_DLC(DLC) ((DLC) <= ((u8)0x08))
/**
* @}
*/
/* CAN identifier type */
#define CAN_ID_STD ((u32)0x00000000) /* Standard Id */
#define CAN_ID_EXT ((u32)0x00000004) /* Extended Id */
/** @defgroup Start_bank_filter_for_slave_CAN
* @{
*/
#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
/**
* @}
*/
/** @defgroup CAN_Tx
* @{
*/
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
/**
* @}
*/
/** @defgroup CAN_identifier_type
* @{
*/
#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT))
/* CAN remote transmission request */
#define CAN_RTR_DATA ((u32)0x00000000) /* Data frame */
#define CAN_RTR_REMOTE ((u32)0x00000002) /* Remote frame */
/**
* @}
*/
/** @defgroup CAN_remote_transmission_request
* @{
*/
#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
/* CAN transmit constants */
#define CANTXFAILED ((u8)0x00) /* CAN transmission failed */
#define CANTXOK ((u8)0x01) /* CAN transmission succeeded */
#define CANTXPENDING ((u8)0x02) /* CAN transmission pending */
#define CAN_NO_MB ((u8)0x04) /* CAN cell did not provide an empty mailbox */
/**
* @}
*/
/* CAN receive FIFO number constants */
#define CAN_FIFO0 ((u8)0x00) /* CAN FIFO0 used to receive */
#define CAN_FIFO1 ((u8)0x01) /* CAN FIFO1 used to receive */
/** @defgroup CAN_transmit_constants
* @{
*/
#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */
#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */
#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */
#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
/**
* @}
*/
/** @defgroup CAN_receive_FIFO_number_constants
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
/* CAN sleep constants */
#define CANSLEEPFAILED ((u8)0x00) /* CAN did not enter the sleep mode */
#define CANSLEEPOK ((u8)0x01) /* CAN entered the sleep mode */
/**
* @}
*/
/* CAN wake up constants */
#define CANWAKEUPFAILED ((u8)0x00) /* CAN did not leave the sleep mode */
#define CANWAKEUPOK ((u8)0x01) /* CAN leaved the sleep mode */
/** @defgroup CAN_sleep_constants
* @{
*/
/* CAN flags */
#define CAN_FLAG_EWG ((u32)0x00000001) /* Error Warning Flag */
#define CAN_FLAG_EPV ((u32)0x00000002) /* Error Passive Flag */
#define CAN_FLAG_BOF ((u32)0x00000004) /* Bus-Off Flag */
#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */
/**
* @}
*/
/** @defgroup CAN_wake_up_constants
* @{
*/
#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
/**
* @}
*/
/** @defgroup CAN_flags
* @{
*/
#define CAN_FLAG_EWG ((uint32_t)0x00000001) /*!< Error Warning Flag */
#define CAN_FLAG_EPV ((uint32_t)0x00000002) /*!< Error Passive Flag */
#define CAN_FLAG_BOF ((uint32_t)0x00000004) /*!< Bus-Off Flag */
#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\
((FLAG) == CAN_FLAG_BOF))
/* CAN interrupts */
#define CAN_IT_RQCP0 ((u32)0x00000005) /* Request completed mailbox 0 */
#define CAN_IT_RQCP1 ((u32)0x00000006) /* Request completed mailbox 1 */
#define CAN_IT_RQCP2 ((u32)0x00000007) /* Request completed mailbox 2 */
#define CAN_IT_TME ((u32)0x00000001) /* Transmit mailbox empty */
#define CAN_IT_FMP0 ((u32)0x00000002) /* FIFO 0 message pending */
#define CAN_IT_FF0 ((u32)0x00000004) /* FIFO 0 full */
#define CAN_IT_FOV0 ((u32)0x00000008) /* FIFO 0 overrun */
#define CAN_IT_FMP1 ((u32)0x00000010) /* FIFO 1 message pending */
#define CAN_IT_FF1 ((u32)0x00000020) /* FIFO 1 full */
#define CAN_IT_FOV1 ((u32)0x00000040) /* FIFO 1 overrun */
#define CAN_IT_EWG ((u32)0x00000100) /* Error warning */
#define CAN_IT_EPV ((u32)0x00000200) /* Error passive */
#define CAN_IT_BOF ((u32)0x00000400) /* Bus-off */
#define CAN_IT_LEC ((u32)0x00000800) /* Last error code */
#define CAN_IT_ERR ((u32)0x00008000) /* Error */
#define CAN_IT_WKU ((u32)0x00010000) /* Wake-up */
#define CAN_IT_SLK ((u32)0x00020000) /* Sleep */
/**
* @}
*/
/** @defgroup CAN_interrupts
* @{
*/
#define CAN_IT_RQCP0 ((uint32_t)0x00000005) /*!< Request completed mailbox 0 */
#define CAN_IT_RQCP1 ((uint32_t)0x00000006) /*!< Request completed mailbox 1 */
#define CAN_IT_RQCP2 ((uint32_t)0x00000007) /*!< Request completed mailbox 2 */
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty */
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending */
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full */
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun */
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending */
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full */
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun */
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning */
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive */
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off */
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code */
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error */
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up */
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep */
#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
@ -237,27 +475,61 @@ typedef struct
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported function protypes ----------------------------------------------- */
void CAN_DeInit(void);
u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct);
/**
* @}
*/
/** @defgroup CAN_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CAN_Exported_Functions
* @{
*/
void CAN_DeInit(CAN_TypeDef* CANx);
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState);
u8 CAN_Transmit(CanTxMsg* TxMessage);
u8 CAN_TransmitStatus(u8 TransmitMailbox);
void CAN_CancelTransmit(u8 Mailbox);
void CAN_FIFORelease(u8 FIFONumber);
u8 CAN_MessagePending(u8 FIFONumber);
void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage);
u8 CAN_Sleep(void);
u8 CAN_WakeUp(void);
FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG);
void CAN_ClearFlag(u32 CAN_FLAG);
ITStatus CAN_GetITStatus(u32 CAN_IT);
void CAN_ClearITPendingBit(u32 CAN_IT);
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_CAN_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

110
src/platform/stm32/FWLib/library/inc/stm32f10x_crc.h
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@ -1,37 +1,93 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_crc.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* CRC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_crc.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the CRC firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CRC_H
#define __STM32F10x_CRC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Exported_Constants
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Exported_Functions
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void CRC_ResetDR(void);
u32 CRC_CalcCRC(u32 Data);
u32 CRC_CalcBlockCRC(u32 pBuffer[], u32 BufferLength);
u32 CRC_GetCRC(void);
void CRC_SetIDRegister(u8 IDValue);
u8 CRC_GetIDRegister(void);
uint32_t CRC_CalcCRC(uint32_t Data);
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
uint32_t CRC_GetCRC(void);
void CRC_SetIDRegister(uint8_t IDValue);
uint8_t CRC_GetIDRegister(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_CRC_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

293
src/platform/stm32/FWLib/library/inc/stm32f10x_dac.h
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@ -1,47 +1,93 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_dac.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* DAC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_dac.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DAC_H
#define __STM32F10x_DAC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/** @defgroup DAC_Exported_Types
* @{
*/
/**
* @brief DAC Init structure definition
*/
/* Exported types ------------------------------------------------------------*/
/* DAC Init structure definition */
typedef struct
{
u32 DAC_Trigger;
u32 DAC_WaveGeneration;
u32 DAC_LFSRUnmask_TriangleAmplitude;
u32 DAC_OutputBuffer;
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
are generated, or whether no wave is generated.
This parameter can be a value of @ref DAC_wave_generation */
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
the maximum amplitude triangle generation for the DAC channel.
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
}DAC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* DAC trigger selection */
#define DAC_Trigger_None ((u32)0x00000000)
#define DAC_Trigger_T6_TRGO ((u32)0x00000004)
#define DAC_Trigger_T8_TRGO ((u32)0x0000000C)
#define DAC_Trigger_T7_TRGO ((u32)0x00000014)
#define DAC_Trigger_T5_TRGO ((u32)0x0000001C)
#define DAC_Trigger_T2_TRGO ((u32)0x00000024)
#define DAC_Trigger_T4_TRGO ((u32)0x0000002C)
#define DAC_Trigger_Ext_IT9 ((u32)0x00000034)
#define DAC_Trigger_Software ((u32)0x0000003C)
/**
* @}
*/
/** @defgroup DAC_Exported_Constants
* @{
*/
/** @defgroup DAC_trigger_selection
* @{
*/
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
only in High-density devices*/
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
only in Connectivity line devices */
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
@ -53,41 +99,52 @@ typedef struct
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
((TRIGGER) == DAC_Trigger_Software))
/* DAC wave generation */
#define DAC_WaveGeneration_None ((u32)0x00000000)
#define DAC_WaveGeneration_Noise ((u32)0x00000040)
#define DAC_WaveGeneration_Triangle ((u32)0x00000080)
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
((WAVE) == DAC_WaveGeneration_Noise) || \
((WAVE) == DAC_WaveGeneration_Triangle))
/**
* @}
*/
/* DAC noise wave generation mask / triangle wave generation max amplitude */
#define DAC_LFSRUnmask_Bit0 ((u32)0x00000000)
#define DAC_LFSRUnmask_Bits1_0 ((u32)0x00000100)
#define DAC_LFSRUnmask_Bits2_0 ((u32)0x00000200)
#define DAC_LFSRUnmask_Bits3_0 ((u32)0x00000300)
#define DAC_LFSRUnmask_Bits4_0 ((u32)0x00000400)
#define DAC_LFSRUnmask_Bits5_0 ((u32)0x00000500)
#define DAC_LFSRUnmask_Bits6_0 ((u32)0x00000600)
#define DAC_LFSRUnmask_Bits7_0 ((u32)0x00000700)
#define DAC_LFSRUnmask_Bits8_0 ((u32)0x00000800)
#define DAC_LFSRUnmask_Bits9_0 ((u32)0x00000900)
#define DAC_LFSRUnmask_Bits10_0 ((u32)0x00000A00)
#define DAC_LFSRUnmask_Bits11_0 ((u32)0x00000B00)
/** @defgroup DAC_lfsrunmask_triangleamplitude
* @{
*/
#define DAC_TriangleAmplitude_1 ((u32)0x00000000)
#define DAC_TriangleAmplitude_3 ((u32)0x00000100)
#define DAC_TriangleAmplitude_7 ((u32)0x00000200)
#define DAC_TriangleAmplitude_15 ((u32)0x00000300)
#define DAC_TriangleAmplitude_31 ((u32)0x00000400)
#define DAC_TriangleAmplitude_63 ((u32)0x00000500)
#define DAC_TriangleAmplitude_127 ((u32)0x00000600)
#define DAC_TriangleAmplitude_255 ((u32)0x00000700)
#define DAC_TriangleAmplitude_511 ((u32)0x00000800)
#define DAC_TriangleAmplitude_1023 ((u32)0x00000900)
#define DAC_TriangleAmplitude_2047 ((u32)0x00000A00)
#define DAC_TriangleAmplitude_4095 ((u32)0x00000B00)
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
@ -113,55 +170,113 @@ typedef struct
((VALUE) == DAC_TriangleAmplitude_1023) || \
((VALUE) == DAC_TriangleAmplitude_2047) || \
((VALUE) == DAC_TriangleAmplitude_4095))
/**
* @}
*/
/* DAC output buffer */
#define DAC_OutputBuffer_Enable ((u32)0x00000000)
#define DAC_OutputBuffer_Disable ((u32)0x00000002)
/** @defgroup DAC_output_buffer
* @{
*/
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
((STATE) == DAC_OutputBuffer_Disable))
/**
* @}
*/
/* DAC Channel selection */
#define DAC_Channel_1 ((u32)0x00000000)
#define DAC_Channel_2 ((u32)0x00000010)
/** @defgroup DAC_Channel_selection
* @{
*/
#define DAC_Channel_1 ((uint32_t)0x00000000)
#define DAC_Channel_2 ((uint32_t)0x00000010)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
((CHANNEL) == DAC_Channel_2))
/**
* @}
*/
/* DAC data alignement */
#define DAC_Align_12b_R ((u32)0x00000000)
#define DAC_Align_12b_L ((u32)0x00000004)
#define DAC_Align_8b_R ((u32)0x00000008)
/** @defgroup DAC_data_alignement
* @{
*/
#define DAC_Align_12b_R ((uint32_t)0x00000000)
#define DAC_Align_12b_L ((uint32_t)0x00000004)
#define DAC_Align_8b_R ((uint32_t)0x00000008)
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
((ALIGN) == DAC_Align_12b_L) || \
((ALIGN) == DAC_Align_8b_R))
/**
* @}
*/
/* DAC wave generation */
#define DAC_Wave_Noise ((u32)0x00000040)
#define DAC_Wave_Triangle ((u32)0x00000080)
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_Wave_Noise ((uint32_t)0x00000040)
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
((WAVE) == DAC_Wave_Triangle))
/**
* @}
*/
/** @defgroup DAC_data
* @{
*/
/* DAC data ------------------------------------------------------------------*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
/**
* @}
*/
/** @defgroup DAC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Exported_Functions
* @{
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
void DAC_DeInit(void);
void DAC_Init(u32 DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
void DAC_Cmd(u32 DAC_Channel, FunctionalState NewState);
void DAC_DMACmd(u32 DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(u32 DAC_Channel, FunctionalState NewState);
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
void DAC_WaveGenerationCmd(u32 DAC_Channel, u32 DAC_Wave, FunctionalState NewState);
void DAC_SetChannel1Data(u32 DAC_Align, u16 Data);
void DAC_SetChannel2Data(u32 DAC_Align, u16 Data);
void DAC_SetDualChannelData(u32 DAC_Align, u16 Data2, u16 Data1);
u16 DAC_GetDataOutputValue(u32 DAC_Channel);
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F10x_DAC_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

138
src/platform/stm32/FWLib/library/inc/stm32f10x_dbgmcu.h
View File

@ -1,55 +1,109 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_dbgmcu.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* DBGMCU firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_dbgmcu.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the DBGMCU
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DBGMCU_H
#define __STM32F10x_DBGMCU_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#include "stm32f10x.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
#define DBGMCU_SLEEP ((u32)0x00000001)
#define DBGMCU_STOP ((u32)0x00000002)
#define DBGMCU_STANDBY ((u32)0x00000004)
#define DBGMCU_IWDG_STOP ((u32)0x00000100)
#define DBGMCU_WWDG_STOP ((u32)0x00000200)
#define DBGMCU_TIM1_STOP ((u32)0x00000400)
#define DBGMCU_TIM2_STOP ((u32)0x00000800)
#define DBGMCU_TIM3_STOP ((u32)0x00001000)
#define DBGMCU_TIM4_STOP ((u32)0x00002000)
#define DBGMCU_CAN_STOP ((u32)0x00004000)
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((u32)0x00008000)
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((u32)0x00010000)
#define DBGMCU_TIM5_STOP ((u32)0x00020000)
#define DBGMCU_TIM6_STOP ((u32)0x00040000)
#define DBGMCU_TIM7_STOP ((u32)0x00080000)
#define DBGMCU_TIM8_STOP ((u32)0x00100000)
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFE000F8) == 0x00) && ((PERIPH) != 0x00))
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
u32 DBGMCU_GetREVID(void);
u32 DBGMCU_GetDEVID(void);
void DBGMCU_Config(u32 DBGMCU_Periph, FunctionalState NewState);
/** @addtogroup DBGMCU
* @{
*/
/** @defgroup DBGMCU_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Exported_Constants
* @{
*/
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
#define DBGMCU_STOP ((uint32_t)0x00000002)
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFC000F8) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup DBGMCU_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Exported_Functions
* @{
*/
uint32_t DBGMCU_GetREVID(void);
uint32_t DBGMCU_GetDEVID(void);
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_DBGMCU_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

512
src/platform/stm32/FWLib/library/inc/stm32f10x_dma.h
View File

@ -1,178 +1,273 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_dma.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* DMA firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_dma.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DMA_H
#define __STM32F10x_DMA_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/** @defgroup DMA_Exported_Types
* @{
*/
/**
* @brief DMA Init structure definition
*/
/* Exported types ------------------------------------------------------------*/
/* DMA Init structure definition */
typedef struct
{
u32 DMA_PeripheralBaseAddr;
u32 DMA_MemoryBaseAddr;
u32 DMA_DIR;
u32 DMA_BufferSize;
u32 DMA_PeripheralInc;
u32 DMA_MemoryInc;
u32 DMA_PeripheralDataSize;
u32 DMA_MemoryDataSize;
u32 DMA_Mode;
u32 DMA_Priority;
u32 DMA_M2M;
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
This parameter can be a value of @ref DMA_data_transfer_direction */
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
The data unit is equal to the configuration set in DMA_PeripheralDataSize
or DMA_MemoryDataSize members depending in the transfer direction. */
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
This parameter can be a value of @ref DMA_memory_incremented_mode */
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_peripheral_data_size */
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_memory_data_size */
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_circular_normal_mode.
@note: The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_priority_level */
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
This parameter can be a value of @ref DMA_memory_to_memory */
}DMA_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
#define IS_DMA_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == DMA1_Channel1_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel2_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel3_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel4_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel5_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel6_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel7_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel1_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel2_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel3_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel4_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel5_BASE))
/**
* @}
*/
/* DMA data transfer direction -----------------------------------------------*/
#define DMA_DIR_PeripheralDST ((u32)0x00000010)
#define DMA_DIR_PeripheralSRC ((u32)0x00000000)
/** @defgroup DMA_Exported_Constants
* @{
*/
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
((PERIPH) == DMA1_Channel2) || \
((PERIPH) == DMA1_Channel3) || \
((PERIPH) == DMA1_Channel4) || \
((PERIPH) == DMA1_Channel5) || \
((PERIPH) == DMA1_Channel6) || \
((PERIPH) == DMA1_Channel7) || \
((PERIPH) == DMA2_Channel1) || \
((PERIPH) == DMA2_Channel2) || \
((PERIPH) == DMA2_Channel3) || \
((PERIPH) == DMA2_Channel4) || \
((PERIPH) == DMA2_Channel5))
/** @defgroup DMA_data_transfer_direction
* @{
*/
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
((DIR) == DMA_DIR_PeripheralSRC))
/**
* @}
*/
/* DMA peripheral incremented mode -------------------------------------------*/
#define DMA_PeripheralInc_Enable ((u32)0x00000040)
#define DMA_PeripheralInc_Disable ((u32)0x00000000)
/** @defgroup DMA_peripheral_incremented_mode
* @{
*/
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
((STATE) == DMA_PeripheralInc_Disable))
/**
* @}
*/
/* DMA memory incremented mode -----------------------------------------------*/
#define DMA_MemoryInc_Enable ((u32)0x00000080)
#define DMA_MemoryInc_Disable ((u32)0x00000000)
/** @defgroup DMA_memory_incremented_mode
* @{
*/
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
((STATE) == DMA_MemoryInc_Disable))
/**
* @}
*/
/* DMA peripheral data size --------------------------------------------------*/
#define DMA_PeripheralDataSize_Byte ((u32)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100)
#define DMA_PeripheralDataSize_Word ((u32)0x00000200)
/** @defgroup DMA_peripheral_data_size
* @{
*/
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
((SIZE) == DMA_PeripheralDataSize_Word))
/**
* @}
*/
/* DMA memory data size ------------------------------------------------------*/
#define DMA_MemoryDataSize_Byte ((u32)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400)
#define DMA_MemoryDataSize_Word ((u32)0x00000800)
/** @defgroup DMA_memory_data_size
* @{
*/
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
((SIZE) == DMA_MemoryDataSize_Word))
/**
* @}
*/
/* DMA circular/normal mode --------------------------------------------------*/
#define DMA_Mode_Circular ((u32)0x00000020)
#define DMA_Mode_Normal ((u32)0x00000000)
/** @defgroup DMA_circular_normal_mode
* @{
*/
#define DMA_Mode_Circular ((uint32_t)0x00000020)
#define DMA_Mode_Normal ((uint32_t)0x00000000)
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
/**
* @}
*/
/* DMA priority level --------------------------------------------------------*/
#define DMA_Priority_VeryHigh ((u32)0x00003000)
#define DMA_Priority_High ((u32)0x00002000)
#define DMA_Priority_Medium ((u32)0x00001000)
#define DMA_Priority_Low ((u32)0x00000000)
/** @defgroup DMA_priority_level
* @{
*/
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define DMA_Priority_High ((uint32_t)0x00002000)
#define DMA_Priority_Medium ((uint32_t)0x00001000)
#define DMA_Priority_Low ((uint32_t)0x00000000)
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
((PRIORITY) == DMA_Priority_High) || \
((PRIORITY) == DMA_Priority_Medium) || \
((PRIORITY) == DMA_Priority_Low))
/**
* @}
*/
/* DMA memory to memory ------------------------------------------------------*/
#define DMA_M2M_Enable ((u32)0x00004000)
#define DMA_M2M_Disable ((u32)0x00000000)
/** @defgroup DMA_memory_to_memory
* @{
*/
#define DMA_M2M_Enable ((uint32_t)0x00004000)
#define DMA_M2M_Disable ((uint32_t)0x00000000)
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
/* DMA interrupts definition -------------------------------------------------*/
#define DMA_IT_TC ((u32)0x00000002)
#define DMA_IT_HT ((u32)0x00000004)
#define DMA_IT_TE ((u32)0x00000008)
/**
* @}
*/
/** @defgroup DMA_interrupts_definition
* @{
*/
#define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004)
#define DMA_IT_TE ((uint32_t)0x00000008)
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
/* For DMA1 */
#define DMA1_IT_GL1 ((u32)0x00000001)
#define DMA1_IT_TC1 ((u32)0x00000002)
#define DMA1_IT_HT1 ((u32)0x00000004)
#define DMA1_IT_TE1 ((u32)0x00000008)
#define DMA1_IT_GL2 ((u32)0x00000010)
#define DMA1_IT_TC2 ((u32)0x00000020)
#define DMA1_IT_HT2 ((u32)0x00000040)
#define DMA1_IT_TE2 ((u32)0x00000080)
#define DMA1_IT_GL3 ((u32)0x00000100)
#define DMA1_IT_TC3 ((u32)0x00000200)
#define DMA1_IT_HT3 ((u32)0x00000400)
#define DMA1_IT_TE3 ((u32)0x00000800)
#define DMA1_IT_GL4 ((u32)0x00001000)
#define DMA1_IT_TC4 ((u32)0x00002000)
#define DMA1_IT_HT4 ((u32)0x00004000)
#define DMA1_IT_TE4 ((u32)0x00008000)
#define DMA1_IT_GL5 ((u32)0x00010000)
#define DMA1_IT_TC5 ((u32)0x00020000)
#define DMA1_IT_HT5 ((u32)0x00040000)
#define DMA1_IT_TE5 ((u32)0x00080000)
#define DMA1_IT_GL6 ((u32)0x00100000)
#define DMA1_IT_TC6 ((u32)0x00200000)
#define DMA1_IT_HT6 ((u32)0x00400000)
#define DMA1_IT_TE6 ((u32)0x00800000)
#define DMA1_IT_GL7 ((u32)0x01000000)
#define DMA1_IT_TC7 ((u32)0x02000000)
#define DMA1_IT_HT7 ((u32)0x04000000)
#define DMA1_IT_TE7 ((u32)0x08000000)
/* For DMA2 */
#define DMA2_IT_GL1 ((u32)0x10000001)
#define DMA2_IT_TC1 ((u32)0x10000002)
#define DMA2_IT_HT1 ((u32)0x10000004)
#define DMA2_IT_TE1 ((u32)0x10000008)
#define DMA2_IT_GL2 ((u32)0x10000010)
#define DMA2_IT_TC2 ((u32)0x10000020)
#define DMA2_IT_HT2 ((u32)0x10000040)
#define DMA2_IT_TE2 ((u32)0x10000080)
#define DMA2_IT_GL3 ((u32)0x10000100)
#define DMA2_IT_TC3 ((u32)0x10000200)
#define DMA2_IT_HT3 ((u32)0x10000400)
#define DMA2_IT_TE3 ((u32)0x10000800)
#define DMA2_IT_GL4 ((u32)0x10001000)
#define DMA2_IT_TC4 ((u32)0x10002000)
#define DMA2_IT_HT4 ((u32)0x10004000)
#define DMA2_IT_TE4 ((u32)0x10008000)
#define DMA2_IT_GL5 ((u32)0x10010000)
#define DMA2_IT_TC5 ((u32)0x10020000)
#define DMA2_IT_HT5 ((u32)0x10040000)
#define DMA2_IT_TE5 ((u32)0x10080000)
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
@ -198,59 +293,65 @@ typedef struct
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
/* DMA flags definition ------------------------------------------------------*/
/* For DMA1 */
#define DMA1_FLAG_GL1 ((u32)0x00000001)
#define DMA1_FLAG_TC1 ((u32)0x00000002)
#define DMA1_FLAG_HT1 ((u32)0x00000004)
#define DMA1_FLAG_TE1 ((u32)0x00000008)
#define DMA1_FLAG_GL2 ((u32)0x00000010)
#define DMA1_FLAG_TC2 ((u32)0x00000020)
#define DMA1_FLAG_HT2 ((u32)0x00000040)
#define DMA1_FLAG_TE2 ((u32)0x00000080)
#define DMA1_FLAG_GL3 ((u32)0x00000100)
#define DMA1_FLAG_TC3 ((u32)0x00000200)
#define DMA1_FLAG_HT3 ((u32)0x00000400)
#define DMA1_FLAG_TE3 ((u32)0x00000800)
#define DMA1_FLAG_GL4 ((u32)0x00001000)
#define DMA1_FLAG_TC4 ((u32)0x00002000)
#define DMA1_FLAG_HT4 ((u32)0x00004000)
#define DMA1_FLAG_TE4 ((u32)0x00008000)
#define DMA1_FLAG_GL5 ((u32)0x00010000)
#define DMA1_FLAG_TC5 ((u32)0x00020000)
#define DMA1_FLAG_HT5 ((u32)0x00040000)
#define DMA1_FLAG_TE5 ((u32)0x00080000)
#define DMA1_FLAG_GL6 ((u32)0x00100000)
#define DMA1_FLAG_TC6 ((u32)0x00200000)
#define DMA1_FLAG_HT6 ((u32)0x00400000)
#define DMA1_FLAG_TE6 ((u32)0x00800000)
#define DMA1_FLAG_GL7 ((u32)0x01000000)
#define DMA1_FLAG_TC7 ((u32)0x02000000)
#define DMA1_FLAG_HT7 ((u32)0x04000000)
#define DMA1_FLAG_TE7 ((u32)0x08000000)
/* For DMA2 */
#define DMA2_FLAG_GL1 ((u32)0x10000001)
#define DMA2_FLAG_TC1 ((u32)0x10000002)
#define DMA2_FLAG_HT1 ((u32)0x10000004)
#define DMA2_FLAG_TE1 ((u32)0x10000008)
#define DMA2_FLAG_GL2 ((u32)0x10000010)
#define DMA2_FLAG_TC2 ((u32)0x10000020)
#define DMA2_FLAG_HT2 ((u32)0x10000040)
#define DMA2_FLAG_TE2 ((u32)0x10000080)
#define DMA2_FLAG_GL3 ((u32)0x10000100)
#define DMA2_FLAG_TC3 ((u32)0x10000200)
#define DMA2_FLAG_HT3 ((u32)0x10000400)
#define DMA2_FLAG_TE3 ((u32)0x10000800)
#define DMA2_FLAG_GL4 ((u32)0x10001000)
#define DMA2_FLAG_TC4 ((u32)0x10002000)
#define DMA2_FLAG_HT4 ((u32)0x10004000)
#define DMA2_FLAG_TE4 ((u32)0x10008000)
#define DMA2_FLAG_GL5 ((u32)0x10010000)
#define DMA2_FLAG_TC5 ((u32)0x10020000)
#define DMA2_FLAG_HT5 ((u32)0x10040000)
#define DMA2_FLAG_TE5 ((u32)0x10080000)
/**
* @}
*/
/** @defgroup DMA_flags_definition
* @{
*/
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
@ -275,23 +376,62 @@ typedef struct
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
/**
* @}
*/
/** @defgroup DMA_Buffer_Size
* @{
*/
/* DMA Buffer Size -----------------------------------------------------------*/
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* @}
*/
/**
* @}
*/
/** @defgroup DMA_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Exported_Functions
* @{
*/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState);
u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);
void DMA_ClearFlag(u32 DMA_FLAG);
ITStatus DMA_GetITStatus(u32 DMA_IT);
void DMA_ClearITPendingBit(u32 DMA_IT);
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
void DMA_ClearFlag(uint32_t DMA_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMA_IT);
void DMA_ClearITPendingBit(uint32_t DMA_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F10x_DMA_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

200
src/platform/stm32/FWLib/library/inc/stm32f10x_exti.h
View File

@ -1,28 +1,51 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_exti.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* EXTI firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_exti.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the EXTI firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_EXTI_H
#define __STM32F10x_EXTI_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** @defgroup EXTI_Exported_Types
* @{
*/
/**
* @brief EXTI mode enumeration
*/
/* Exported types ------------------------------------------------------------*/
/* EXTI mode enumeration -----------------------------------------------------*/
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
@ -30,8 +53,11 @@ typedef enum
}EXTIMode_TypeDef;
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
/* EXTI Trigger enumeration --------------------------------------------------*/
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Rising = 0x08,
@ -42,43 +68,60 @@ typedef enum
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
((TRIGGER) == EXTI_Trigger_Falling) || \
((TRIGGER) == EXTI_Trigger_Rising_Falling))
/**
* @brief EXTI Init Structure definition
*/
/* EXTI Init Structure definition --------------------------------------------*/
typedef struct
{
u32 EXTI_Line;
EXTIMode_TypeDef EXTI_Mode;
EXTITrigger_TypeDef EXTI_Trigger;
FunctionalState EXTI_LineCmd;
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
}EXTI_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* EXTI Lines ----------------------------------------------------------------*/
#define EXTI_Line0 ((u32)0x00001) /* External interrupt line 0 */
#define EXTI_Line1 ((u32)0x00002) /* External interrupt line 1 */
#define EXTI_Line2 ((u32)0x00004) /* External interrupt line 2 */
#define EXTI_Line3 ((u32)0x00008) /* External interrupt line 3 */
#define EXTI_Line4 ((u32)0x00010) /* External interrupt line 4 */
#define EXTI_Line5 ((u32)0x00020) /* External interrupt line 5 */
#define EXTI_Line6 ((u32)0x00040) /* External interrupt line 6 */
#define EXTI_Line7 ((u32)0x00080) /* External interrupt line 7 */
#define EXTI_Line8 ((u32)0x00100) /* External interrupt line 8 */
#define EXTI_Line9 ((u32)0x00200) /* External interrupt line 9 */
#define EXTI_Line10 ((u32)0x00400) /* External interrupt line 10 */
#define EXTI_Line11 ((u32)0x00800) /* External interrupt line 11 */
#define EXTI_Line12 ((u32)0x01000) /* External interrupt line 12 */
#define EXTI_Line13 ((u32)0x02000) /* External interrupt line 13 */
#define EXTI_Line14 ((u32)0x04000) /* External interrupt line 14 */
#define EXTI_Line15 ((u32)0x08000) /* External interrupt line 15 */
#define EXTI_Line16 ((u32)0x10000) /* External interrupt line 16
Connected to the PVD Output */
#define EXTI_Line17 ((u32)0x20000) /* External interrupt line 17
Connected to the RTC Alarm event */
#define EXTI_Line18 ((u32)0x40000) /* External interrupt line 18
Connected to the USB Wakeup from
suspend event */
/**
* @}
*/
#define IS_EXTI_LINE(LINE) ((((LINE) & (u32)0xFFF80000) == 0x00) && ((LINE) != (u16)0x00))
/** @defgroup EXTI_Exported_Constants
* @{
*/
/** @defgroup EXTI_Lines
* @{
*/
#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
Wakeup from suspend event */
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
@ -89,19 +132,52 @@ typedef struct
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
((LINE) == EXTI_Line18))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
/**
* @}
*/
/**
* @}
*/
/** @defgroup EXTI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions
* @{
*/
void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_GenerateSWInterrupt(u32 EXTI_Line);
FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line);
void EXTI_ClearFlag(u32 EXTI_Line);
ITStatus EXTI_GetITStatus(u32 EXTI_Line);
void EXTI_ClearITPendingBit(u32 EXTI_Line);
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
void EXTI_ClearFlag(uint32_t EXTI_Line);
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_EXTI_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

430
src/platform/stm32/FWLib/library/inc/stm32f10x_flash.h
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@ -1,29 +1,51 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_flash.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* FLASH firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_flash.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FLASH_H
#define __STM32F10x_FLASH_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @defgroup FLASH_Exported_Types
* @{
*/
/**
* @brief FLASH Status
*/
/* Exported types ------------------------------------------------------------*/
#ifdef _FLASH_PROG
/* FLASH Status */
typedef enum
{
FLASH_BUSY = 1,
@ -32,177 +54,293 @@ typedef enum
FLASH_COMPLETE,
FLASH_TIMEOUT
}FLASH_Status;
#endif
/* Flash Latency -------------------------------------------------------------*/
#define FLASH_Latency_0 ((u32)0x00000000) /* FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((u32)0x00000001) /* FLASH One Latency cycle */
#define FLASH_Latency_2 ((u32)0x00000002) /* FLASH Two Latency cycles */
/**
* @}
*/
/** @defgroup FLASH_Exported_Constants
* @{
*/
/** @defgroup Flash_Latency
* @{
*/
#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \
((LATENCY) == FLASH_Latency_2))
/**
* @}
*/
/* Half Cycle Enable/Disable -------------------------------------------------*/
#define FLASH_HalfCycleAccess_Enable ((u32)0x00000008) /* FLASH Half Cycle Enable */
#define FLASH_HalfCycleAccess_Disable ((u32)0x00000000) /* FLASH Half Cycle Disable */
/** @defgroup Half_Cycle_Enable_Disable
* @{
*/
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
((STATE) == FLASH_HalfCycleAccess_Disable))
/**
* @}
*/
/** @defgroup Prefetch_Buffer_Enable_Disable
* @{
*/
/* Prefetch Buffer Enable/Disable --------------------------------------------*/
#define FLASH_PrefetchBuffer_Enable ((u32)0x00000010) /* FLASH Prefetch Buffer Enable */
#define FLASH_PrefetchBuffer_Disable ((u32)0x00000000) /* FLASH Prefetch Buffer Disable */
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
((STATE) == FLASH_PrefetchBuffer_Disable))
/**
* @}
*/
#ifdef _FLASH_PROG
/* Option Bytes Write Protection ---------------------------------------------*/
/* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density
ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */
#define FLASH_WRProt_Pages0to3 ((u32)0x00000001) /* Write protection of page 0 to 3 */
#define FLASH_WRProt_Pages4to7 ((u32)0x00000002) /* Write protection of page 4 to 7 */
#define FLASH_WRProt_Pages8to11 ((u32)0x00000004) /* Write protection of page 8 to 11 */
#define FLASH_WRProt_Pages12to15 ((u32)0x00000008) /* Write protection of page 12 to 15 */
#define FLASH_WRProt_Pages16to19 ((u32)0x00000010) /* Write protection of page 16 to 19 */
#define FLASH_WRProt_Pages20to23 ((u32)0x00000020) /* Write protection of page 20 to 23 */
#define FLASH_WRProt_Pages24to27 ((u32)0x00000040) /* Write protection of page 24 to 27 */
#define FLASH_WRProt_Pages28to31 ((u32)0x00000080) /* Write protection of page 28 to 31 */
#define FLASH_WRProt_Pages32to35 ((u32)0x00000100) /* Write protection of page 32 to 35 */
#define FLASH_WRProt_Pages36to39 ((u32)0x00000200) /* Write protection of page 36 to 39 */
#define FLASH_WRProt_Pages40to43 ((u32)0x00000400) /* Write protection of page 40 to 43 */
#define FLASH_WRProt_Pages44to47 ((u32)0x00000800) /* Write protection of page 44 to 47 */
#define FLASH_WRProt_Pages48to51 ((u32)0x00001000) /* Write protection of page 48 to 51 */
#define FLASH_WRProt_Pages52to55 ((u32)0x00002000) /* Write protection of page 52 to 55 */
#define FLASH_WRProt_Pages56to59 ((u32)0x00004000) /* Write protection of page 56 to 59 */
#define FLASH_WRProt_Pages60to63 ((u32)0x00008000) /* Write protection of page 60 to 63 */
#define FLASH_WRProt_Pages64to67 ((u32)0x00010000) /* Write protection of page 64 to 67 */
#define FLASH_WRProt_Pages68to71 ((u32)0x00020000) /* Write protection of page 68 to 71 */
#define FLASH_WRProt_Pages72to75 ((u32)0x00040000) /* Write protection of page 72 to 75 */
#define FLASH_WRProt_Pages76to79 ((u32)0x00080000) /* Write protection of page 76 to 79 */
#define FLASH_WRProt_Pages80to83 ((u32)0x00100000) /* Write protection of page 80 to 83 */
#define FLASH_WRProt_Pages84to87 ((u32)0x00200000) /* Write protection of page 84 to 87 */
#define FLASH_WRProt_Pages88to91 ((u32)0x00400000) /* Write protection of page 88 to 91 */
#define FLASH_WRProt_Pages92to95 ((u32)0x00800000) /* Write protection of page 92 to 95 */
#define FLASH_WRProt_Pages96to99 ((u32)0x01000000) /* Write protection of page 96 to 99 */
#define FLASH_WRProt_Pages100to103 ((u32)0x02000000) /* Write protection of page 100 to 103 */
#define FLASH_WRProt_Pages104to107 ((u32)0x04000000) /* Write protection of page 104 to 107 */
#define FLASH_WRProt_Pages108to111 ((u32)0x08000000) /* Write protection of page 108 to 111 */
#define FLASH_WRProt_Pages112to115 ((u32)0x10000000) /* Write protection of page 112 to 115 */
#define FLASH_WRProt_Pages116to119 ((u32)0x20000000) /* Write protection of page 115 to 119 */
#define FLASH_WRProt_Pages120to123 ((u32)0x40000000) /* Write protection of page 120 to 123 */
#define FLASH_WRProt_Pages124to127 ((u32)0x80000000) /* Write protection of page 124 to 127 */
/* Values to be used with STM32F10Xxx High-density devices: FLASH memory density
ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
#define FLASH_WRProt_Pages0to1 ((u32)0x00000001) /* Write protection of page 0 to 1 */
#define FLASH_WRProt_Pages2to3 ((u32)0x00000002) /* Write protection of page 2 to 3 */
#define FLASH_WRProt_Pages4to5 ((u32)0x00000004) /* Write protection of page 4 to 5 */
#define FLASH_WRProt_Pages6to7 ((u32)0x00000008) /* Write protection of page 6 to 7 */
#define FLASH_WRProt_Pages8to9 ((u32)0x00000010) /* Write protection of page 8 to 9 */
#define FLASH_WRProt_Pages10to11 ((u32)0x00000020) /* Write protection of page 10 to 11 */
#define FLASH_WRProt_Pages12to13 ((u32)0x00000040) /* Write protection of page 12 to 13 */
#define FLASH_WRProt_Pages14to15 ((u32)0x00000080) /* Write protection of page 14 to 15 */
#define FLASH_WRProt_Pages16to17 ((u32)0x00000100) /* Write protection of page 16 to 17 */
#define FLASH_WRProt_Pages18to19 ((u32)0x00000200) /* Write protection of page 18 to 19 */
#define FLASH_WRProt_Pages20to21 ((u32)0x00000400) /* Write protection of page 20 to 21 */
#define FLASH_WRProt_Pages22to23 ((u32)0x00000800) /* Write protection of page 22 to 23 */
#define FLASH_WRProt_Pages24to25 ((u32)0x00001000) /* Write protection of page 24 to 25 */
#define FLASH_WRProt_Pages26to27 ((u32)0x00002000) /* Write protection of page 26 to 27 */
#define FLASH_WRProt_Pages28to29 ((u32)0x00004000) /* Write protection of page 28 to 29 */
#define FLASH_WRProt_Pages30to31 ((u32)0x00008000) /* Write protection of page 30 to 31 */
#define FLASH_WRProt_Pages32to33 ((u32)0x00010000) /* Write protection of page 32 to 33 */
#define FLASH_WRProt_Pages34to35 ((u32)0x00020000) /* Write protection of page 34 to 35 */
#define FLASH_WRProt_Pages36to37 ((u32)0x00040000) /* Write protection of page 36 to 37 */
#define FLASH_WRProt_Pages38to39 ((u32)0x00080000) /* Write protection of page 38 to 39 */
#define FLASH_WRProt_Pages40to41 ((u32)0x00100000) /* Write protection of page 40 to 41 */
#define FLASH_WRProt_Pages42to43 ((u32)0x00200000) /* Write protection of page 42 to 43 */
#define FLASH_WRProt_Pages44to45 ((u32)0x00400000) /* Write protection of page 44 to 45 */
#define FLASH_WRProt_Pages46to47 ((u32)0x00800000) /* Write protection of page 46 to 47 */
#define FLASH_WRProt_Pages48to49 ((u32)0x01000000) /* Write protection of page 48 to 49 */
#define FLASH_WRProt_Pages50to51 ((u32)0x02000000) /* Write protection of page 50 to 51 */
#define FLASH_WRProt_Pages52to53 ((u32)0x04000000) /* Write protection of page 52 to 53 */
#define FLASH_WRProt_Pages54to55 ((u32)0x08000000) /* Write protection of page 54 to 55 */
#define FLASH_WRProt_Pages56to57 ((u32)0x10000000) /* Write protection of page 56 to 57 */
#define FLASH_WRProt_Pages58to59 ((u32)0x20000000) /* Write protection of page 58 to 59 */
#define FLASH_WRProt_Pages60to61 ((u32)0x40000000) /* Write protection of page 60 to 61 */
#define FLASH_WRProt_Pages62to255 ((u32)0x80000000) /* Write protection of page 62 to 255 */
#define FLASH_WRProt_AllPages ((u32)0xFFFFFFFF) /* Write protection of all Pages */
/** @defgroup Option_Bytes_Write_Protection
* @{
*/
/* Values to be used with STM32 Low and Medium density devices */
#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
/* Values to be used with STM32 Medium-density devices */
#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 0 to 1 */
#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 2 to 3 */
#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 4 to 5 */
#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 6 to 7 */
#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 8 to 9 */
#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 10 to 11 */
#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 12 to 13 */
#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 14 to 15 */
#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 16 to 17 */
#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 18 to 19 */
#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 20 to 21 */
#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 22 to 23 */
#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 24 to 25 */
#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 26 to 27 */
#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 28 to 29 */
#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 30 to 31 */
#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 32 to 33 */
#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 34 to 35 */
#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 36 to 37 */
#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 38 to 39 */
#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 40 to 41 */
#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 42 to 43 */
#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 44 to 45 */
#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 46 to 47 */
#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 48 to 49 */
#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 50 to 51 */
#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 52 to 53 */
#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 54 to 55 */
#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 56 to 57 */
#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 58 to 59 */
#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 Medium-density and Connectivity line devices:
Write protection of page 60 to 61 */
#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
/* Option Bytes IWatchdog ----------------------------------------------------*/
#define OB_IWDG_SW ((u16)0x0001) /* Software IWDG selected */
#define OB_IWDG_HW ((u16)0x0000) /* Hardware IWDG selected */
/**
* @}
*/
/** @defgroup Option_Bytes_IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
/* Option Bytes nRST_STOP ----------------------------------------------------*/
#define OB_STOP_NoRST ((u16)0x0002) /* No reset generated when entering in STOP */
#define OB_STOP_RST ((u16)0x0000) /* Reset generated when entering in STOP */
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STOP
* @{
*/
#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
/* Option Bytes nRST_STDBY ---------------------------------------------------*/
#define OB_STDBY_NoRST ((u16)0x0004) /* No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((u16)0x0000) /* Reset generated when entering in STANDBY */
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STDBY
* @{
*/
#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
/* FLASH Interrupts ----------------------------------------------------------*/
#define FLASH_IT_ERROR ((u32)0x00000400) /* FPEC error interrupt source */
#define FLASH_IT_EOP ((u32)0x00001000) /* End of FLASH Operation Interrupt source */
/**
* @}
*/
#define IS_FLASH_IT(IT) ((((IT) & (u32)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
/** @defgroup FLASH_Interrupts
* @{
*/
/* FLASH Flags ---------------------------------------------------------------*/
#define FLASH_FLAG_BSY ((u32)0x00000001) /* FLASH Busy flag */
#define FLASH_FLAG_EOP ((u32)0x00000020) /* FLASH End of Operation flag */
#define FLASH_FLAG_PGERR ((u32)0x00000004) /* FLASH Program error flag */
#define FLASH_FLAG_WRPRTERR ((u32)0x00000010) /* FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((u32)0x00000001) /* FLASH Option Byte error flag */
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
/**
* @}
*/
/** @defgroup FLASH_Flags
* @{
*/
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
((FLAG) == FLASH_FLAG_OPTERR))
#endif
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void FLASH_SetLatency(u32 FLASH_Latency);
void FLASH_HalfCycleAccessCmd(u32 FLASH_HalfCycleAccess);
void FLASH_PrefetchBufferCmd(u32 FLASH_PrefetchBuffer);
#ifdef _FLASH_PROG
/**
* @}
*/
/**
* @}
*/
/** @defgroup FLASH_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions
* @{
*/
void FLASH_SetLatency(uint32_t FLASH_Latency);
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(u32 Page_Address);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseOptionBytes(void);
FLASH_Status FLASH_ProgramWord(u32 Address, u32 Data);
FLASH_Status FLASH_ProgramHalfWord(u32 Address, u16 Data);
FLASH_Status FLASH_ProgramOptionByteData(u32 Address, u8 Data);
FLASH_Status FLASH_EnableWriteProtection(u32 FLASH_Pages);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
FLASH_Status FLASH_UserOptionByteConfig(u16 OB_IWDG, u16 OB_STOP, u16 OB_STDBY);
u32 FLASH_GetUserOptionByte(void);
u32 FLASH_GetWriteProtectionOptionByte(void);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
FlagStatus FLASH_GetPrefetchBufferStatus(void);
void FLASH_ITConfig(u16 FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(u16 FLASH_FLAG);
void FLASH_ClearFlag(u16 FLASH_FLAG);
void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG);
void FLASH_ClearFlag(uint16_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(u32 Timeout);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_FLASH_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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src/platform/stm32/FWLib/library/inc/stm32f10x_fsmc.h
View File

@ -1,116 +1,275 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_fsmc.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* FSMC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_fsmc.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the FSMC firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FSMC_H
#define __STM32F10x_FSMC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup FSMC
* @{
*/
/** @defgroup FSMC_Exported_Types
* @{
*/
/**
* @brief Timing parameters For NOR/SRAM Banks
*/
/* Exported types ------------------------------------------------------------*/
/* Timing parameters For NOR/SRAM Banks */
typedef struct
{
u32 FSMC_AddressSetupTime;
u32 FSMC_AddressHoldTime;
u32 FSMC_DataSetupTime;
u32 FSMC_BusTurnAroundDuration;
u32 FSMC_CLKDivision;
u32 FSMC_DataLatency;
u32 FSMC_AccessMode;
uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between 0 and 0xF.
@note: It is not used with synchronous NOR Flash memories. */
uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between 0 and 0xF.
@note: It is not used with synchronous NOR Flash memories.*/
uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between 0 and 0xFF.
@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between 0 and 0xF.
@note: It is only used for multiplexed NOR Flash memories. */
uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
This parameter can be a value between 1 and 0xF.
@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The value of this parameter depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don<EFBFBD>t care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between 0 and 0xF in NOR Flash memories
with synchronous burst mode enable */
uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FSMC_Access_Mode */
}FSMC_NORSRAMTimingInitTypeDef;
/* FSMC NOR/SRAM Init structure definition */
/**
* @brief FSMC NOR/SRAM Init structure definition
*/
typedef struct
{
u32 FSMC_Bank;
u32 FSMC_DataAddressMux;
u32 FSMC_MemoryType;
u32 FSMC_MemoryDataWidth;
u32 FSMC_BurstAccessMode;
u32 FSMC_WaitSignalPolarity;
u32 FSMC_WrapMode;
u32 FSMC_WaitSignalActive;
u32 FSMC_WriteOperation;
u32 FSMC_WaitSignal;
u32 FSMC_ExtendedMode;
u32 FSMC_WriteBurst;
/* Timing Parameters for write and read access if the ExtendedMode is not used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;
/* Timing Parameters for write access if the ExtendedMode is used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;
uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the databus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory bank.
This parameter can be a value of @ref FSMC_Memory_Type */
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FSMC_Data_Width */
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FSMC_Wrap_Mode */
uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FSMC_Wait_Timing */
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */
uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FSMC_Extended_Mode */
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FSMC_Write_Burst */
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
}FSMC_NORSRAMInitTypeDef;
/* Timing parameters For FSMC NAND and PCCARD Banks */
/**
* @brief Timing parameters For FSMC NAND and PCCARD Banks
*/
typedef struct
{
u32 FSMC_SetupTime;
u32 FSMC_WaitSetupTime;
u32 FSMC_HoldSetupTime;
u32 FSMC_HiZSetupTime;
uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between 0 and 0xFF.*/
uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between 0x00 and 0xFF */
uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command deassertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between 0x00 and 0xFF */
uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
databus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between 0x00 and 0xFF */
}FSMC_NAND_PCCARDTimingInitTypeDef;
/* FSMC NAND Init structure definition */
/**
* @brief FSMC NAND Init structure definition
*/
typedef struct
{
u32 FSMC_Bank;
u32 FSMC_Waitfeature;
u32 FSMC_MemoryDataWidth;
u32 FSMC_ECC;
u32 FSMC_ECCPageSize;
u32 FSMC_AddressLowMapping;
u32 FSMC_TCLRSetupTime;
u32 FSMC_TARSetupTime;
/* FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
/* FSMC Attribute Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
This parameter can be a value of @ref FSMC_NAND_Bank */
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FSMC_Data_Width */
uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FSMC_ECC */
uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FSMC_ECC_Page_Size */
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between 0 and 0xFF. */
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between 0x0 and 0xFF */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
}FSMC_NANDInitTypeDef;
/* FSMC PCCARD Init structure definition */
/**
* @brief FSMC PCCARD Init structure definition
*/
typedef struct
{
u32 FSMC_Waitfeature;
u32 FSMC_AddressLowMapping;
u32 FSMC_TCLRSetupTime;
u32 FSMC_TARSetupTime;
/* FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
/* FSMC Attribute Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
/* FSMC IO Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct;
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between 0 and 0xFF. */
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between 0x0 and 0xFF */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
}FSMC_PCCARDInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/*-------------------------------FSMC Banks definitions ----------------------*/
#define FSMC_Bank1_NORSRAM1 ((u32)0x00000000)
#define FSMC_Bank1_NORSRAM2 ((u32)0x00000002)
#define FSMC_Bank1_NORSRAM3 ((u32)0x00000004)
#define FSMC_Bank1_NORSRAM4 ((u32)0x00000006)
#define FSMC_Bank2_NAND ((u32)0x00000010)
#define FSMC_Bank3_NAND ((u32)0x00000100)
#define FSMC_Bank4_PCCARD ((u32)0x00001000)
/**
* @}
*/
/** @defgroup FSMC_Exported_Constants
* @{
*/
/** @defgroup FSMC_NORSRAM_Bank
* @{
*/
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
/**
* @}
*/
/** @defgroup FSMC_NAND_Bank
* @{
*/
#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
/**
* @}
*/
/** @defgroup FSMC_PCCARD_Bank
* @{
*/
#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
/**
* @}
*/
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
((BANK) == FSMC_Bank1_NORSRAM2) || \
((BANK) == FSMC_Bank1_NORSRAM3) || \
((BANK) == FSMC_Bank1_NORSRAM4))
((BANK) == FSMC_Bank1_NORSRAM4))
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND))
@ -118,210 +277,407 @@ typedef struct
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND) || \
((BANK) == FSMC_Bank4_PCCARD))
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND) || \
((BANK) == FSMC_Bank4_PCCARD))
((BANK) == FSMC_Bank4_PCCARD))
/** @defgroup NOR_SRAM_Controller
* @{
*/
/*------------------------------- NOR/SRAM Banks -----------------------------*/
/* FSMC Data/Address Bus Multiplexing ----------------------------------------*/
#define FSMC_DataAddressMux_Disable ((u32)0x00000000)
#define FSMC_DataAddressMux_Enable ((u32)0x00000002)
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
* @{
*/
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
((MUX) == FSMC_DataAddressMux_Enable))
((MUX) == FSMC_DataAddressMux_Enable))
/* FSMC Memory Type ----------------------------------------------------------*/
#define FSMC_MemoryType_SRAM ((u32)0x00000000)
#define FSMC_MemoryType_PSRAM ((u32)0x00000004)
#define FSMC_MemoryType_NOR ((u32)0x00000008)
/**
* @}
*/
/** @defgroup FSMC_Memory_Type
* @{
*/
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
((MEMORY) == FSMC_MemoryType_NOR))
/* FSMC Data Width ----------------------------------------------------------*/
#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)
#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)
/**
* @}
*/
/** @defgroup FSMC_Data_Width
* @{
*/
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
/* FSMC Burst Access Mode ----------------------------------------------------*/
#define FSMC_BurstAccessMode_Disable ((u32)0x00000000)
#define FSMC_BurstAccessMode_Enable ((u32)0x00000100)
/**
* @}
*/
/** @defgroup FSMC_Burst_Access_Mode
* @{
*/
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
((STATE) == FSMC_BurstAccessMode_Enable))
/**
* @}
*/
/* FSMC Wait Signal Polarity -------------------------------------------------*/
#define FSMC_WaitSignalPolarity_Low ((u32)0x00000000)
#define FSMC_WaitSignalPolarity_High ((u32)0x00000200)
/** @defgroup FSMC_Wait_Signal_Polarity
* @{
*/
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
((POLARITY) == FSMC_WaitSignalPolarity_High))
/* FSMC Wrap Mode ------------------------------------------------------------*/
#define FSMC_WrapMode_Disable ((u32)0x00000000)
#define FSMC_WrapMode_Enable ((u32)0x00000400)
/**
* @}
*/
/** @defgroup FSMC_Wrap_Mode
* @{
*/
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
((MODE) == FSMC_WrapMode_Enable))
/* FSMC Wait Timing ----------------------------------------------------------*/
#define FSMC_WaitSignalActive_BeforeWaitState ((u32)0x00000000)
#define FSMC_WaitSignalActive_DuringWaitState ((u32)0x00000800)
/**
* @}
*/
/** @defgroup FSMC_Wait_Timing
* @{
*/
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
/* FSMC Write Operation ------------------------------------------------------*/
#define FSMC_WriteOperation_Disable ((u32)0x00000000)
#define FSMC_WriteOperation_Enable ((u32)0x00001000)
/**
* @}
*/
/** @defgroup FSMC_Write_Operation
* @{
*/
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
((OPERATION) == FSMC_WriteOperation_Enable))
/* FSMC Wait Signal ----------------------------------------------------------*/
#define FSMC_WaitSignal_Disable ((u32)0x00000000)
#define FSMC_WaitSignal_Enable ((u32)0x00002000)
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal
* @{
*/
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
((SIGNAL) == FSMC_WaitSignal_Enable))
/**
* @}
*/
/* FSMC Extended Mode --------------------------------------------------------*/
#define FSMC_ExtendedMode_Disable ((u32)0x00000000)
#define FSMC_ExtendedMode_Enable ((u32)0x00004000)
/** @defgroup FSMC_Extended_Mode
* @{
*/
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
((MODE) == FSMC_ExtendedMode_Enable))
/* FSMC Write Burst ----------------------------------------------------------*/
#define FSMC_WriteBurst_Disable ((u32)0x00000000)
#define FSMC_WriteBurst_Enable ((u32)0x00080000)
/**
* @}
*/
/** @defgroup FSMC_Write_Burst
* @{
*/
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
((BURST) == FSMC_WriteBurst_Enable))
/**
* @}
*/
/** @defgroup FSMC_Address_Setup_Time
* @{
*/
/* FSMC Address Setup Time ---------------------------------------------------*/
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
/* FSMC Address Hold Time ----------------------------------------------------*/
/**
* @}
*/
/** @defgroup FSMC_Address_Hold_Time
* @{
*/
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
/* FSMC Data Setup Time ------------------------------------------------------*/
/**
* @}
*/
/** @defgroup FSMC_Data_Setup_Time
* @{
*/
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
/* FSMC Bus Turn around Duration ---------------------------------------------*/
/**
* @}
*/
/** @defgroup FSMC_Bus_Turn_around_Duration
* @{
*/
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
/* FSMC CLK Division ---------------------------------------------------------*/
/**
* @}
*/
/** @defgroup FSMC_CLK_Division
* @{
*/
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
/* FSMC Data Latency ---------------------------------------------------------*/
/**
* @}
*/
/** @defgroup FSMC_Data_Latency
* @{
*/
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
/* FSMC Access Mode ----------------------------------------------------------*/
#define FSMC_AccessMode_A ((u32)0x00000000)
#define FSMC_AccessMode_B ((u32)0x10000000)
#define FSMC_AccessMode_C ((u32)0x20000000)
#define FSMC_AccessMode_D ((u32)0x30000000)
/**
* @}
*/
/** @defgroup FSMC_Access_Mode
* @{
*/
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
((MODE) == FSMC_AccessMode_B) || \
((MODE) == FSMC_AccessMode_C) || \
((MODE) == FSMC_AccessMode_D))
/*----------------------------- NAND and PCCARD Banks ------------------------*/
/* FSMC Wait feature ---------------------------------------------------------*/
#define FSMC_Waitfeature_Disable ((u32)0x00000000)
#define FSMC_Waitfeature_Enable ((u32)0x00000002)
/**
* @}
*/
/**
* @}
*/
/** @defgroup NAND_PCCARD_Controller
* @{
*/
/** @defgroup FSMC_Wait_feature
* @{
*/
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
((FEATURE) == FSMC_Waitfeature_Enable))
/* FSMC Memory Data Width ----------------------------------------------------*/
#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)
#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)
#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
/* FSMC ECC ------------------------------------------------------------------*/
#define FSMC_ECC_Disable ((u32)0x00000000)
#define FSMC_ECC_Enable ((u32)0x00000040)
/**
* @}
*/
/** @defgroup FSMC_ECC
* @{
*/
#define FSMC_ECC_Disable ((uint32_t)0x00000000)
#define FSMC_ECC_Enable ((uint32_t)0x00000040)
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
((STATE) == FSMC_ECC_Enable))
/* FSMC ECC Page Size --------------------------------------------------------*/
#define FSMC_ECCPageSize_256Bytes ((u32)0x00000000)
#define FSMC_ECCPageSize_512Bytes ((u32)0x00020000)
#define FSMC_ECCPageSize_1024Bytes ((u32)0x00040000)
#define FSMC_ECCPageSize_2048Bytes ((u32)0x00060000)
#define FSMC_ECCPageSize_4096Bytes ((u32)0x00080000)
#define FSMC_ECCPageSize_8192Bytes ((u32)0x000A0000)
/**
* @}
*/
/** @defgroup FSMC_ECC_Page_Size
* @{
*/
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
((SIZE) == FSMC_ECCPageSize_8192Bytes))
/* FSMC Address Low Mapping --------------------------------------------------*/
#define FSMC_AddressLowMapping_Direct ((u32)0x00000000)
#define FSMC_AddressLowMapping_InDirect ((u32)0x00000100)
#define IS_FSMC_ADDRESS_LOW_MAPPING(MAPPING) (((MAPPING) == FSMC_AddressLowMapping_Direct) || \
((MAPPING) == FSMC_AddressLowMapping_InDirect))
/* FSMC TCLR Setup Time ------------------------------------------------------*/
/**
* @}
*/
/** @defgroup FSMC_TCLR_Setup_Time
* @{
*/
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
/* FSMC TAR Setup Time -------------------------------------------------------*/
/**
* @}
*/
/** @defgroup FSMC_TAR_Setup_Time
* @{
*/
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
/* FSMC Setup Time ----------------------------------------------------*/
/**
* @}
*/
/** @defgroup FSMC_Setup_Time
* @{
*/
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
/* FSMC Wait Setup Time -----------------------------------------------*/
/**
* @}
*/
/** @defgroup FSMC_Wait_Setup_Time
* @{
*/
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
/* FSMC Hold Setup Time -----------------------------------------------*/
/**
* @}
*/
/** @defgroup FSMC_Hold_Setup_Time
* @{
*/
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
/* FSMC HiZ Setup Time ------------------------------------------------*/
/**
* @}
*/
/** @defgroup FSMC_HiZ_Setup_Time
* @{
*/
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
/* FSMC Interrupt sources ----------------------------------------------------*/
#define FSMC_IT_RisingEdge ((u32)0x00000008)
#define FSMC_IT_Level ((u32)0x00000010)
#define FSMC_IT_FallingEdge ((u32)0x00000020)
/**
* @}
*/
#define IS_FSMC_IT(IT) ((((IT) & (u32)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
/** @defgroup FSMC_Interrupt_sources
* @{
*/
#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
#define FSMC_IT_Level ((uint32_t)0x00000010)
#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
((IT) == FSMC_IT_Level) || \
((IT) == FSMC_IT_FallingEdge))
/**
* @}
*/
/* FSMC Flags ----------------------------------------------------------------*/
#define FSMC_FLAG_RisingEdge ((u32)0x00000001)
#define FSMC_FLAG_Level ((u32)0x00000002)
#define FSMC_FLAG_FallingEdge ((u32)0x00000004)
#define FSMC_FLAG_FEMPT ((u32)0x00000040)
/** @defgroup FSMC_Flags
* @{
*/
#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
#define FSMC_FLAG_Level ((uint32_t)0x00000002)
#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
((FLAG) == FSMC_FLAG_Level) || \
((FLAG) == FSMC_FLAG_FallingEdge) || \
((FLAG) == FSMC_FLAG_FEMPT))
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void FSMC_NORSRAMDeInit(u32 FSMC_Bank);
void FSMC_NANDDeInit(u32 FSMC_Bank);
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/** @defgroup FSMC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup FSMC_Exported_Functions
* @{
*/
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
void FSMC_PCCARDDeInit(void);
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
@ -329,17 +685,32 @@ void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState);
void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState);
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
void FSMC_PCCARDCmd(FunctionalState NewState);
void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState);
u32 FSMC_GetECC(u32 FSMC_Bank);
void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState);
FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG);
void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG);
ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT);
void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT);
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F10x_FSMC_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

378
src/platform/stm32/FWLib/library/inc/stm32f10x_gpio.h
View File

@ -1,47 +1,72 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_gpio.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_gpio.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_GPIO_H
#define __STM32F10x_GPIO_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == GPIOA_BASE) || \
((*(u32*)&(PERIPH)) == GPIOB_BASE) || \
((*(u32*)&(PERIPH)) == GPIOC_BASE) || \
((*(u32*)&(PERIPH)) == GPIOD_BASE) || \
((*(u32*)&(PERIPH)) == GPIOE_BASE) || \
((*(u32*)&(PERIPH)) == GPIOF_BASE) || \
((*(u32*)&(PERIPH)) == GPIOG_BASE))
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** @defgroup GPIO_Exported_Types
* @{
*/
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
((PERIPH) == GPIOB) || \
((PERIPH) == GPIOC) || \
((PERIPH) == GPIOD) || \
((PERIPH) == GPIOE) || \
((PERIPH) == GPIOF) || \
((PERIPH) == GPIOG))
/* Output Maximum frequency selection ----------------------------------------*/
/**
* @brief Output Maximum frequency selection
*/
typedef enum
{
GPIO_Speed_10MHz = 1,
GPIO_Speed_2MHz,
GPIO_Speed_50MHz
}GPIOSpeed_TypeDef;
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
((SPEED) == GPIO_Speed_50MHz))
/* Configuration Mode enumeration --------------------------------------------*/
/**
* @brief Configuration Mode enumeration
*/
typedef enum
{ GPIO_Mode_AIN = 0x0,
GPIO_Mode_IN_FLOATING = 0x04,
@ -57,43 +82,66 @@ typedef enum
((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
/* GPIO Init structure definition */
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
u16 GPIO_Pin;
GPIOSpeed_TypeDef GPIO_Speed;
GPIOMode_TypeDef GPIO_Mode;
uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
}GPIO_InitTypeDef;
/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/
/**
* @brief Bit_SET and Bit_RESET enumeration
*/
typedef enum
{ Bit_RESET = 0,
Bit_SET
}BitAction;
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
/* Exported constants --------------------------------------------------------*/
/* GPIO pins define ----------------------------------------------------------*/
#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */
#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */
#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */
#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */
#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */
#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */
#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */
#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */
#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */
#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */
#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */
#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */
#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */
#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */
#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */
#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */
#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */
/**
* @}
*/
#define IS_GPIO_PIN(PIN) ((((PIN) & (u16)0x00) == 0x00) && ((PIN) != (u16)0x00))
/** @defgroup GPIO_Exported_Constants
* @{
*/
/** @defgroup GPIO_pins_define
* @{
*/
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \
@ -111,34 +159,47 @@ typedef enum
((PIN) == GPIO_Pin_13) || \
((PIN) == GPIO_Pin_14) || \
((PIN) == GPIO_Pin_15))
/* GPIO Remap define ---------------------------------------------------------*/
#define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */
#define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */
#define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */
#define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */
#define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */
#define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */
#define GPIO_Remap1_CAN ((u32)0x001D4000) /* CAN Alternate Function mapping */
#define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */
#define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */
#define GPIO_Remap_TIM5CH4_LSI ((u32)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
#define GPIO_Remap_ADC1_ETRGINJ ((u32)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC1_ETRGREG ((u32)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ADC2_ETRGINJ ((u32)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC2_ETRGREG ((u32)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */
#define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */
#define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
/**
* @}
*/
/** @defgroup GPIO_Remap_define
* @{
*/
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3 Alternate Function mapping (only for Connectivity line devices) */
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
to TIM2 Internal Trigger 1 for calibration
(only for Connectivity line devices) */
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
@ -147,28 +208,36 @@ typedef enum
((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
((REMAP) == GPIO_Remap1_CAN) || ((REMAP) == GPIO_Remap2_CAN) || \
((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
((REMAP) == GPIO_Remap_SWJ_Disable))
((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS))
/* GPIO Port Sources ---------------------------------------------------------*/
#define GPIO_PortSourceGPIOA ((u8)0x00)
#define GPIO_PortSourceGPIOB ((u8)0x01)
#define GPIO_PortSourceGPIOC ((u8)0x02)
#define GPIO_PortSourceGPIOD ((u8)0x03)
#define GPIO_PortSourceGPIOE ((u8)0x04)
#define GPIO_PortSourceGPIOF ((u8)0x05)
#define GPIO_PortSourceGPIOG ((u8)0x06)
/**
* @}
*/
/** @defgroup GPIO_Port_Sources
* @{
*/
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
((PORTSOURCE) == GPIO_PortSourceGPIOE))
#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
@ -176,24 +245,31 @@ typedef enum
((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
((PORTSOURCE) == GPIO_PortSourceGPIOG))
/* GPIO Pin sources ----------------------------------------------------------*/
#define GPIO_PinSource0 ((u8)0x00)
#define GPIO_PinSource1 ((u8)0x01)
#define GPIO_PinSource2 ((u8)0x02)
#define GPIO_PinSource3 ((u8)0x03)
#define GPIO_PinSource4 ((u8)0x04)
#define GPIO_PinSource5 ((u8)0x05)
#define GPIO_PinSource6 ((u8)0x06)
#define GPIO_PinSource7 ((u8)0x07)
#define GPIO_PinSource8 ((u8)0x08)
#define GPIO_PinSource9 ((u8)0x09)
#define GPIO_PinSource10 ((u8)0x0A)
#define GPIO_PinSource11 ((u8)0x0B)
#define GPIO_PinSource12 ((u8)0x0C)
#define GPIO_PinSource13 ((u8)0x0D)
#define GPIO_PinSource14 ((u8)0x0E)
#define GPIO_PinSource15 ((u8)0x0F)
/**
* @}
*/
/** @defgroup GPIO_Pin_sources
* @{
*/
#define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07)
#define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A)
#define GPIO_PinSource11 ((uint8_t)0x0B)
#define GPIO_PinSource12 ((uint8_t)0x0C)
#define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F)
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
((PINSOURCE) == GPIO_PinSource1) || \
@ -211,27 +287,73 @@ typedef enum
((PINSOURCE) == GPIO_PinSource13) || \
((PINSOURCE) == GPIO_PinSource14) || \
((PINSOURCE) == GPIO_PinSource15))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* @}
*/
/** @defgroup Ethernet_Media_Interface
* @{
*/
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
/**
* @}
*/
/**
* @}
*/
/** @defgroup GPIO_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions
* @{
*/
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_EventOutputCmd(FunctionalState NewState);
void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState);
void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_GPIO_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

510
src/platform/stm32/FWLib/library/inc/stm32f10x_i2c.h
View File

@ -1,89 +1,158 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_i2c.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* I2C firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_i2c.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_I2C_H
#ifndef __STM32F10x_I2C_H
#define __STM32F10x_I2C_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/** @defgroup I2C_Exported_Types
* @{
*/
/**
* @brief I2C Init structure definition
*/
/* Exported types ------------------------------------------------------------*/
/* I2C Init structure definition */
typedef struct
{
u16 I2C_Mode;
u16 I2C_DutyCycle;
u16 I2C_OwnAddress1;
u16 I2C_Ack;
u16 I2C_AcknowledgedAddress;
u32 I2C_ClockSpeed;
uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */
uint16_t I2C_Mode; /*!< Specifies the I2C mode.
This parameter can be a value of @ref I2C_mode */
uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
This parameter can be a value of @ref I2C_acknowledgement */
uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */
}I2C_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
#define IS_I2C_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == I2C1_BASE) || \
((*(u32*)&(PERIPH)) == I2C2_BASE))
/**
* @}
*/
/* I2C modes */
#define I2C_Mode_I2C ((u16)0x0000)
#define I2C_Mode_SMBusDevice ((u16)0x0002)
#define I2C_Mode_SMBusHost ((u16)0x000A)
/** @defgroup I2C_Exported_Constants
* @{
*/
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
((PERIPH) == I2C2))
/** @defgroup I2C_mode
* @{
*/
#define I2C_Mode_I2C ((uint16_t)0x0000)
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
((MODE) == I2C_Mode_SMBusDevice) || \
((MODE) == I2C_Mode_SMBusHost))
/* I2C duty cycle in fast mode */
#define I2C_DutyCycle_16_9 ((u16)0x4000)
#define I2C_DutyCycle_2 ((u16)0xBFFF)
/**
* @}
*/
/** @defgroup I2C_duty_cycle_in_fast_mode
* @{
*/
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
((CYCLE) == I2C_DutyCycle_2))
/**
* @}
*/
/* I2C cknowledgementy */
#define I2C_Ack_Enable ((u16)0x0400)
#define I2C_Ack_Disable ((u16)0x0000)
/** @defgroup I2C_acknowledgement
* @{
*/
#define I2C_Ack_Enable ((uint16_t)0x0400)
#define I2C_Ack_Disable ((uint16_t)0x0000)
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
((STATE) == I2C_Ack_Disable))
/**
* @}
*/
/* I2C transfer direction */
#define I2C_Direction_Transmitter ((u8)0x00)
#define I2C_Direction_Receiver ((u8)0x01)
/** @defgroup I2C_transfer_direction
* @{
*/
#define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01)
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
((DIRECTION) == I2C_Direction_Receiver))
/**
* @}
*/
/* I2C acknowledged address defines */
#define I2C_AcknowledgedAddress_7bit ((u16)0x4000)
#define I2C_AcknowledgedAddress_10bit ((u16)0xC000)
/** @defgroup I2C_acknowledged_address
* @{
*/
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
/**
* @}
*/
/* I2C registers */
#define I2C_Register_CR1 ((u8)0x00)
#define I2C_Register_CR2 ((u8)0x04)
#define I2C_Register_OAR1 ((u8)0x08)
#define I2C_Register_OAR2 ((u8)0x0C)
#define I2C_Register_DR ((u8)0x10)
#define I2C_Register_SR1 ((u8)0x14)
#define I2C_Register_SR2 ((u8)0x18)
#define I2C_Register_CCR ((u8)0x1C)
#define I2C_Register_TRISE ((u8)0x20)
/** @defgroup I2C_registers
* @{
*/
#define I2C_Register_CR1 ((uint8_t)0x00)
#define I2C_Register_CR2 ((uint8_t)0x04)
#define I2C_Register_OAR1 ((uint8_t)0x08)
#define I2C_Register_OAR2 ((uint8_t)0x0C)
#define I2C_Register_DR ((uint8_t)0x10)
#define I2C_Register_SR1 ((uint8_t)0x14)
#define I2C_Register_SR2 ((uint8_t)0x18)
#define I2C_Register_CCR ((uint8_t)0x1C)
#define I2C_Register_TRISE ((uint8_t)0x20)
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
((REGISTER) == I2C_Register_CR2) || \
((REGISTER) == I2C_Register_OAR1) || \
@ -93,45 +162,66 @@ typedef struct
((REGISTER) == I2C_Register_SR2) || \
((REGISTER) == I2C_Register_CCR) || \
((REGISTER) == I2C_Register_TRISE))
/**
* @}
*/
/* I2C SMBus alert pin level */
#define I2C_SMBusAlert_Low ((u16)0x2000)
#define I2C_SMBusAlert_High ((u16)0xDFFF)
/** @defgroup I2C_SMBus_alert_pin_level
* @{
*/
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
((ALERT) == I2C_SMBusAlert_High))
/**
* @}
*/
/* I2C PEC position */
#define I2C_PECPosition_Next ((u16)0x0800)
#define I2C_PECPosition_Current ((u16)0xF7FF)
/** @defgroup I2C_PEC_position
* @{
*/
#define I2C_PECPosition_Next ((uint16_t)0x0800)
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
((POSITION) == I2C_PECPosition_Current))
/**
* @}
*/
/* I2C interrupts definition */
#define I2C_IT_BUF ((u16)0x0400)
#define I2C_IT_EVT ((u16)0x0200)
#define I2C_IT_ERR ((u16)0x0100)
/** @defgroup I2C_interrupts_definition
* @{
*/
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (u16)0xF8FF) == 0x00) && ((IT) != 0x00))
#define I2C_IT_BUF ((uint16_t)0x0400)
#define I2C_IT_EVT ((uint16_t)0x0200)
#define I2C_IT_ERR ((uint16_t)0x0100)
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/* I2C interrupts definition */
#define I2C_IT_SMBALERT ((u32)0x01008000)
#define I2C_IT_TIMEOUT ((u32)0x01004000)
#define I2C_IT_PECERR ((u32)0x01001000)
#define I2C_IT_OVR ((u32)0x01000800)
#define I2C_IT_AF ((u32)0x01000400)
#define I2C_IT_ARLO ((u32)0x01000200)
#define I2C_IT_BERR ((u32)0x01000100)
#define I2C_IT_TXE ((u32)0x06000080)
#define I2C_IT_RXNE ((u32)0x06000040)
#define I2C_IT_STOPF ((u32)0x02000010)
#define I2C_IT_ADD10 ((u32)0x02000008)
#define I2C_IT_BTF ((u32)0x02000004)
#define I2C_IT_ADDR ((u32)0x02000002)
#define I2C_IT_SB ((u32)0x02000001)
/** @defgroup I2C_interrupts_definition
* @{
*/
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (u16)0x20FF) == 0x00) && ((IT) != (u16)0x00))
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
#define I2C_IT_PECERR ((uint32_t)0x01001000)
#define I2C_IT_OVR ((uint32_t)0x01000800)
#define I2C_IT_AF ((uint32_t)0x01000400)
#define I2C_IT_ARLO ((uint32_t)0x01000200)
#define I2C_IT_BERR ((uint32_t)0x01000100)
#define I2C_IT_TXE ((uint32_t)0x06000080)
#define I2C_IT_RXNE ((uint32_t)0x06000040)
#define I2C_IT_STOPF ((uint32_t)0x02000010)
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
#define I2C_IT_BTF ((uint32_t)0x02000004)
#define I2C_IT_ADDR ((uint32_t)0x02000002)
#define I2C_IT_SB ((uint32_t)0x02000001)
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
@ -140,33 +230,46 @@ typedef struct
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
/**
* @}
*/
/* I2C flags definition */
/* SR2 register flags */
#define I2C_FLAG_DUALF ((u32)0x00800000)
#define I2C_FLAG_SMBHOST ((u32)0x00400000)
#define I2C_FLAG_SMBDEFAULT ((u32)0x00200000)
#define I2C_FLAG_GENCALL ((u32)0x00100000)
#define I2C_FLAG_TRA ((u32)0x00040000)
#define I2C_FLAG_BUSY ((u32)0x00020000)
#define I2C_FLAG_MSL ((u32)0x00010000)
/* SR1 register flags */
#define I2C_FLAG_SMBALERT ((u32)0x10008000)
#define I2C_FLAG_TIMEOUT ((u32)0x10004000)
#define I2C_FLAG_PECERR ((u32)0x10001000)
#define I2C_FLAG_OVR ((u32)0x10000800)
#define I2C_FLAG_AF ((u32)0x10000400)
#define I2C_FLAG_ARLO ((u32)0x10000200)
#define I2C_FLAG_BERR ((u32)0x10000100)
#define I2C_FLAG_TXE ((u32)0x10000080)
#define I2C_FLAG_RXNE ((u32)0x10000040)
#define I2C_FLAG_STOPF ((u32)0x10000010)
#define I2C_FLAG_ADD10 ((u32)0x10000008)
#define I2C_FLAG_BTF ((u32)0x10000004)
#define I2C_FLAG_ADDR ((u32)0x10000002)
#define I2C_FLAG_SB ((u32)0x10000001)
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0x20FF) == 0x00) && ((FLAG) != (u16)0x00))
/** @defgroup I2C_flags_definition
* @{
*/
/**
* @brief SR2 register flags
*/
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
/**
* @brief SR1 register flags
*/
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
#define I2C_FLAG_AF ((uint32_t)0x10000400)
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define I2C_FLAG_SB ((uint32_t)0x10000001)
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
@ -179,45 +282,84 @@ typedef struct
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
((FLAG) == I2C_FLAG_SB))
/**
* @}
*/
/* I2C Events */
/* EV1 */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((u32)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((u32)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((u32)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((u32)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((u32)0x00120000) /* GENCALL and BUSY flags */
/** @defgroup I2C_Events
* @{
*/
/* EV2 */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((u32)0x00020040) /* BUSY and RXNE flags */
/* EV3 */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((u32)0x00060084) /* TRA, BUSY, TXE and BTF flags */
/**
* @brief EV1
*/
/* EV4 */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((u32)0x00000010) /* STOPF flag */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
/* EV5 */
#define I2C_EVENT_MASTER_MODE_SELECT ((u32)0x00030001) /* BUSY, MSL and SB flag */
/**
* @brief EV2
*/
/* EV6 */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((u32)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((u32)0x00030002) /* BUSY, MSL and ADDR flags */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
/* EV7 */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((u32)0x00030040) /* BUSY, MSL and RXNE flags */
/**
* @brief EV3
*/
/* EV8 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((u32)0x00070080) /* TRA, BUSY, MSL, TXE flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
/* EV8_2 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((u32)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/* EV9 */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((u32)0x00030008) /* BUSY, MSL and ADD10 flags */
/* EV3_2 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((u32)0x00000400) /* AF flag */
/**
* @brief EV4
*/
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
/**
* @brief EV5
*/
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
/**
* @brief EV6
*/
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
/**
* @brief EV7
*/
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
/**
* @brief EV8
*/
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
/**
* @brief EV8_2
*/
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/**
* @brief EV9
*/
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
/**
* @brief EV3_2
*/
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
@ -236,16 +378,47 @@ typedef struct
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
/**
* @}
*/
/** @defgroup I2C_own_address1
* @{
*/
/* I2C own address1 -----------------------------------------------------------*/
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
/* I2C clock speed ------------------------------------------------------------*/
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
/**
* @}
*/
/** @defgroup I2C_clock_speed
* @{
*/
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
/**
* @}
*/
/**
* @}
*/
/** @defgroup I2C_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup I2C_Exported_Functions
* @{
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
@ -255,30 +428,45 @@ void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address);
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data);
u8 I2C_ReceiveData(I2C_TypeDef* I2Cx);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction);
u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register);
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert);
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition);
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
u8 I2C_GetPEC(I2C_TypeDef* I2Cx);
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle);
u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx);
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT);
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F10x_I2C_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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src/platform/stm32/FWLib/library/inc/stm32f10x_iwdg.h
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@ -1,44 +1,78 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_iwdg.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* IWDG firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_iwdg.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_IWDG_H
#define __STM32F10x_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#include "stm32f10x.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Write access to IWDG_PR and IWDG_RLR registers */
#define IWDG_WriteAccess_Enable ((u16)0x5555)
#define IWDG_WriteAccess_Disable ((u16)0x0000)
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup IWDG
* @{
*/
/** @defgroup IWDG_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_Constants
* @{
*/
/** @defgroup IWDG_WriteAccess
* @{
*/
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
((ACCESS) == IWDG_WriteAccess_Disable))
/**
* @}
*/
/* IWDG prescaler */
#define IWDG_Prescaler_4 ((u8)0x00)
#define IWDG_Prescaler_8 ((u8)0x01)
#define IWDG_Prescaler_16 ((u8)0x02)
#define IWDG_Prescaler_32 ((u8)0x03)
#define IWDG_Prescaler_64 ((u8)0x04)
#define IWDG_Prescaler_128 ((u8)0x05)
#define IWDG_Prescaler_256 ((u8)0x06)
/** @defgroup IWDG_prescaler
* @{
*/
#define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_8 ((uint8_t)0x01)
#define IWDG_Prescaler_16 ((uint8_t)0x02)
#define IWDG_Prescaler_32 ((uint8_t)0x03)
#define IWDG_Prescaler_64 ((uint8_t)0x04)
#define IWDG_Prescaler_128 ((uint8_t)0x05)
#define IWDG_Prescaler_256 ((uint8_t)0x06)
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
((PRESCALER) == IWDG_Prescaler_8) || \
((PRESCALER) == IWDG_Prescaler_16) || \
@ -46,24 +80,60 @@
((PRESCALER) == IWDG_Prescaler_64) || \
((PRESCALER) == IWDG_Prescaler_128)|| \
((PRESCALER) == IWDG_Prescaler_256))
/**
* @}
*/
/* IWDG Flag */
#define IWDG_FLAG_PVU ((u16)0x0001)
#define IWDG_FLAG_RVU ((u16)0x0002)
/** @defgroup IWDG_Flag
* @{
*/
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess);
void IWDG_SetPrescaler(u8 IWDG_Prescaler);
void IWDG_SetReload(u16 Reload);
/**
* @}
*/
/** @defgroup IWDG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions
* @{
*/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG);
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_IWDG_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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src/platform/stm32/FWLib/library/inc/stm32f10x_lib.h
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@ -1,124 +0,0 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_lib.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file includes the peripherals header files in the
* user application.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_LIB_H
#define __STM32F10x_LIB_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef _ADC
#include "stm32f10x_adc.h"
#endif /*_ADC */
#ifdef _BKP
#include "stm32f10x_bkp.h"
#endif /*_BKP */
#ifdef _CAN
#include "stm32f10x_can.h"
#endif /*_CAN */
#ifdef _CRC
#include "stm32f10x_crc.h"
#endif /*_CRC */
#ifdef _DAC
#include "stm32f10x_dac.h"
#endif /*_DAC */
#ifdef _DBGMCU
#include "stm32f10x_dbgmcu.h"
#endif /*_DBGMCU */
#ifdef _DMA
#include "stm32f10x_dma.h"
#endif /*_DMA */
#ifdef _EXTI
#include "stm32f10x_exti.h"
#endif /*_EXTI */
#ifdef _FLASH
#include "stm32f10x_flash.h"
#endif /*_FLASH */
#ifdef _FSMC
#include "stm32f10x_fsmc.h"
#endif /*_FSMC */
#ifdef _GPIO
#include "stm32f10x_gpio.h"
#endif /*_GPIO */
#ifdef _I2C
#include "stm32f10x_i2c.h"
#endif /*_I2C */
#ifdef _IWDG
#include "stm32f10x_iwdg.h"
#endif /*_IWDG */
#ifdef _NVIC
#include "stm32f10x_nvic.h"
#endif /*_NVIC */
#ifdef _PWR
#include "stm32f10x_pwr.h"
#endif /*_PWR */
#ifdef _RCC
#include "stm32f10x_rcc.h"
#endif /*_RCC */
#ifdef _RTC
#include "stm32f10x_rtc.h"
#endif /*_RTC */
#ifdef _SDIO
#include "stm32f10x_sdio.h"
#endif /*_SDIO */
#ifdef _SPI
#include "stm32f10x_spi.h"
#endif /*_SPI */
#ifdef _SysTick
#include "stm32f10x_systick.h"
#endif /*_SysTick */
#ifdef _TIM
#include "stm32f10x_tim.h"
#endif /*_TIM */
#ifdef _USART
#include "stm32f10x_usart.h"
#endif /*_USART */
#ifdef _WWDG
#include "stm32f10x_wwdg.h"
#endif /*_WWDG */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void debug(void);
#endif /* __STM32F10x_LIB_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

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src/platform/stm32/FWLib/library/inc/stm32f10x_map.h
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src/platform/stm32/FWLib/library/inc/stm32f10x_nvic.h
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@ -1,287 +0,0 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_nvic.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* NVIC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_NVIC_H
#define __STM32F10x_NVIC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* NVIC Init Structure definition */
typedef struct
{
u8 NVIC_IRQChannel;
u8 NVIC_IRQChannelPreemptionPriority;
u8 NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* IRQ Channels --------------------------------------------------------------*/
#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */
#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */
#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */
#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */
#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */
#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */
#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */
#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */
#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */
#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */
#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */
#define DMA1_Channel1_IRQChannel ((u8)0x0B) /* DMA1 Channel 1 global Interrupt */
#define DMA1_Channel2_IRQChannel ((u8)0x0C) /* DMA1 Channel 2 global Interrupt */
#define DMA1_Channel3_IRQChannel ((u8)0x0D) /* DMA1 Channel 3 global Interrupt */
#define DMA1_Channel4_IRQChannel ((u8)0x0E) /* DMA1 Channel 4 global Interrupt */
#define DMA1_Channel5_IRQChannel ((u8)0x0F) /* DMA1 Channel 5 global Interrupt */
#define DMA1_Channel6_IRQChannel ((u8)0x10) /* DMA1 Channel 6 global Interrupt */
#define DMA1_Channel7_IRQChannel ((u8)0x11) /* DMA1 Channel 7 global Interrupt */
#define ADC1_2_IRQChannel ((u8)0x12) /* ADC1 et ADC2 global Interrupt */
#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */
#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */
#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */
#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */
#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */
#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */
#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */
#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */
#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */
#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */
#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */
#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */
#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */
#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */
#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */
#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */
#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */
#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */
#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */
#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */
#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */
#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */
#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */
#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */
#define TIM8_BRK_IRQChannel ((u8)0x2B) /* TIM8 Break Interrupt */
#define TIM8_UP_IRQChannel ((u8)0x2C) /* TIM8 Update Interrupt */
#define TIM8_TRG_COM_IRQChannel ((u8)0x2D) /* TIM8 Trigger and Commutation Interrupt */
#define TIM8_CC_IRQChannel ((u8)0x2E) /* TIM8 Capture Compare Interrupt */
#define ADC3_IRQChannel ((u8)0x2F) /* ADC3 global Interrupt */
#define FSMC_IRQChannel ((u8)0x30) /* FSMC global Interrupt */
#define SDIO_IRQChannel ((u8)0x31) /* SDIO global Interrupt */
#define TIM5_IRQChannel ((u8)0x32) /* TIM5 global Interrupt */
#define SPI3_IRQChannel ((u8)0x33) /* SPI3 global Interrupt */
#define UART4_IRQChannel ((u8)0x34) /* UART4 global Interrupt */
#define UART5_IRQChannel ((u8)0x35) /* UART5 global Interrupt */
#define TIM6_IRQChannel ((u8)0x36) /* TIM6 global Interrupt */
#define TIM7_IRQChannel ((u8)0x37) /* TIM7 global Interrupt */
#define DMA2_Channel1_IRQChannel ((u8)0x38) /* DMA2 Channel 1 global Interrupt */
#define DMA2_Channel2_IRQChannel ((u8)0x39) /* DMA2 Channel 2 global Interrupt */
#define DMA2_Channel3_IRQChannel ((u8)0x3A) /* DMA2 Channel 3 global Interrupt */
#define DMA2_Channel4_5_IRQChannel ((u8)0x3B) /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */
#define IS_NVIC_IRQ_CHANNEL(CHANNEL) (((CHANNEL) == WWDG_IRQChannel) || \
((CHANNEL) == PVD_IRQChannel) || \
((CHANNEL) == TAMPER_IRQChannel) || \
((CHANNEL) == RTC_IRQChannel) || \
((CHANNEL) == FLASH_IRQChannel) || \
((CHANNEL) == RCC_IRQChannel) || \
((CHANNEL) == EXTI0_IRQChannel) || \
((CHANNEL) == EXTI1_IRQChannel) || \
((CHANNEL) == EXTI2_IRQChannel) || \
((CHANNEL) == EXTI3_IRQChannel) || \
((CHANNEL) == EXTI4_IRQChannel) || \
((CHANNEL) == DMA1_Channel1_IRQChannel) || \
((CHANNEL) == DMA1_Channel2_IRQChannel) || \
((CHANNEL) == DMA1_Channel3_IRQChannel) || \
((CHANNEL) == DMA1_Channel4_IRQChannel) || \
((CHANNEL) == DMA1_Channel5_IRQChannel) || \
((CHANNEL) == DMA1_Channel6_IRQChannel) || \
((CHANNEL) == DMA1_Channel7_IRQChannel) || \
((CHANNEL) == ADC1_2_IRQChannel) || \
((CHANNEL) == USB_HP_CAN_TX_IRQChannel) || \
((CHANNEL) == USB_LP_CAN_RX0_IRQChannel) || \
((CHANNEL) == CAN_RX1_IRQChannel) || \
((CHANNEL) == CAN_SCE_IRQChannel) || \
((CHANNEL) == EXTI9_5_IRQChannel) || \
((CHANNEL) == TIM1_BRK_IRQChannel) || \
((CHANNEL) == TIM1_UP_IRQChannel) || \
((CHANNEL) == TIM1_TRG_COM_IRQChannel) || \
((CHANNEL) == TIM1_CC_IRQChannel) || \
((CHANNEL) == TIM2_IRQChannel) || \
((CHANNEL) == TIM3_IRQChannel) || \
((CHANNEL) == TIM4_IRQChannel) || \
((CHANNEL) == I2C1_EV_IRQChannel) || \
((CHANNEL) == I2C1_ER_IRQChannel) || \
((CHANNEL) == I2C2_EV_IRQChannel) || \
((CHANNEL) == I2C2_ER_IRQChannel) || \
((CHANNEL) == SPI1_IRQChannel) || \
((CHANNEL) == SPI2_IRQChannel) || \
((CHANNEL) == USART1_IRQChannel) || \
((CHANNEL) == USART2_IRQChannel) || \
((CHANNEL) == USART3_IRQChannel) || \
((CHANNEL) == EXTI15_10_IRQChannel) || \
((CHANNEL) == RTCAlarm_IRQChannel) || \
((CHANNEL) == USBWakeUp_IRQChannel) || \
((CHANNEL) == TIM8_BRK_IRQChannel) || \
((CHANNEL) == TIM8_UP_IRQChannel) || \
((CHANNEL) == TIM8_TRG_COM_IRQChannel) || \
((CHANNEL) == TIM8_CC_IRQChannel) || \
((CHANNEL) == ADC3_IRQChannel) || \
((CHANNEL) == FSMC_IRQChannel) || \
((CHANNEL) == SDIO_IRQChannel) || \
((CHANNEL) == TIM5_IRQChannel) || \
((CHANNEL) == SPI3_IRQChannel) || \
((CHANNEL) == UART4_IRQChannel) || \
((CHANNEL) == UART5_IRQChannel) || \
((CHANNEL) == TIM6_IRQChannel) || \
((CHANNEL) == TIM7_IRQChannel) || \
((CHANNEL) == DMA2_Channel1_IRQChannel) || \
((CHANNEL) == DMA2_Channel2_IRQChannel) || \
((CHANNEL) == DMA2_Channel3_IRQChannel) || \
((CHANNEL) == DMA2_Channel4_5_IRQChannel))
/* System Handlers -----------------------------------------------------------*/
#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */
#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */
#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */
#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */
#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */
#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */
#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */
#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */
#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */
#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault))
#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault) || \
((HANDLER) == SystemHandler_SVCall) || \
((HANDLER) == SystemHandler_DebugMonitor) || \
((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_SVCall))
#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_NMI) || \
((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault) || \
((HANDLER) == SystemHandler_SVCall) || \
((HANDLER) == SystemHandler_DebugMonitor) || \
((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_HardFault) || \
((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault) || \
((HANDLER) == SystemHandler_DebugMonitor))
#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault))
/* Vector Table Base ---------------------------------------------------------*/
#define NVIC_VectTab_RAM ((u32)0x20000000)
#define NVIC_VectTab_FLASH ((u32)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/* System Low Power ----------------------------------------------------------*/
#define NVIC_LP_SEVONPEND ((u8)0x10)
#define NVIC_LP_SLEEPDEEP ((u8)0x04)
#define NVIC_LP_SLEEPONEXIT ((u8)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/* Preemption Priority Group -------------------------------------------------*/
#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
#define IS_NVIC_BASE_PRI(PRI) ((PRI) < 0x10)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NVIC_DeInit(void);
void NVIC_SCBDeInit(void);
void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SETPRIMASK(void);
void NVIC_RESETPRIMASK(void);
void NVIC_SETFAULTMASK(void);
void NVIC_RESETFAULTMASK(void);
void NVIC_BASEPRICONFIG(u32 NewPriority);
u32 NVIC_GetBASEPRI(void);
u16 NVIC_GetCurrentPendingIRQChannel(void);
ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);
void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);
void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);
u16 NVIC_GetCurrentActiveHandler(void);
ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);
u32 NVIC_GetCPUID(void);
void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);
void NVIC_GenerateSystemReset(void);
void NVIC_GenerateCoreReset(void);
void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);
void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);
void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
u8 SystemHandlerSubPriority);
ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);
void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);
void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);
ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);
u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);
u32 NVIC_GetFaultAddress(u32 SystemHandler);
#endif /* __STM32F10x_NVIC_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

168
src/platform/stm32/FWLib/library/inc/stm32f10x_pwr.h
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@ -1,77 +1,155 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_pwr.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* PWR firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_pwr.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_PWR_H
#define __STM32F10x_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#include "stm32f10x.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* PVD detection level */
#define PWR_PVDLevel_2V2 ((u32)0x00000000)
#define PWR_PVDLevel_2V3 ((u32)0x00000020)
#define PWR_PVDLevel_2V4 ((u32)0x00000040)
#define PWR_PVDLevel_2V5 ((u32)0x00000060)
#define PWR_PVDLevel_2V6 ((u32)0x00000080)
#define PWR_PVDLevel_2V7 ((u32)0x000000A0)
#define PWR_PVDLevel_2V8 ((u32)0x000000C0)
#define PWR_PVDLevel_2V9 ((u32)0x000000E0)
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/** @defgroup PWR_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Constants
* @{
*/
/** @defgroup PVD_detection_level
* @{
*/
#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
/**
* @}
*/
/* Regulator state is STOP mode */
#define PWR_Regulator_ON ((u32)0x00000000)
#define PWR_Regulator_LowPower ((u32)0x00000001)
/** @defgroup Regulator_state_is_STOP_mode
* @{
*/
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
((REGULATOR) == PWR_Regulator_LowPower))
/**
* @}
*/
/* STOP mode entry */
#define PWR_STOPEntry_WFI ((u8)0x01)
#define PWR_STOPEntry_WFE ((u8)0x02)
/** @defgroup STOP_mode_entry
* @{
*/
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
/* PWR Flag */
#define PWR_FLAG_WU ((u32)0x00000001)
#define PWR_FLAG_SB ((u32)0x00000002)
#define PWR_FLAG_PVDO ((u32)0x00000004)
/**
* @}
*/
/** @defgroup PWR_Flag
* @{
*/
#define PWR_FLAG_WU ((uint32_t)0x00000001)
#define PWR_FLAG_SB ((uint32_t)0x00000002)
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_PVDO))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
/**
* @}
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Functions
* @{
*/
void PWR_DeInit(void);
void PWR_BackupAccessCmd(FunctionalState NewState);
void PWR_PVDCmd(FunctionalState NewState);
void PWR_PVDLevelConfig(u32 PWR_PVDLevel);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_WakeUpPinCmd(FunctionalState NewState);
void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry);
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG);
void PWR_ClearFlag(u32 PWR_FLAG);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_PWR_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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src/platform/stm32/FWLib/library/inc/stm32f10x_rcc.h
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@ -1,288 +1,700 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_rcc.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* RCC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_rcc.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the RCC firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RCC_H
#define __STM32F10x_RCC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup RCC
* @{
*/
/** @defgroup RCC_Exported_Types
* @{
*/
/* Exported types ------------------------------------------------------------*/
typedef struct
{
u32 SYSCLK_Frequency;
u32 HCLK_Frequency;
u32 PCLK1_Frequency;
u32 PCLK2_Frequency;
u32 ADCCLK_Frequency;
uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
}RCC_ClocksTypeDef;
/* Exported constants --------------------------------------------------------*/
/* HSE configuration */
#define RCC_HSE_OFF ((u32)0x00000000)
#define RCC_HSE_ON ((u32)0x00010000)
#define RCC_HSE_Bypass ((u32)0x00040000)
/**
* @}
*/
/** @defgroup RCC_Exported_Constants
* @{
*/
/** @defgroup HSE_configuration
* @{
*/
#define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_ON ((uint32_t)0x00010000)
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_Bypass))
/* PLL entry clock source */
#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000)
#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000)
/**
* @}
*/
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
/** @defgroup PLL_entry_clock_source
* @{
*/
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
#ifndef STM32F10X_CL
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
((SOURCE) == RCC_PLLSource_HSE_Div1) || \
((SOURCE) == RCC_PLLSource_HSE_Div2))
#else
#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
((SOURCE) == RCC_PLLSource_PREDIV1))
#endif /* STM32F10X_CL */
/* PLL multiplication factor */
#define RCC_PLLMul_2 ((u32)0x00000000)
#define RCC_PLLMul_3 ((u32)0x00040000)
#define RCC_PLLMul_4 ((u32)0x00080000)
#define RCC_PLLMul_5 ((u32)0x000C0000)
#define RCC_PLLMul_6 ((u32)0x00100000)
#define RCC_PLLMul_7 ((u32)0x00140000)
#define RCC_PLLMul_8 ((u32)0x00180000)
#define RCC_PLLMul_9 ((u32)0x001C0000)
#define RCC_PLLMul_10 ((u32)0x00200000)
#define RCC_PLLMul_11 ((u32)0x00240000)
#define RCC_PLLMul_12 ((u32)0x00280000)
#define RCC_PLLMul_13 ((u32)0x002C0000)
#define RCC_PLLMul_14 ((u32)0x00300000)
#define RCC_PLLMul_15 ((u32)0x00340000)
#define RCC_PLLMul_16 ((u32)0x00380000)
/**
* @}
*/
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
((MUL) == RCC_PLLMul_16))
/** @defgroup PLL_multiplication_factor
* @{
*/
#ifndef STM32F10X_CL
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
((MUL) == RCC_PLLMul_16))
/* System clock source */
#define RCC_SYSCLKSource_HSI ((u32)0x00000000)
#define RCC_SYSCLKSource_HSE ((u32)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002)
#else
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
#define RCC_PLLMul_6_5 ((uint32_t)0x00340000)
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
((MUL) == RCC_PLLMul_6_5))
#endif /* STM32F10X_CL */
/**
* @}
*/
#ifdef STM32F10X_CL
/** @defgroup PREDIV1_division_factor
* @{
*/
#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
/**
* @}
*/
/** @defgroup PREDIV1_clock_source
* @{
*/
/* PREDIV1 clock source (only for STM32 connectivity line devices) */
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
((SOURCE) == RCC_PREDIV1_Source_PLL2))
/**
* @}
*/
/** @defgroup PREDIV2_division_factor
* @{
*/
#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
#define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
/**
* @}
*/
/** @defgroup PLL2_multiplication_factor
* @{
*/
#define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
#define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
#define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
#define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
#define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
((MUL) == RCC_PLL2Mul_20))
/**
* @}
*/
/** @defgroup PLL3_multiplication_factor
* @{
*/
#define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
#define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
#define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
#define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
#define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
((MUL) == RCC_PLL3Mul_20))
/**
* @}
*/
#endif /* STM32F10X_CL */
/** @defgroup System_clock_source
* @{
*/
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
/**
* @}
*/
/* AHB clock source */
#define RCC_SYSCLK_Div1 ((u32)0x00000000)
#define RCC_SYSCLK_Div2 ((u32)0x00000080)
#define RCC_SYSCLK_Div4 ((u32)0x00000090)
#define RCC_SYSCLK_Div8 ((u32)0x000000A0)
#define RCC_SYSCLK_Div16 ((u32)0x000000B0)
#define RCC_SYSCLK_Div64 ((u32)0x000000C0)
#define RCC_SYSCLK_Div128 ((u32)0x000000D0)
#define RCC_SYSCLK_Div256 ((u32)0x000000E0)
#define RCC_SYSCLK_Div512 ((u32)0x000000F0)
/** @defgroup AHB_clock_source
* @{
*/
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
((HCLK) == RCC_SYSCLK_Div512))
/**
* @}
*/
/* APB1/APB2 clock source */
#define RCC_HCLK_Div1 ((u32)0x00000000)
#define RCC_HCLK_Div2 ((u32)0x00000400)
#define RCC_HCLK_Div4 ((u32)0x00000500)
#define RCC_HCLK_Div8 ((u32)0x00000600)
#define RCC_HCLK_Div16 ((u32)0x00000700)
/** @defgroup APB1_APB2_clock_source
* @{
*/
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
((PCLK) == RCC_HCLK_Div16))
/**
* @}
*/
/* RCC Interrupt source */
#define RCC_IT_LSIRDY ((u8)0x01)
#define RCC_IT_LSERDY ((u8)0x02)
#define RCC_IT_HSIRDY ((u8)0x04)
#define RCC_IT_HSERDY ((u8)0x08)
#define RCC_IT_PLLRDY ((u8)0x10)
#define RCC_IT_CSS ((u8)0x80)
/** @defgroup RCC_Interrupt_source
* @{
*/
#define IS_RCC_IT(IT) ((((IT) & (u8)0xE0) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (u8)0x60) == 0x00) && ((IT) != 0x00))
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_CSS ((uint8_t)0x80)
/* USB clock source */
#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00)
#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01)
#ifndef STM32F10X_CL
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
#else
#define RCC_IT_PLL2RDY ((uint8_t)0x20)
#define RCC_IT_PLL3RDY ((uint8_t)0x40)
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
#endif /* STM32F10X_CL */
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
/**
* @}
*/
#ifndef STM32F10X_CL
/** @defgroup USB_Device_clock_source
* @{
*/
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
#else
/** @defgroup USB_OTG_FS_clock_source
* @{
*/
#define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)
#define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)
/* ADC clock source */
#define RCC_PCLK2_Div2 ((u32)0x00000000)
#define RCC_PCLK2_Div4 ((u32)0x00004000)
#define RCC_PCLK2_Div6 ((u32)0x00008000)
#define RCC_PCLK2_Div8 ((u32)0x0000C000)
#define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
#endif /* STM32F10X_CL */
/**
* @}
*/
#ifdef STM32F10X_CL
/** @defgroup I2S2_clock_source
* @{
*/
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
#define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
/**
* @}
*/
/** @defgroup I2S3_clock_source
* @{
*/
#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
#define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
/**
* @}
*/
#endif /* STM32F10X_CL */
/** @defgroup ADC_clock_source
* @{
*/
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
/**
* @}
*/
/* LSE configuration */
#define RCC_LSE_OFF ((u8)0x00)
#define RCC_LSE_ON ((u8)0x01)
#define RCC_LSE_Bypass ((u8)0x04)
/** @defgroup LSE_configuration
* @{
*/
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_Bypass ((uint8_t)0x04)
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_Bypass))
/**
* @}
*/
/* RTC clock source */
#define RCC_RTCCLKSource_LSE ((u32)0x00000100)
#define RCC_RTCCLKSource_LSI ((u32)0x00000200)
#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300)
/** @defgroup RTC_clock_source
* @{
*/
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
((SOURCE) == RCC_RTCCLKSource_LSI) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
/**
* @}
*/
/* AHB peripheral */
#define RCC_AHBPeriph_DMA1 ((u32)0x00000001)
#define RCC_AHBPeriph_DMA2 ((u32)0x00000002)
#define RCC_AHBPeriph_SRAM ((u32)0x00000004)
#define RCC_AHBPeriph_FLITF ((u32)0x00000010)
#define RCC_AHBPeriph_CRC ((u32)0x00000040)
#define RCC_AHBPeriph_FSMC ((u32)0x00000100)
#define RCC_AHBPeriph_SDIO ((u32)0x00000400)
/** @defgroup AHB_peripheral
* @{
*/
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
/* APB2 peripheral */
#define RCC_APB2Periph_AFIO ((u32)0x00000001)
#define RCC_APB2Periph_GPIOA ((u32)0x00000004)
#define RCC_APB2Periph_GPIOB ((u32)0x00000008)
#define RCC_APB2Periph_GPIOC ((u32)0x00000010)
#define RCC_APB2Periph_GPIOD ((u32)0x00000020)
#define RCC_APB2Periph_GPIOE ((u32)0x00000040)
#define RCC_APB2Periph_GPIOF ((u32)0x00000080)
#define RCC_APB2Periph_GPIOG ((u32)0x00000100)
#define RCC_APB2Periph_ADC1 ((u32)0x00000200)
#define RCC_APB2Periph_ADC2 ((u32)0x00000400)
#define RCC_APB2Periph_TIM1 ((u32)0x00000800)
#define RCC_APB2Periph_SPI1 ((u32)0x00001000)
#define RCC_APB2Periph_TIM8 ((u32)0x00002000)
#define RCC_APB2Periph_USART1 ((u32)0x00004000)
#define RCC_APB2Periph_ADC3 ((u32)0x00008000)
#define RCC_APB2Periph_ALL ((u32)0x0000FFFD)
#ifndef STM32F10X_CL
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
#else
#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
#endif /* STM32F10X_CL */
/**
* @}
*/
/** @defgroup APB2_peripheral
* @{
*/
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/* APB1 peripheral */
#define RCC_APB1Periph_TIM2 ((u32)0x00000001)
#define RCC_APB1Periph_TIM3 ((u32)0x00000002)
#define RCC_APB1Periph_TIM4 ((u32)0x00000004)
#define RCC_APB1Periph_TIM5 ((u32)0x00000008)
#define RCC_APB1Periph_TIM6 ((u32)0x00000010)
#define RCC_APB1Periph_TIM7 ((u32)0x00000020)
#define RCC_APB1Periph_WWDG ((u32)0x00000800)
#define RCC_APB1Periph_SPI2 ((u32)0x00004000)
#define RCC_APB1Periph_SPI3 ((u32)0x00008000)
#define RCC_APB1Periph_USART2 ((u32)0x00020000)
#define RCC_APB1Periph_USART3 ((u32)0x00040000)
#define RCC_APB1Periph_UART4 ((u32)0x00080000)
#define RCC_APB1Periph_UART5 ((u32)0x00100000)
#define RCC_APB1Periph_I2C1 ((u32)0x00200000)
#define RCC_APB1Periph_I2C2 ((u32)0x00400000)
#define RCC_APB1Periph_USB ((u32)0x00800000)
#define RCC_APB1Periph_CAN ((u32)0x02000000)
#define RCC_APB1Periph_BKP ((u32)0x08000000)
#define RCC_APB1Periph_PWR ((u32)0x10000000)
#define RCC_APB1Periph_DAC ((u32)0x20000000)
#define RCC_APB1Periph_ALL ((u32)0x3AFEC83F)
/** @defgroup APB1_peripheral
* @{
*/
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00))
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC10137C0) == 0x00) && ((PERIPH) != 0x00))
/* Clock source to output on MCO pin */
#define RCC_MCO_NoClock ((u8)0x00)
#define RCC_MCO_SYSCLK ((u8)0x04)
#define RCC_MCO_HSI ((u8)0x05)
#define RCC_MCO_HSE ((u8)0x06)
#define RCC_MCO_PLLCLK_Div2 ((u8)0x07)
/**
* @}
*/
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
((MCO) == RCC_MCO_PLLCLK_Div2))
/** @defgroup Clock_source_to_output_on_MCO_pin
* @{
*/
/* RCC Flag */
#define RCC_FLAG_HSIRDY ((u8)0x21)
#define RCC_FLAG_HSERDY ((u8)0x31)
#define RCC_FLAG_PLLRDY ((u8)0x39)
#define RCC_FLAG_LSERDY ((u8)0x41)
#define RCC_FLAG_LSIRDY ((u8)0x61)
#define RCC_FLAG_PINRST ((u8)0x7A)
#define RCC_FLAG_PORRST ((u8)0x7B)
#define RCC_FLAG_SFTRST ((u8)0x7C)
#define RCC_FLAG_IWDGRST ((u8)0x7D)
#define RCC_FLAG_WWDGRST ((u8)0x7E)
#define RCC_FLAG_LPWRRST ((u8)0x7F)
#define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
#define RCC_MCO_HSI ((uint8_t)0x05)
#define RCC_MCO_HSE ((uint8_t)0x06)
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
((FLAG) == RCC_FLAG_LPWRRST))
#ifndef STM32F10X_CL
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
((MCO) == RCC_MCO_PLLCLK_Div2))
#else
#define RCC_MCO_PLL2CLK ((uint8_t)0x08)
#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
#define RCC_MCO_XT1 ((uint8_t)0x0A)
#define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
((MCO) == RCC_MCO_PLL3CLK))
#endif /* STM32F10X_CL */
/**
* @}
*/
/** @defgroup RCC_Flag
* @{
*/
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#ifndef STM32F10X_CL
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
((FLAG) == RCC_FLAG_LPWRRST))
#else
#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
((FLAG) == RCC_FLAG_LPWRRST))
#endif /* STM32F10X_CL */
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/**
* @}
*/
/**
* @}
*/
/** @defgroup RCC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup RCC_Exported_Functions
* @{
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void RCC_DeInit(void);
void RCC_HSEConfig(u32 RCC_HSE);
void RCC_HSEConfig(uint32_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource);
u8 RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(u32 RCC_SYSCLK);
void RCC_PCLK1Config(u32 RCC_HCLK);
void RCC_PCLK2Config(u32 RCC_HCLK);
void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState);
void RCC_USBCLKConfig(u32 RCC_USBCLKSource);
void RCC_ADCCLKConfig(u32 RCC_PCLK2);
void RCC_LSEConfig(u8 RCC_LSE);
#ifdef STM32F10X_CL
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
void RCC_PLL2Cmd(FunctionalState NewState);
void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
void RCC_PLL3Cmd(FunctionalState NewState);
#endif /* STM32F10X_CL */
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
#ifndef STM32F10X_CL
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
#else
void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
#endif /* STM32F10X_CL */
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
#ifdef STM32F10X_CL
void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
#endif /* STM32F10X_CL */
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
#ifdef STM32F10X_CL
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
#endif /* STM32F10X_CL */
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(u8 RCC_MCO);
FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG);
void RCC_MCOConfig(uint8_t RCC_MCO);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(u8 RCC_IT);
void RCC_ClearITPendingBit(u8 RCC_IT);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_RCC_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

156
src/platform/stm32/FWLib/library/inc/stm32f10x_rtc.h
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@ -1,70 +1,134 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_rtc.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* RTC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_rtc.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RTC_H
#define __STM32F10x_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#include "stm32f10x.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* RTC interrupts define -----------------------------------------------------*/
#define RTC_IT_OW ((u16)0x0004) /* Overflow interrupt */
#define RTC_IT_ALR ((u16)0x0002) /* Alarm interrupt */
#define RTC_IT_SEC ((u16)0x0001) /* Second interrupt */
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
#define IS_RTC_IT(IT) ((((IT) & (u16)0xFFF8) == 0x00) && ((IT) != 0x00))
/** @addtogroup RTC
* @{
*/
/** @defgroup RTC_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Constants
* @{
*/
/** @defgroup RTC_interrupts_define
* @{
*/
#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
((IT) == RTC_IT_SEC))
/* RTC interrupts flags ------------------------------------------------------*/
#define RTC_FLAG_RTOFF ((u16)0x0020) /* RTC Operation OFF flag */
#define RTC_FLAG_RSF ((u16)0x0008) /* Registers Synchronized flag */
#define RTC_FLAG_OW ((u16)0x0004) /* Overflow flag */
#define RTC_FLAG_ALR ((u16)0x0002) /* Alarm flag */
#define RTC_FLAG_SEC ((u16)0x0001) /* Second flag */
/**
* @}
*/
#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFFF0) == 0x00) && ((FLAG) != 0x00))
/** @defgroup RTC_interrupts_flags
* @{
*/
#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
((FLAG) == RTC_FLAG_SEC))
#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState);
/**
* @}
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Functions
* @{
*/
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
void RTC_EnterConfigMode(void);
void RTC_ExitConfigMode(void);
u32 RTC_GetCounter(void);
void RTC_SetCounter(u32 CounterValue);
void RTC_SetPrescaler(u32 PrescalerValue);
void RTC_SetAlarm(u32 AlarmValue);
u32 RTC_GetDivider(void);
uint32_t RTC_GetCounter(void);
void RTC_SetCounter(uint32_t CounterValue);
void RTC_SetPrescaler(uint32_t PrescalerValue);
void RTC_SetAlarm(uint32_t AlarmValue);
uint32_t RTC_GetDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchro(void);
FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG);
void RTC_ClearFlag(u16 RTC_FLAG);
ITStatus RTC_GetITStatus(u16 RTC_IT);
void RTC_ClearITPendingBit(u16 RTC_IT);
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
void RTC_ClearFlag(uint16_t RTC_FLAG);
ITStatus RTC_GetITStatus(uint16_t RTC_IT);
void RTC_ClearITPendingBit(uint16_t RTC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_RTC_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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src/platform/stm32/FWLib/library/inc/stm32f10x_sdio.h
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@ -1,181 +1,316 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_sdio.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* SDIO firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_sdio.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SDIO_H
#define __STM32F10x_SDIO_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup SDIO
* @{
*/
/** @defgroup SDIO_Exported_Types
* @{
*/
/* Exported types ------------------------------------------------------------*/
typedef struct
{
u8 SDIO_ClockDiv;
u32 SDIO_ClockEdge;
u32 SDIO_ClockBypass;
u32 SDIO_ClockPowerSave;
u32 SDIO_BusWide;
u32 SDIO_HardwareFlowControl;
uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref SDIO_Clock_Edge */
uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
enabled or disabled.
This parameter can be a value of @ref SDIO_Clock_Bypass */
uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
disabled when the bus is idle.
This parameter can be a value of @ref SDIO_Clock_Power_Save */
uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
This parameter can be a value of @ref SDIO_Bus_Wide */
uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
This parameter can be a value between 0x00 and 0xFF. */
} SDIO_InitTypeDef;
typedef struct
{
u32 SDIO_Argument;
u32 SDIO_CmdIndex;
u32 SDIO_Response;
u32 SDIO_Wait;
u32 SDIO_CPSM;
uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
to a card as part of a command message. If a command
contains an argument, it must be loaded into this register
before writing the command to the command register */
uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
This parameter can be a value of @ref SDIO_Response_Type */
uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
is enabled or disabled.
This parameter can be a value of @ref SDIO_CPSM_State */
} SDIO_CmdInitTypeDef;
typedef struct
{
u32 SDIO_DataTimeOut;
u32 SDIO_DataLength;
u32 SDIO_DataBlockSize;
u32 SDIO_TransferDir;
u32 SDIO_TransferMode;
u32 SDIO_DPSM;
uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
This parameter can be a value of @ref SDIO_Data_Block_Size */
uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
is a read or write.
This parameter can be a value of @ref SDIO_Transfer_Direction */
uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
This parameter can be a value of @ref SDIO_Transfer_Type */
uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
is enabled or disabled.
This parameter can be a value of @ref SDIO_DPSM_State */
} SDIO_DataInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* SDIO Clock Edge -----------------------------------------------------------*/
#define SDIO_ClockEdge_Rising ((u32)0x00000000)
#define SDIO_ClockEdge_Falling ((u32)0x00002000)
/**
* @}
*/
/** @defgroup SDIO_Exported_Constants
* @{
*/
/** @defgroup SDIO_Clock_Edge
* @{
*/
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
((EDGE) == SDIO_ClockEdge_Falling))
/* SDIO Clock Bypass ----------------------------------------------------------*/
#define SDIO_ClockBypass_Disable ((u32)0x00000000)
#define SDIO_ClockBypass_Enable ((u32)0x00000400)
/**
* @}
*/
/** @defgroup SDIO_Clock_Bypass
* @{
*/
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
((BYPASS) == SDIO_ClockBypass_Enable))
((BYPASS) == SDIO_ClockBypass_Enable))
/**
* @}
*/
/* SDIO Clock Power Save ----------------------------------------------------*/
#define SDIO_ClockPowerSave_Disable ((u32)0x00000000)
#define SDIO_ClockPowerSave_Enable ((u32)0x00000200)
/** @defgroup SDIO_Clock_Power_Save
* @{
*/
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
((SAVE) == SDIO_ClockPowerSave_Enable))
/**
* @}
*/
/* SDIO Bus Wide -------------------------------------------------------------*/
#define SDIO_BusWide_1b ((u32)0x00000000)
#define SDIO_BusWide_4b ((u32)0x00000800)
#define SDIO_BusWide_8b ((u32)0x00001000)
/** @defgroup SDIO_Bus_Wide
* @{
*/
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
((WIDE) == SDIO_BusWide_8b))
/* SDIO Hardware Flow Control -----------------------------------------------*/
#define SDIO_HardwareFlowControl_Disable ((u32)0x00000000)
#define SDIO_HardwareFlowControl_Enable ((u32)0x00004000)
/**
* @}
*/
/** @defgroup SDIO_Hardware_Flow_Control
* @{
*/
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
((CONTROL) == SDIO_HardwareFlowControl_Enable))
/* SDIO Power State ----------------------------------------------------------*/
#define SDIO_PowerState_OFF ((u32)0x00000000)
#define SDIO_PowerState_ON ((u32)0x00000003)
/**
* @}
*/
/** @defgroup SDIO_Power_State
* @{
*/
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
/**
* @}
*/
/* SDIO Interrupt soucres ----------------------------------------------------*/
#define SDIO_IT_CCRCFAIL ((u32)0x00000001)
#define SDIO_IT_DCRCFAIL ((u32)0x00000002)
#define SDIO_IT_CTIMEOUT ((u32)0x00000004)
#define SDIO_IT_DTIMEOUT ((u32)0x00000008)
#define SDIO_IT_TXUNDERR ((u32)0x00000010)
#define SDIO_IT_RXOVERR ((u32)0x00000020)
#define SDIO_IT_CMDREND ((u32)0x00000040)
#define SDIO_IT_CMDSENT ((u32)0x00000080)
#define SDIO_IT_DATAEND ((u32)0x00000100)
#define SDIO_IT_STBITERR ((u32)0x00000200)
#define SDIO_IT_DBCKEND ((u32)0x00000400)
#define SDIO_IT_CMDACT ((u32)0x00000800)
#define SDIO_IT_TXACT ((u32)0x00001000)
#define SDIO_IT_RXACT ((u32)0x00002000)
#define SDIO_IT_TXFIFOHE ((u32)0x00004000)
#define SDIO_IT_RXFIFOHF ((u32)0x00008000)
#define SDIO_IT_TXFIFOF ((u32)0x00010000)
#define SDIO_IT_RXFIFOF ((u32)0x00020000)
#define SDIO_IT_TXFIFOE ((u32)0x00040000)
#define SDIO_IT_RXFIFOE ((u32)0x00080000)
#define SDIO_IT_TXDAVL ((u32)0x00100000)
#define SDIO_IT_RXDAVL ((u32)0x00200000)
#define SDIO_IT_SDIOIT ((u32)0x00400000)
#define SDIO_IT_CEATAEND ((u32)0x00800000)
#define IS_SDIO_IT(IT) ((((IT) & (u32)0xFF000000) == 0x00) && ((IT) != (u32)0x00))
/** @defgroup SDIO_Interrupt_soucres
* @{
*/
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SDIO_Command_Index
* @{
*/
/* SDIO Command Index -------------------------------------------------------*/
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
/**
* @}
*/
/* SDIO Response Type --------------------------------------------------------*/
#define SDIO_Response_No ((u32)0x00000000)
#define SDIO_Response_Short ((u32)0x00000040)
#define SDIO_Response_Long ((u32)0x000000C0)
/** @defgroup SDIO_Response_Type
* @{
*/
#define SDIO_Response_No ((uint32_t)0x00000000)
#define SDIO_Response_Short ((uint32_t)0x00000040)
#define SDIO_Response_Long ((uint32_t)0x000000C0)
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
((RESPONSE) == SDIO_Response_Short) || \
((RESPONSE) == SDIO_Response_Long))
/**
* @}
*/
/* SDIO Wait Interrupt State -------------------------------------------------*/
#define SDIO_Wait_No ((u32)0x00000000) /* SDIO No Wait, TimeOut is enabled */
#define SDIO_Wait_IT ((u32)0x00000100) /* SDIO Wait Interrupt Request */
#define SDIO_Wait_Pend ((u32)0x00000200) /* SDIO Wait End of transfer */
/** @defgroup SDIO_Wait_Interrupt_State
* @{
*/
#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
((WAIT) == SDIO_Wait_Pend))
/**
* @}
*/
/* SDIO CPSM State -----------------------------------------------------------*/
#define SDIO_CPSM_Disable ((u32)0x00000000)
#define SDIO_CPSM_Enable ((u32)0x00000400)
/** @defgroup SDIO_CPSM_State
* @{
*/
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
/**
* @}
*/
/* SDIO Response Registers ---------------------------------------------------*/
#define SDIO_RESP1 ((u32)0x00000000)
#define SDIO_RESP2 ((u32)0x00000004)
#define SDIO_RESP3 ((u32)0x00000008)
#define SDIO_RESP4 ((u32)0x0000000C)
/** @defgroup SDIO_Response_Registers
* @{
*/
#define SDIO_RESP1 ((uint32_t)0x00000000)
#define SDIO_RESP2 ((uint32_t)0x00000004)
#define SDIO_RESP3 ((uint32_t)0x00000008)
#define SDIO_RESP4 ((uint32_t)0x0000000C)
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
/**
* @}
*/
/** @defgroup SDIO_Data_Length
* @{
*/
/* SDIO Data Length ----------------------------------------------------------*/
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
/**
* @}
*/
/* SDIO Data Block Size ------------------------------------------------------*/
#define SDIO_DataBlockSize_1b ((u32)0x00000000)
#define SDIO_DataBlockSize_2b ((u32)0x00000010)
#define SDIO_DataBlockSize_4b ((u32)0x00000020)
#define SDIO_DataBlockSize_8b ((u32)0x00000030)
#define SDIO_DataBlockSize_16b ((u32)0x00000040)
#define SDIO_DataBlockSize_32b ((u32)0x00000050)
#define SDIO_DataBlockSize_64b ((u32)0x00000060)
#define SDIO_DataBlockSize_128b ((u32)0x00000070)
#define SDIO_DataBlockSize_256b ((u32)0x00000080)
#define SDIO_DataBlockSize_512b ((u32)0x00000090)
#define SDIO_DataBlockSize_1024b ((u32)0x000000A0)
#define SDIO_DataBlockSize_2048b ((u32)0x000000B0)
#define SDIO_DataBlockSize_4096b ((u32)0x000000C0)
#define SDIO_DataBlockSize_8192b ((u32)0x000000D0)
#define SDIO_DataBlockSize_16384b ((u32)0x000000E0)
/** @defgroup SDIO_Data_Block_Size
* @{
*/
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
((SIZE) == SDIO_DataBlockSize_2b) || \
((SIZE) == SDIO_DataBlockSize_4b) || \
@ -191,53 +326,73 @@ typedef struct
((SIZE) == SDIO_DataBlockSize_4096b) || \
((SIZE) == SDIO_DataBlockSize_8192b) || \
((SIZE) == SDIO_DataBlockSize_16384b))
/**
* @}
*/
/* SDIO Transfer Direction ---------------------------------------------------*/
#define SDIO_TransferDir_ToCard ((u32)0x00000000)
#define SDIO_TransferDir_ToSDIO ((u32)0x00000002)
/** @defgroup SDIO_Transfer_Direction
* @{
*/
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
((DIR) == SDIO_TransferDir_ToSDIO))
((DIR) == SDIO_TransferDir_ToSDIO))
/**
* @}
*/
/* SDIO Transfer Type --------------------------------------------------------*/
#define SDIO_TransferMode_Block ((u32)0x00000000)
#define SDIO_TransferMode_Stream ((u32)0x00000004)
/** @defgroup SDIO_Transfer_Type
* @{
*/
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
((MODE) == SDIO_TransferMode_Block))
((MODE) == SDIO_TransferMode_Block))
/**
* @}
*/
/* SDIO DPSM State -----------------------------------------------------------*/
#define SDIO_DPSM_Disable ((u32)0x00000000)
#define SDIO_DPSM_Enable ((u32)0x00000001)
/** @defgroup SDIO_DPSM_State
* @{
*/
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
/**
* @}
*/
/* SDIO Flags ----------------------------------------------------------------*/
#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001)
#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002)
#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004)
#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008)
#define SDIO_FLAG_TXUNDERR ((u32)0x00000010)
#define SDIO_FLAG_RXOVERR ((u32)0x00000020)
#define SDIO_FLAG_CMDREND ((u32)0x00000040)
#define SDIO_FLAG_CMDSENT ((u32)0x00000080)
#define SDIO_FLAG_DATAEND ((u32)0x00000100)
#define SDIO_FLAG_STBITERR ((u32)0x00000200)
#define SDIO_FLAG_DBCKEND ((u32)0x00000400)
#define SDIO_FLAG_CMDACT ((u32)0x00000800)
#define SDIO_FLAG_TXACT ((u32)0x00001000)
#define SDIO_FLAG_RXACT ((u32)0x00002000)
#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000)
#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000)
#define SDIO_FLAG_TXFIFOF ((u32)0x00010000)
#define SDIO_FLAG_RXFIFOF ((u32)0x00020000)
#define SDIO_FLAG_TXFIFOE ((u32)0x00040000)
#define SDIO_FLAG_RXFIFOE ((u32)0x00080000)
#define SDIO_FLAG_TXDAVL ((u32)0x00100000)
#define SDIO_FLAG_RXDAVL ((u32)0x00200000)
#define SDIO_FLAG_SDIOIT ((u32)0x00400000)
#define SDIO_FLAG_CEATAEND ((u32)0x00800000)
/** @defgroup SDIO_Flags
* @{
*/
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
@ -263,7 +418,7 @@ typedef struct
((FLAG) == SDIO_FLAG_SDIOIT) || \
((FLAG) == SDIO_FLAG_CEATAEND))
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFF3FF800) == 0x00) && ((FLAG) != (u32)0x00))
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
((IT) == SDIO_IT_DCRCFAIL) || \
@ -290,48 +445,86 @@ typedef struct
((IT) == SDIO_IT_SDIOIT) || \
((IT) == SDIO_IT_CEATAEND))
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (u32)0xFF3FF800) == 0x00) && ((IT) != (u32)0x00))
/* SDIO Read Wait Mode -------------------------------------------------------*/
#define SDIO_ReadWaitMode_CLK ((u32)0x00000000)
#define SDIO_ReadWaitMode_DATA2 ((u32)0x00000001)
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SDIO_Read_Wait_Mode
* @{
*/
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
((MODE) == SDIO_ReadWaitMode_DATA2))
((MODE) == SDIO_ReadWaitMode_DATA2))
/**
* @}
*/
/**
* @}
*/
/** @defgroup SDIO_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup SDIO_Exported_Functions
* @{
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void SDIO_DeInit(void);
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_ClockCmd(FunctionalState NewState);
void SDIO_SetPowerState(u32 SDIO_PowerState);
u32 SDIO_GetPowerState(void);
void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState);
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
uint32_t SDIO_GetPowerState(void);
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
void SDIO_DMACmd(FunctionalState NewState);
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
u8 SDIO_GetCommandResponse(void);
u32 SDIO_GetResponse(u32 SDIO_RESP);
uint8_t SDIO_GetCommandResponse(void);
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
u32 SDIO_GetDataCounter(void);
u32 SDIO_ReadData(void);
void SDIO_WriteData(u32 Data);
u32 SDIO_GetFIFOCount(void);
uint32_t SDIO_GetDataCounter(void);
uint32_t SDIO_ReadData(void);
void SDIO_WriteData(uint32_t Data);
uint32_t SDIO_GetFIFOCount(void);
void SDIO_StartSDIOReadWait(FunctionalState NewState);
void SDIO_StopSDIOReadWait(FunctionalState NewState);
void SDIO_SetSDIOReadWaitMode(u32 SDIO_ReadWaitMode);
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
void SDIO_SetSDIOOperation(FunctionalState NewState);
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
void SDIO_CommandCompletionCmd(FunctionalState NewState);
void SDIO_CEATAITCmd(FunctionalState NewState);
void SDIO_SendCEATACmd(FunctionalState NewState);
FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG);
void SDIO_ClearFlag(u32 SDIO_FLAG);
ITStatus SDIO_GetITStatus(u32 SDIO_IT);
void SDIO_ClearITPendingBit(u32 SDIO_IT);
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_SDIO_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

511
src/platform/stm32/FWLib/library/inc/stm32f10x_spi.h
View File

@ -1,117 +1,213 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_spi.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* SPI firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_spi.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the SPI firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SPI_H
#define __STM32F10x_SPI_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/** @defgroup SPI_Exported_Types
* @{
*/
/**
* @brief SPI Init structure definition
*/
/* Exported types ------------------------------------------------------------*/
/* SPI Init structure definition */
typedef struct
{
u16 SPI_Direction;
u16 SPI_Mode;
u16 SPI_DataSize;
u16 SPI_CPOL;
u16 SPI_CPHA;
u16 SPI_NSS;
u16 SPI_BaudRatePrescaler;
u16 SPI_FirstBit;
u16 SPI_CRCPolynomial;
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be any combination of @ref SPI_data_direction */
uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
This parameter can be any combination of @ref SPI_mode */
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
This parameter can be any combination of @ref SPI_data_size */
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
This parameter can be any combination of @ref SPI_Clock_Polarity */
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
This parameter can be any combination of @ref SPI_Clock_Phase */
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be any combination of @ref SPI_Slave_Select_management */
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be any combination of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be any combination of @ref SPI_MSB_LSB_transmission */
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
}SPI_InitTypeDef;
/* I2S Init structure definition */
/**
* @brief I2S Init structure definition
*/
typedef struct
{
u16 I2S_Mode;
u16 I2S_Standard;
u16 I2S_DataFormat;
u16 I2S_MCLKOutput;
u16 I2S_AudioFreq;
u16 I2S_CPOL;
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
This parameter can be any combination of @ref I2S_Mode */
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be any combination of @ref I2S_Standard */
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be any combination of @ref I2S_Data_Format */
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be any combination of @ref I2S_MCLK_Output */
uint16_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be any combination of @ref I2S_Audio_Frequency */
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be any combination of @ref I2S_Clock_Polarity */
}I2S_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/**
* @}
*/
#define IS_SPI_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI1_BASE) || \
((*(u32*)&(PERIPH)) == SPI2_BASE) || \
((*(u32*)&(PERIPH)) == SPI3_BASE))
/** @defgroup SPI_Exported_Constants
* @{
*/
#define IS_SPI_23_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI2_BASE) || \
((*(u32*)&(PERIPH)) == SPI3_BASE))
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
((PERIPH) == SPI2) || \
((PERIPH) == SPI3))
/* SPI data direction mode */
#define SPI_Direction_2Lines_FullDuplex ((u16)0x0000)
#define SPI_Direction_2Lines_RxOnly ((u16)0x0400)
#define SPI_Direction_1Line_Rx ((u16)0x8000)
#define SPI_Direction_1Line_Tx ((u16)0xC000)
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
((PERIPH) == SPI3))
/** @defgroup SPI_data_direction
* @{
*/
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
((MODE) == SPI_Direction_2Lines_RxOnly) || \
((MODE) == SPI_Direction_1Line_Rx) || \
((MODE) == SPI_Direction_1Line_Tx))
/**
* @}
*/
/* SPI master/slave mode */
#define SPI_Mode_Master ((u16)0x0104)
#define SPI_Mode_Slave ((u16)0x0000)
/** @defgroup SPI_mode
* @{
*/
#define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
((MODE) == SPI_Mode_Slave))
/**
* @}
*/
/* SPI data size */
#define SPI_DataSize_16b ((u16)0x0800)
#define SPI_DataSize_8b ((u16)0x0000)
/** @defgroup SPI_data_size
* @{
*/
#define SPI_DataSize_16b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000)
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
((DATASIZE) == SPI_DataSize_8b))
/**
* @}
*/
/* SPI Clock Polarity */
#define SPI_CPOL_Low ((u16)0x0000)
#define SPI_CPOL_High ((u16)0x0002)
/** @defgroup SPI_Clock_Polarity
* @{
*/
#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002)
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
((CPOL) == SPI_CPOL_High))
/**
* @}
*/
/* SPI Clock Phase */
#define SPI_CPHA_1Edge ((u16)0x0000)
#define SPI_CPHA_2Edge ((u16)0x0001)
/** @defgroup SPI_Clock_Phase
* @{
*/
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
((CPHA) == SPI_CPHA_2Edge))
/**
* @}
*/
/* SPI Slave Select management */
#define SPI_NSS_Soft ((u16)0x0200)
#define SPI_NSS_Hard ((u16)0x0000)
/** @defgroup SPI_Slave_Select_management
* @{
*/
#define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
((NSS) == SPI_NSS_Hard))
((NSS) == SPI_NSS_Hard))
/**
* @}
*/
/* SPI BaudRate Prescaler */
#define SPI_BaudRatePrescaler_2 ((u16)0x0000)
#define SPI_BaudRatePrescaler_4 ((u16)0x0008)
#define SPI_BaudRatePrescaler_8 ((u16)0x0010)
#define SPI_BaudRatePrescaler_16 ((u16)0x0018)
#define SPI_BaudRatePrescaler_32 ((u16)0x0020)
#define SPI_BaudRatePrescaler_64 ((u16)0x0028)
#define SPI_BaudRatePrescaler_128 ((u16)0x0030)
#define SPI_BaudRatePrescaler_256 ((u16)0x0038)
/** @defgroup SPI_BaudRate_Prescaler
* @{
*/
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
@ -120,146 +216,236 @@ typedef struct
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
((PRESCALER) == SPI_BaudRatePrescaler_256))
/**
* @}
*/
/* SPI MSB/LSB transmission */
#define SPI_FirstBit_MSB ((u16)0x0000)
#define SPI_FirstBit_LSB ((u16)0x0080)
/** @defgroup SPI_MSB_LSB_transmission
* @{
*/
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
((BIT) == SPI_FirstBit_LSB))
/**
* @}
*/
/* I2S Mode */
#define I2S_Mode_SlaveTx ((u16)0x0000)
#define I2S_Mode_SlaveRx ((u16)0x0100)
#define I2S_Mode_MasterTx ((u16)0x0200)
#define I2S_Mode_MasterRx ((u16)0x0300)
/** @defgroup I2S_Mode
* @{
*/
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
((MODE) == I2S_Mode_SlaveRx) || \
((MODE) == I2S_Mode_MasterTx) || \
((MODE) == I2S_Mode_MasterRx) )
/**
* @}
*/
/* I2S Standard */
#define I2S_Standard_Phillips ((u16)0x0000)
#define I2S_Standard_MSB ((u16)0x0010)
#define I2S_Standard_LSB ((u16)0x0020)
#define I2S_Standard_PCMShort ((u16)0x0030)
#define I2S_Standard_PCMLong ((u16)0x00B0)
/** @defgroup I2S_Standard
* @{
*/
#define I2S_Standard_Phillips ((uint16_t)0x0000)
#define I2S_Standard_MSB ((uint16_t)0x0010)
#define I2S_Standard_LSB ((uint16_t)0x0020)
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
((STANDARD) == I2S_Standard_MSB) || \
((STANDARD) == I2S_Standard_LSB) || \
((STANDARD) == I2S_Standard_PCMShort) || \
((STANDARD) == I2S_Standard_PCMLong))
/**
* @}
*/
/* I2S Data Format */
#define I2S_DataFormat_16b ((u16)0x0000)
#define I2S_DataFormat_16bextended ((u16)0x0001)
#define I2S_DataFormat_24b ((u16)0x0003)
#define I2S_DataFormat_32b ((u16)0x0005)
/** @defgroup I2S_Data_Format
* @{
*/
#define I2S_DataFormat_16b ((uint16_t)0x0000)
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define I2S_DataFormat_24b ((uint16_t)0x0003)
#define I2S_DataFormat_32b ((uint16_t)0x0005)
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
((FORMAT) == I2S_DataFormat_16bextended) || \
((FORMAT) == I2S_DataFormat_24b) || \
((FORMAT) == I2S_DataFormat_32b))
/**
* @}
*/
/* I2S MCLK Output */
#define I2S_MCLKOutput_Enable ((u16)0x0200)
#define I2S_MCLKOutput_Disable ((u16)0x0000)
/** @defgroup I2S_MCLK_Output
* @{
*/
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
((OUTPUT) == I2S_MCLKOutput_Disable))
/**
* @}
*/
/* I2S Audio Frequency */
#define I2S_AudioFreq_48k ((u16)48000)
#define I2S_AudioFreq_44k ((u16)44100)
#define I2S_AudioFreq_22k ((u16)22050)
#define I2S_AudioFreq_16k ((u16)16000)
#define I2S_AudioFreq_8k ((u16)8000)
#define I2S_AudioFreq_Default ((u16)2)
/** @defgroup I2S_Audio_Frequency
* @{
*/
#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_48k) || \
#define I2S_AudioFreq_96k ((uint16_t)96000)
#define I2S_AudioFreq_48k ((uint16_t)48000)
#define I2S_AudioFreq_44k ((uint16_t)44100)
#define I2S_AudioFreq_32k ((uint16_t)32000)
#define I2S_AudioFreq_22k ((uint16_t)22050)
#define I2S_AudioFreq_16k ((uint16_t)16000)
#define I2S_AudioFreq_11k ((uint16_t)11025)
#define I2S_AudioFreq_8k ((uint16_t)8000)
#define I2S_AudioFreq_Default ((uint16_t)2)
#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_96k) || \
((FREQ) == I2S_AudioFreq_48k) || \
((FREQ) == I2S_AudioFreq_44k) || \
((FREQ) == I2S_AudioFreq_32k) || \
((FREQ) == I2S_AudioFreq_22k) || \
((FREQ) == I2S_AudioFreq_16k) || \
((FREQ) == I2S_AudioFreq_11k) || \
((FREQ) == I2S_AudioFreq_8k) || \
((FREQ) == I2S_AudioFreq_Default))
/**
* @}
*/
/* I2S Clock Polarity */
#define I2S_CPOL_Low ((u16)0x0000)
#define I2S_CPOL_High ((u16)0x0008)
/** @defgroup I2S_Clock_Polarity
* @{
*/
#define I2S_CPOL_Low ((uint16_t)0x0000)
#define I2S_CPOL_High ((uint16_t)0x0008)
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
((CPOL) == I2S_CPOL_High))
/**
* @}
*/
/* SPI_I2S DMA transfer requests */
#define SPI_I2S_DMAReq_Tx ((u16)0x0002)
#define SPI_I2S_DMAReq_Rx ((u16)0x0001)
/** @defgroup SPI_I2S_DMA_transfer_requests
* @{
*/
#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
/**
* @}
*/
/* SPI NSS internal software mangement */
#define SPI_NSSInternalSoft_Set ((u16)0x0100)
#define SPI_NSSInternalSoft_Reset ((u16)0xFEFF)
/** @defgroup SPI_NSS_internal_software_mangement
* @{
*/
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
((INTERNAL) == SPI_NSSInternalSoft_Reset))
/**
* @}
*/
/* SPI CRC Transmit/Receive */
#define SPI_CRC_Tx ((u8)0x00)
#define SPI_CRC_Rx ((u8)0x01)
/** @defgroup SPI_CRC_Transmit_Receive
* @{
*/
#define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_CRC_Rx ((uint8_t)0x01)
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
/**
* @}
*/
/* SPI direction transmit/receive */
#define SPI_Direction_Rx ((u16)0xBFFF)
#define SPI_Direction_Tx ((u16)0x4000)
/** @defgroup SPI_direction_transmit_receive
* @{
*/
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_Direction_Tx ((uint16_t)0x4000)
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
((DIRECTION) == SPI_Direction_Tx))
/**
* @}
*/
/* SPI_I2S interrupts definition */
#define SPI_I2S_IT_TXE ((u8)0x71)
#define SPI_I2S_IT_RXNE ((u8)0x60)
#define SPI_I2S_IT_ERR ((u8)0x50)
/** @defgroup SPI_I2S_interrupts_definition
* @{
*/
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
((IT) == SPI_I2S_IT_RXNE) || \
((IT) == SPI_I2S_IT_ERR))
#define SPI_I2S_IT_OVR ((u8)0x56)
#define SPI_IT_MODF ((u8)0x55)
#define SPI_IT_CRCERR ((u8)0x54)
#define I2S_IT_UDR ((u8)0x53)
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_IT_MODF ((uint8_t)0x55)
#define SPI_IT_CRCERR ((uint8_t)0x54)
#define I2S_IT_UDR ((uint8_t)0x53)
#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
/**
* @}
*/
/* SPI_I2S flags definition */
#define SPI_I2S_FLAG_RXNE ((u16)0x0001)
#define SPI_I2S_FLAG_TXE ((u16)0x0002)
#define I2S_FLAG_CHSIDE ((u16)0x0004)
#define I2S_FLAG_UDR ((u16)0x0008)
#define SPI_FLAG_CRCERR ((u16)0x0010)
#define SPI_FLAG_MODF ((u16)0x0020)
#define SPI_I2S_FLAG_OVR ((u16)0x0040)
#define SPI_I2S_FLAG_BSY ((u16)0x0080)
/** @defgroup SPI_I2S_flags_definition
* @{
*/
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define I2S_FLAG_UDR ((uint16_t)0x0008)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
/**
* @}
*/
/** @defgroup SPI_CRC_polynomial
* @{
*/
/* SPI CRC polynomial --------------------------------------------------------*/
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
/**
* @}
*/
/**
* @}
*/
/** @defgroup SPI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup SPI_Exported_Functions
* @{
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
@ -267,23 +453,38 @@ void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, u8 SPI_I2S_IT, FunctionalState NewState);
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, u16 SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_I2S_SendData(SPI_TypeDef* SPIx, u16 Data);
u16 SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft);
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC);
u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_I2S_IT);
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F10x_SPI_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

64
src/platform/stm32/FWLib/library/inc/stm32f10x_systick.h
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@ -1,64 +0,0 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_systick.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* SysTick firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SYSTICK_H
#define __STM32F10x_SYSTICK_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* SysTick clock source */
#define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((u32)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
/* SysTick counter state */
#define SysTick_Counter_Disable ((u32)0xFFFFFFFE)
#define SysTick_Counter_Enable ((u32)0x00000001)
#define SysTick_Counter_Clear ((u32)0x00000000)
#define IS_SYSTICK_COUNTER(COUNTER) (((COUNTER) == SysTick_Counter_Disable) || \
((COUNTER) == SysTick_Counter_Enable) || \
((COUNTER) == SysTick_Counter_Clear))
/* SysTick Flag */
#define SysTick_FLAG_COUNT ((u32)0x00000010)
#define SysTick_FLAG_SKEW ((u32)0x0000001E)
#define SysTick_FLAG_NOREF ((u32)0x0000001F)
#define IS_SYSTICK_FLAG(FLAG) (((FLAG) == SysTick_FLAG_COUNT) || \
((FLAG) == SysTick_FLAG_SKEW) || \
((FLAG) == SysTick_FLAG_NOREF))
#define IS_SYSTICK_RELOAD(RELOAD) (((RELOAD) > 0) && ((RELOAD) <= 0xFFFFFF))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void SysTick_CLKSourceConfig(u32 SysTick_CLKSource);
void SysTick_SetReload(u32 Reload);
void SysTick_CounterCmd(u32 SysTick_Counter);
void SysTick_ITConfig(FunctionalState NewState);
u32 SysTick_GetCounter(void);
FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG);
#endif /* __STM32F10x_SYSTICK_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

1184
src/platform/stm32/FWLib/library/inc/stm32f10x_tim.h
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80
src/platform/stm32/FWLib/library/inc/stm32f10x_type.h
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@ -1,80 +0,0 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_type.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the common data types used for the
* STM32F10x firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_TYPE_H
#define __STM32F10x_TYPE_H
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
typedef signed long s32;
typedef signed short s16;
typedef signed char s8;
typedef signed long const sc32; /* Read Only */
typedef signed short const sc16; /* Read Only */
typedef signed char const sc8; /* Read Only */
typedef volatile signed long vs32;
typedef volatile signed short vs16;
typedef volatile signed char vs8;
typedef volatile signed long const vsc32; /* Read Only */
typedef volatile signed short const vsc16; /* Read Only */
typedef volatile signed char const vsc8; /* Read Only */
typedef unsigned long u32;
typedef unsigned short u16;
typedef unsigned char u8;
typedef unsigned long const uc32; /* Read Only */
typedef unsigned short const uc16; /* Read Only */
typedef unsigned char const uc8; /* Read Only */
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
typedef volatile unsigned char vu8;
typedef volatile unsigned long const vuc32; /* Read Only */
typedef volatile unsigned short const vuc16; /* Read Only */
typedef volatile unsigned char const vuc8; /* Read Only */
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#define U8_MAX ((u8)255)
#define S8_MAX ((s8)127)
#define S8_MIN ((s8)-128)
#define U16_MAX ((u16)65535u)
#define S16_MAX ((s16)32767)
#define S16_MIN ((s16)-32768)
#define U32_MAX ((u32)4294967295uL)
#define S32_MAX ((s32)2147483647)
#define S32_MIN ((s32)-2147483648)
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
#endif /* __STM32F10x_TYPE_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

458
src/platform/stm32/FWLib/library/inc/stm32f10x_usart.h
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@ -1,253 +1,409 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_usart.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* USART firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_usart.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the USART
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_USART_H
#define __STM32F10x_USART_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* USART Init Structure definition */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup USART
* @{
*/
/** @defgroup USART_Exported_Types
* @{
*/
/**
* @brief USART Init Structure definition
*/
typedef struct
{
u32 USART_BaudRate;
u16 USART_WordLength;
u16 USART_StopBits;
u16 USART_Parity;
u16 USART_Mode;
u16 USART_HardwareFlowControl;
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint16_t USART_Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitTypeDef;
/* USART Clock Init Structure definition */
/**
* @brief USART Clock Init Structure definition
*/
typedef struct
{
u16 USART_Clock;
u16 USART_CPOL;
u16 USART_CPHA;
u16 USART_LastBit;
uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */
uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef;
/* Exported constants --------------------------------------------------------*/
#define IS_USART_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \
((*(u32*)&(PERIPH)) == USART2_BASE) || \
((*(u32*)&(PERIPH)) == USART3_BASE) || \
((*(u32*)&(PERIPH)) == UART4_BASE) || \
((*(u32*)&(PERIPH)) == UART5_BASE))
/**
* @}
*/
#define IS_USART_123_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \
((*(u32*)&(PERIPH)) == USART2_BASE) || \
((*(u32*)&(PERIPH)) == USART3_BASE))
/** @defgroup USART_Exported_Constants
* @{
*/
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3) || \
((PERIPH) == UART4) || \
((PERIPH) == UART5))
#define IS_USART_1234_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \
((*(u32*)&(PERIPH)) == USART2_BASE) || \
((*(u32*)&(PERIPH)) == USART3_BASE) || \
((*(u32*)&(PERIPH)) == UART4_BASE))
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3))
/* USART Word Length ---------------------------------------------------------*/
#define USART_WordLength_8b ((u16)0x0000)
#define USART_WordLength_9b ((u16)0x1000)
#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3) || \
((PERIPH) == UART4))
/** @defgroup USART_Word_Length
* @{
*/
#define USART_WordLength_8b ((uint16_t)0x0000)
#define USART_WordLength_9b ((uint16_t)0x1000)
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
((LENGTH) == USART_WordLength_9b))
/**
* @}
*/
/* USART Stop Bits -----------------------------------------------------------*/
#define USART_StopBits_1 ((u16)0x0000)
#define USART_StopBits_0_5 ((u16)0x1000)
#define USART_StopBits_2 ((u16)0x2000)
#define USART_StopBits_1_5 ((u16)0x3000)
/** @defgroup USART_Stop_Bits
* @{
*/
#define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_0_5 ((uint16_t)0x1000)
#define USART_StopBits_2 ((uint16_t)0x2000)
#define USART_StopBits_1_5 ((uint16_t)0x3000)
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
((STOPBITS) == USART_StopBits_0_5) || \
((STOPBITS) == USART_StopBits_2) || \
((STOPBITS) == USART_StopBits_1_5))
/* USART Parity --------------------------------------------------------------*/
#define USART_Parity_No ((u16)0x0000)
#define USART_Parity_Even ((u16)0x0400)
#define USART_Parity_Odd ((u16)0x0600)
/**
* @}
*/
/** @defgroup USART_Parity
* @{
*/
#define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400)
#define USART_Parity_Odd ((uint16_t)0x0600)
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
((PARITY) == USART_Parity_Even) || \
((PARITY) == USART_Parity_Odd))
/**
* @}
*/
/* USART Mode ----------------------------------------------------------------*/
#define USART_Mode_Rx ((u16)0x0004)
#define USART_Mode_Tx ((u16)0x0008)
#define IS_USART_MODE(MODE) ((((MODE) & (u16)0xFFF3) == 0x00) && ((MODE) != (u16)0x00))
/* USART Hardware Flow Control -----------------------------------------------*/
#define USART_HardwareFlowControl_None ((u16)0x0000)
#define USART_HardwareFlowControl_RTS ((u16)0x0100)
#define USART_HardwareFlowControl_CTS ((u16)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300)
/** @defgroup USART_Mode
* @{
*/
#define USART_Mode_Rx ((uint16_t)0x0004)
#define USART_Mode_Tx ((uint16_t)0x0008)
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
/**
* @}
*/
/** @defgroup USART_Hardware_Flow_Control
* @{
*/
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == USART_HardwareFlowControl_None) || \
((CONTROL) == USART_HardwareFlowControl_RTS) || \
((CONTROL) == USART_HardwareFlowControl_CTS) || \
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
/**
* @}
*/
#define IS_USART_PERIPH_HFC(PERIPH, HFC) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \
((*(u32*)&(PERIPH)) != UART5_BASE)) \
|| ((HFC) == USART_HardwareFlowControl_None))
/* USART Clock ---------------------------------------------------------------*/
#define USART_Clock_Disable ((u16)0x0000)
#define USART_Clock_Enable ((u16)0x0800)
/** @defgroup USART_Clock
* @{
*/
#define USART_Clock_Disable ((uint16_t)0x0000)
#define USART_Clock_Enable ((uint16_t)0x0800)
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
((CLOCK) == USART_Clock_Enable))
/**
* @}
*/
/* USART Clock Polarity ------------------------------------------------------*/
#define USART_CPOL_Low ((u16)0x0000)
#define USART_CPOL_High ((u16)0x0400)
/** @defgroup USART_Clock_Polarity
* @{
*/
#define USART_CPOL_Low ((uint16_t)0x0000)
#define USART_CPOL_High ((uint16_t)0x0400)
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
/* USART Clock Phase ---------------------------------------------------------*/
#define USART_CPHA_1Edge ((u16)0x0000)
#define USART_CPHA_2Edge ((u16)0x0200)
/**
* @}
*/
/** @defgroup USART_Clock_Phase
* @{
*/
#define USART_CPHA_1Edge ((uint16_t)0x0000)
#define USART_CPHA_2Edge ((uint16_t)0x0200)
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
/* USART Last Bit ------------------------------------------------------------*/
#define USART_LastBit_Disable ((u16)0x0000)
#define USART_LastBit_Enable ((u16)0x0100)
/**
* @}
*/
/** @defgroup USART_Last_Bit
* @{
*/
#define USART_LastBit_Disable ((uint16_t)0x0000)
#define USART_LastBit_Enable ((uint16_t)0x0100)
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
((LASTBIT) == USART_LastBit_Enable))
/**
* @}
*/
/* USART Interrupt definition ------------------------------------------------*/
#define USART_IT_PE ((u16)0x0028)
#define USART_IT_TXE ((u16)0x0727)
#define USART_IT_TC ((u16)0x0626)
#define USART_IT_RXNE ((u16)0x0525)
#define USART_IT_IDLE ((u16)0x0424)
#define USART_IT_LBD ((u16)0x0846)
#define USART_IT_CTS ((u16)0x096A)
#define USART_IT_ERR ((u16)0x0060)
#define USART_IT_ORE ((u16)0x0360)
#define USART_IT_NE ((u16)0x0260)
#define USART_IT_FE ((u16)0x0160)
/** @defgroup USART_Interrupt_definition
* @{
*/
#define USART_IT_PE ((uint16_t)0x0028)
#define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_RXNE ((uint16_t)0x0525)
#define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_ERR ((uint16_t)0x0060)
#define USART_IT_ORE ((uint16_t)0x0360)
#define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_FE ((uint16_t)0x0160)
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
/**
* @}
*/
#define IS_USART_PERIPH_IT(PERIPH, USART_IT) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \
((*(u32*)&(PERIPH)) != UART5_BASE)) \
|| ((USART_IT) != USART_IT_CTS))
/** @defgroup USART_DMA_Requests
* @{
*/
/* USART DMA Requests --------------------------------------------------------*/
#define USART_DMAReq_Tx ((u16)0x0080)
#define USART_DMAReq_Rx ((u16)0x0040)
#define USART_DMAReq_Tx ((uint16_t)0x0080)
#define USART_DMAReq_Rx ((uint16_t)0x0040)
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFF3F) == 0x00) && ((DMAREQ) != (u16)0x00))
/**
* @}
*/
/* USART WakeUp methods ------------------------------------------------------*/
#define USART_WakeUp_IdleLine ((u16)0x0000)
#define USART_WakeUp_AddressMark ((u16)0x0800)
/** @defgroup USART_WakeUp_methods
* @{
*/
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
((WAKEUP) == USART_WakeUp_AddressMark))
/**
* @}
*/
/* USART LIN Break Detection Length ------------------------------------------*/
#define USART_LINBreakDetectLength_10b ((u16)0x0000)
#define USART_LINBreakDetectLength_11b ((u16)0x0020)
/** @defgroup USART_LIN_Break_Detection_Length
* @{
*/
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
((LENGTH) == USART_LINBreakDetectLength_11b))
/**
* @}
*/
/* USART IrDA Low Power ------------------------------------------------------*/
#define USART_IrDAMode_LowPower ((u16)0x0004)
#define USART_IrDAMode_Normal ((u16)0x0000)
/** @defgroup USART_IrDA_Low_Power
* @{
*/
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
((MODE) == USART_IrDAMode_Normal))
/**
* @}
*/
/* USART Flags ---------------------------------------------------------------*/
#define USART_FLAG_CTS ((u16)0x0200)
#define USART_FLAG_LBD ((u16)0x0100)
#define USART_FLAG_TXE ((u16)0x0080)
#define USART_FLAG_TC ((u16)0x0040)
#define USART_FLAG_RXNE ((u16)0x0020)
#define USART_FLAG_IDLE ((u16)0x0010)
#define USART_FLAG_ORE ((u16)0x0008)
#define USART_FLAG_NE ((u16)0x0004)
#define USART_FLAG_FE ((u16)0x0002)
#define USART_FLAG_PE ((u16)0x0001)
/** @defgroup USART_Flags
* @{
*/
#define USART_FLAG_CTS ((uint16_t)0x0200)
#define USART_FLAG_LBD ((uint16_t)0x0100)
#define USART_FLAG_TXE ((uint16_t)0x0080)
#define USART_FLAG_TC ((uint16_t)0x0040)
#define USART_FLAG_RXNE ((uint16_t)0x0020)
#define USART_FLAG_IDLE ((uint16_t)0x0010)
#define USART_FLAG_ORE ((uint16_t)0x0008)
#define USART_FLAG_NE ((uint16_t)0x0004)
#define USART_FLAG_FE ((uint16_t)0x0002)
#define USART_FLAG_PE ((uint16_t)0x0001)
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFC9F) == 0x00) && ((FLAG) != (u16)0x00))
#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(u32*)&(PERIPH)) != UART4_BASE) &&\
((*(u32*)&(PERIPH)) != UART5_BASE)) \
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
|| ((USART_FLAG) != USART_FLAG_CTS))
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* @}
*/
/**
* @}
*/
/** @defgroup USART_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USART_Exported_Functions
* @{
*/
void USART_DeInit(USART_TypeDef* USARTx);
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState);
void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address);
void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp);
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength);
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SendData(USART_TypeDef* USARTx, u16 Data);
u16 USART_ReceiveData(USART_TypeDef* USARTx);
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
void USART_SendBreak(USART_TypeDef* USARTx);
void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime);
void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler);
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode);
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG);
void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT);
void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT);
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_USART_H */
/**
* @}
*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

124
src/platform/stm32/FWLib/library/inc/stm32f10x_wwdg.h
View File

@ -1,54 +1,114 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_wwdg.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* WWDG firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file stm32f10x_wwdg.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains all the functions prototypes for the WWDG firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_WWDG_H
#define __STM32F10x_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#include "stm32f10x.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* WWDG Prescaler */
#define WWDG_Prescaler_1 ((u32)0x00000000)
#define WWDG_Prescaler_2 ((u32)0x00000080)
#define WWDG_Prescaler_4 ((u32)0x00000100)
#define WWDG_Prescaler_8 ((u32)0x00000180)
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/** @defgroup WWDG_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Exported_Constants
* @{
*/
/** @defgroup WWDG_Prescaler
* @{
*/
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
((PRESCALER) == WWDG_Prescaler_2) || \
((PRESCALER) == WWDG_Prescaler_4) || \
((PRESCALER) == WWDG_Prescaler_8))
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* @}
*/
/**
* @}
*/
/** @defgroup WWDG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Exported_Functions
* @{
*/
void WWDG_DeInit(void);
void WWDG_SetPrescaler(u32 WWDG_Prescaler);
void WWDG_SetWindowValue(u8 WindowValue);
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableIT(void);
void WWDG_SetCounter(u8 Counter);
void WWDG_Enable(u8 Counter);
void WWDG_SetCounter(uint8_t Counter);
void WWDG_Enable(uint8_t Counter);
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_WWDG_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file misc.c
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "misc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
/** @defgroup MISC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_Defines
* @{
*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/**
* @}
*/
/** @defgroup MISC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_Functions
* @{
*/
/**
* @brief Configures the priority grouping: pre-emption priority and subpriority.
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
* 4 bits for subpriority
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
* 3 bits for subpriority
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
* 2 bits for subpriority
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
* 1 bits for subpriority
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
* 0 bits for subpriority
* @retval None
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
}
/**
* @brief Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct.
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
* the configuration information for the specified NVIC peripheral.
* @retval None
*/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority --------------------------------*/
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
tmppre = (0x4 - tmppriority);
tmpsub = tmpsub >> tmppriority;
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
tmppriority = tmppriority << 0x04;
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
/* Enable the Selected IRQ Channels --------------------------------------*/
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
else
{
/* Disable the Selected IRQ Channels -------------------------------------*/
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
}
/**
* @brief Sets the vector table location and Offset.
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
* This parameter can be one of the following values:
* @arg NVIC_VectTab_RAM
* @arg NVIC_VectTab_FLASH
* @param Offset: Vector Table base offset field. This value must be a multiple of 0x100.
* @retval None
*/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
{
/* Check the parameters */
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
assert_param(IS_NVIC_OFFSET(Offset));
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief Selects the condition for the system to enter low power mode.
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
* This parameter can be one of the following values:
* @arg NVIC_LP_SEVONPEND
* @arg NVIC_LP_SLEEPDEEP
* @arg NVIC_LP_SLEEPONEXIT
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_NVIC_LP(LowPowerMode));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SCB->SCR |= LowPowerMode;
}
else
{
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
}
}
/**
* @brief Configures the SysTick clock source.
* @param SysTick_CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_bkp.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the BKP firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_bkp.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ------------ BKP registers bit address in the alias region ----------- */
#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of TPAL bit */
#define CR_OFFSET (BKP_OFFSET + 0x30)
#define TPAL_BitNumber 0x01
#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
/* Alias word address of TPE bit */
#define TPE_BitNumber 0x00
#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of TPIE bit */
#define CSR_OFFSET (BKP_OFFSET + 0x34)
#define TPIE_BitNumber 0x02
#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
/* Alias word address of TIF bit */
#define TIF_BitNumber 0x09
#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
/* Alias word address of TEF bit */
#define TEF_BitNumber 0x08
#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
/* ---------------------- BKP registers bit mask ------------------------ */
/* RTCCR register bit mask */
#define RTCCR_CAL_Mask ((u16)0xFF80)
#define RTCCR_Mask ((u16)0xFC7F)
/* CSR register bit mask */
#define CSR_CTE_Set ((u16)0x0001)
#define CSR_CTI_Set ((u16)0x0002)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : BKP_DeInit
* Description : Deinitializes the BKP peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void BKP_DeInit(void)
{
RCC_BackupResetCmd(ENABLE);
RCC_BackupResetCmd(DISABLE);
}
/*******************************************************************************
* Function Name : BKP_TamperPinLevelConfig
* Description : Configures the Tamper Pin active level.
* Input : - BKP_TamperPinLevel: specifies the Tamper Pin active level.
* This parameter can be one of the following values:
* - BKP_TamperPinLevel_High: Tamper pin active on high level
* - BKP_TamperPinLevel_Low: Tamper pin active on low level
* Output : None
* Return : None
*******************************************************************************/
void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel)
{
/* Check the parameters */
assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
*(vu32 *) CR_TPAL_BB = BKP_TamperPinLevel;
}
/*******************************************************************************
* Function Name : BKP_TamperPinCmd
* Description : Enables or disables the Tamper Pin activation.
* Input : - NewState: new state of the Tamper Pin activation.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void BKP_TamperPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_TPE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : BKP_ITConfig
* Description : Enables or disables the Tamper Pin Interrupt.
* Input : - NewState: new state of the Tamper Pin Interrupt.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void BKP_ITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CSR_TPIE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : BKP_RTCOutputConfig
* Description : Select the RTC output source to output on the Tamper pin.
* Input : - BKP_RTCOutputSource: specifies the RTC output source.
* This parameter can be one of the following values:
* - BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
* - BKP_RTCOutputSource_CalibClock: output the RTC clock
* with frequency divided by 64 on the Tamper pin.
* - BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse
* signal on the Tamper pin.
* - BKP_RTCOutputSource_Second: output the RTC Second pulse
* signal on the Tamper pin.
* Output : None
* Return : None
*******************************************************************************/
void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource)
{
u16 tmpreg = 0;
/* Check the parameters */
assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
tmpreg = BKP->RTCCR;
/* Clear CCO, ASOE and ASOS bits */
tmpreg &= RTCCR_Mask;
/* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
tmpreg |= BKP_RTCOutputSource;
/* Store the new value */
BKP->RTCCR = tmpreg;
}
/*******************************************************************************
* Function Name : BKP_SetRTCCalibrationValue
* Description : Sets RTC Clock Calibration value.
* Input : - CalibrationValue: specifies the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x7F.
* Output : None
* Return : None
*******************************************************************************/
void BKP_SetRTCCalibrationValue(u8 CalibrationValue)
{
u16 tmpreg = 0;
/* Check the parameters */
assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
tmpreg = BKP->RTCCR;
/* Clear CAL[6:0] bits */
tmpreg &= RTCCR_CAL_Mask;
/* Set CAL[6:0] bits according to CalibrationValue value */
tmpreg |= CalibrationValue;
/* Store the new value */
BKP->RTCCR = tmpreg;
}
/*******************************************************************************
* Function Name : BKP_WriteBackupRegister
* Description : Writes user data to the specified Data Backup Register.
* Input : - BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 42]
* - Data: data to write
* Output : None
* Return : None
*******************************************************************************/
void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data)
{
/* Check the parameters */
assert_param(IS_BKP_DR(BKP_DR));
*(vu16 *) (BKP_BASE + BKP_DR) = Data;
}
/*******************************************************************************
* Function Name : BKP_ReadBackupRegister
* Description : Reads data from the specified Data Backup Register.
* Input : - BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 42]
* Output : None
* Return : The content of the specified Data Backup Register
*******************************************************************************/
u16 BKP_ReadBackupRegister(u16 BKP_DR)
{
/* Check the parameters */
assert_param(IS_BKP_DR(BKP_DR));
return (*(vu16 *) (BKP_BASE + BKP_DR));
}
/*******************************************************************************
* Function Name : BKP_GetFlagStatus
* Description : Checks whether the Tamper Pin Event flag is set or not.
* Input : None
* Output : None
* Return : The new state of the Tamper Pin Event flag (SET or RESET).
*******************************************************************************/
FlagStatus BKP_GetFlagStatus(void)
{
return (FlagStatus)(*(vu32 *) CSR_TEF_BB);
}
/*******************************************************************************
* Function Name : BKP_ClearFlag
* Description : Clears Tamper Pin Event pending flag.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void BKP_ClearFlag(void)
{
/* Set CTE bit to clear Tamper Pin Event flag */
BKP->CSR |= CSR_CTE_Set;
}
/*******************************************************************************
* Function Name : BKP_GetITStatus
* Description : Checks whether the Tamper Pin Interrupt has occurred or not.
* Input : None
* Output : None
* Return : The new state of the Tamper Pin Interrupt (SET or RESET).
*******************************************************************************/
ITStatus BKP_GetITStatus(void)
{
return (ITStatus)(*(vu32 *) CSR_TIF_BB);
}
/*******************************************************************************
* Function Name : BKP_ClearITPendingBit
* Description : Clears Tamper Pin Interrupt pending bit.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void BKP_ClearITPendingBit(void)
{
/* Set CTI bit to clear Tamper Pin Interrupt pending bit */
BKP->CSR |= CSR_CTI_Set;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f10x_bkp.c
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file provides all the BKP firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_bkp.h"
#include "stm32f10x_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup BKP
* @brief BKP driver modules
* @{
*/
/** @defgroup BKP_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Private_Defines
* @{
*/
/* ------------ BKP registers bit address in the alias region --------------- */
#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
/* --- CR Register ----*/
/* Alias word address of TPAL bit */
#define CR_OFFSET (BKP_OFFSET + 0x30)
#define TPAL_BitNumber 0x01
#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
/* Alias word address of TPE bit */
#define TPE_BitNumber 0x00
#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of TPIE bit */
#define CSR_OFFSET (BKP_OFFSET + 0x34)
#define TPIE_BitNumber 0x02
#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
/* Alias word address of TIF bit */
#define TIF_BitNumber 0x09
#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
/* Alias word address of TEF bit */
#define TEF_BitNumber 0x08
#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
/* ---------------------- BKP registers bit mask ------------------------ */
/* RTCCR register bit mask */
#define RTCCR_CAL_Mask ((uint16_t)0xFF80)
#define RTCCR_Mask ((uint16_t)0xFC7F)
/* CSR register bit mask */
#define CSR_CTE_Set ((uint16_t)0x0001)
#define CSR_CTI_Set ((uint16_t)0x0002)
/**
* @}
*/
/** @defgroup BKP_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Private_Functions
* @{
*/
/**
* @brief Deinitializes the BKP peripheral registers to their default reset values.
* @param None
* @retval None
*/
void BKP_DeInit(void)
{
RCC_BackupResetCmd(ENABLE);
RCC_BackupResetCmd(DISABLE);
}
/**
* @brief Configures the Tamper Pin active level.
* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
* This parameter can be one of the following values:
* @arg BKP_TamperPinLevel_High: Tamper pin active on high level
* @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
* @retval None
*/
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
{
/* Check the parameters */
assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
*(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
}
/**
* @brief Enables or disables the Tamper Pin activation.
* @param NewState: new state of the Tamper Pin activation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void BKP_TamperPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
}
/**
* @brief Enables or disables the Tamper Pin Interrupt.
* @param NewState: new state of the Tamper Pin Interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void BKP_ITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
}
/**
* @brief Select the RTC output source to output on the Tamper pin.
* @param BKP_RTCOutputSource: specifies the RTC output source.
* This parameter can be one of the following values:
* @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
* @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
* divided by 64 on the Tamper pin.
* @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
* the Tamper pin.
* @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
* the Tamper pin.
* @retval None
*/
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
{
uint16_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
tmpreg = BKP->RTCCR;
/* Clear CCO, ASOE and ASOS bits */
tmpreg &= RTCCR_Mask;
/* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
tmpreg |= BKP_RTCOutputSource;
/* Store the new value */
BKP->RTCCR = tmpreg;
}
/**
* @brief Sets RTC Clock Calibration value.
* @param CalibrationValue: specifies the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x7F.
* @retval None
*/
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
{
uint16_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
tmpreg = BKP->RTCCR;
/* Clear CAL[6:0] bits */
tmpreg &= RTCCR_CAL_Mask;
/* Set CAL[6:0] bits according to CalibrationValue value */
tmpreg |= CalibrationValue;
/* Store the new value */
BKP->RTCCR = tmpreg;
}
/**
* @brief Writes user data to the specified Data Backup Register.
* @param BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 42]
* @param Data: data to write
* @retval None
*/
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_BKP_DR(BKP_DR));
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
*(__IO uint32_t *) tmp = Data;
}
/**
* @brief Reads data from the specified Data Backup Register.
* @param BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 42]
* @retval The content of the specified Data Backup Register
*/
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_BKP_DR(BKP_DR));
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
return (*(__IO uint16_t *) tmp);
}
/**
* @brief Checks whether the Tamper Pin Event flag is set or not.
* @param None
* @retval The new state of the Tamper Pin Event flag (SET or RESET).
*/
FlagStatus BKP_GetFlagStatus(void)
{
return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
}
/**
* @brief Clears Tamper Pin Event pending flag.
* @param None
* @retval None
*/
void BKP_ClearFlag(void)
{
/* Set CTE bit to clear Tamper Pin Event flag */
BKP->CSR |= CSR_CTE_Set;
}
/**
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
* @param None
* @retval The new state of the Tamper Pin Interrupt (SET or RESET).
*/
ITStatus BKP_GetITStatus(void)
{
return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
}
/**
* @brief Clears Tamper Pin Interrupt pending bit.
* @param None
* @retval None
*/
void BKP_ClearITPendingBit(void)
{
/* Set CTI bit to clear Tamper Pin Interrupt pending bit */
BKP->CSR |= CSR_CTI_Set;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_crc.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the CRC firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_crc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* CR register bit mask */
#define CR_RESET_Set ((u32)0x00000001)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : CRC_ResetDR
* Description : Resets the CRC Data register (DR).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void CRC_ResetDR(void)
{
/* Reset CRC generator */
CRC->CR = CR_RESET_Set;
}
/*******************************************************************************
* Function Name : CRC_CalcCRC
* Description : Computes the 32-bit CRC of a given data word(32-bit).
* Input : - Data: data word(32-bit) to compute its CRC
* Output : None
* Return : 32-bit CRC
*******************************************************************************/
u32 CRC_CalcCRC(u32 Data)
{
CRC->DR = Data;
return (CRC->DR);
}
/*******************************************************************************
* Function Name : CRC_CalcBlockCRC
* Description : Computes the 32-bit CRC of a given buffer of data word(32-bit).
* Input : - pBuffer: pointer to the buffer containing the data to be
* computed
* - BufferLength: length of the buffer to be computed
* Output : None
* Return : 32-bit CRC
*******************************************************************************/
u32 CRC_CalcBlockCRC(u32 pBuffer[], u32 BufferLength)
{
u32 index = 0;
for(index = 0; index < BufferLength; index++)
{
CRC->DR = pBuffer[index];
}
return (CRC->DR);
}
/*******************************************************************************
* Function Name : CRC_GetCRC
* Description : Returns the current CRC value.
* Input : None
* Output : None
* Return : 32-bit CRC
*******************************************************************************/
u32 CRC_GetCRC(void)
{
return (CRC->DR);
}
/*******************************************************************************
* Function Name : CRC_SetIDRegister
* Description : Stores a 8-bit data in the Independent Data(ID) register.
* Input : - IDValue: 8-bit value to be stored in the ID register
* Output : None
* Return : None
*******************************************************************************/
void CRC_SetIDRegister(u8 IDValue)
{
CRC->IDR = IDValue;
}
/*******************************************************************************
* Function Name : CRC_GetIDRegister
* Description : Returns the 8-bit data stored in the Independent Data(ID) register
* Input : None
* Output : None
* Return : 8-bit value of the ID register
*******************************************************************************/
u8 CRC_GetIDRegister(void)
{
return (CRC->IDR);
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f10x_crc.c
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file provides all the CRC firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_crc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
/** @defgroup CRC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Defines
* @{
*/
/* CR register bit mask */
#define CR_RESET_Set ((uint32_t)0x00000001)
/**
* @}
*/
/** @defgroup CRC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Functions
* @{
*/
/**
* @brief Resets the CRC Data register (DR).
* @param None
* @retval None
*/
void CRC_ResetDR(void)
{
/* Reset CRC generator */
CRC->CR = CR_RESET_Set;
}
/**
* @brief Computes the 32-bit CRC of a given data word(32-bit).
* @param Data: data word(32-bit) to compute its CRC
* @retval 32-bit CRC
*/
uint32_t CRC_CalcCRC(uint32_t Data)
{
CRC->DR = Data;
return (CRC->DR);
}
/**
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
* @param pBuffer: pointer to the buffer containing the data to be computed
* @param BufferLength: length of the buffer to be computed
* @retval 32-bit CRC
*/
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0;
for(index = 0; index < BufferLength; index++)
{
CRC->DR = pBuffer[index];
}
return (CRC->DR);
}
/**
* @brief Returns the current CRC value.
* @param None
* @retval 32-bit CRC
*/
uint32_t CRC_GetCRC(void)
{
return (CRC->DR);
}
/**
* @brief Stores a 8-bit data in the Independent Data(ID) register.
* @param IDValue: 8-bit value to be stored in the ID register
* @retval None
*/
void CRC_SetIDRegister(uint8_t IDValue)
{
CRC->IDR = IDValue;
}
/**
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
* @param None
* @retval 8-bit value of the ID register
*/
uint8_t CRC_GetIDRegister(void)
{
return (CRC->IDR);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_dac.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the DAC firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dac.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* DAC EN mask */
#define CR_EN_Set ((u32)0x00000001)
/* DAC DMAEN mask */
#define CR_DMAEN_Set ((u32)0x00001000)
/* CR register Mask */
#define CR_CLEAR_Mask ((u32)0x00000FFE)
/* DAC SWTRIG mask */
#define SWTRIGR_SWTRIG_Set ((u32)0x00000001)
/* DAC Dual Channels SWTRIG masks */
#define DUAL_SWTRIG_Set ((u32)0x00000003)
#define DUAL_SWTRIG_Reset ((u32)0xFFFFFFFC)
/* DHR registers offsets */
#define DHR12R1_Offset ((u32)0x00000008)
#define DHR12R2_Offset ((u32)0x00000014)
#define DHR12RD_Offset ((u32)0x00000020)
/* DOR register offset */
#define DOR_Offset ((u32)0x0000002C)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : DAC_DeInit
* Description : Deinitializes the DAC peripheral registers to their default
* reset values.
* Input : None.
* Output : None
* Return : None
*******************************************************************************/
void DAC_DeInit(void)
{
/* Enable DAC reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
/* Release DAC from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
}
/*******************************************************************************
* Function Name : DAC_Init
* Description : Initializes the DAC peripheral according to the specified
* parameters in the DAC_InitStruct.
* Input : - DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* - DAC_Channel_1: DAC Channel1 selected
* - DAC_Channel_2: DAC Channel2 selected
* - DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
* contains the configuration information for the specified
* DAC channel.
* Output : None
* Return : None
*******************************************************************************/
void DAC_Init(u32 DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
{
u32 tmpreg1 = 0, tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
/*---------------------------- DAC CR Configuration --------------------------*/
/* Get the DAC CR value */
tmpreg1 = DAC->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);
/* Configure for the selected DAC channel: buffer output, trigger, wave genration,
mask/amplitude for wave genration */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set WAVEx bits according to DAC_WaveGeneration value */
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << DAC_Channel;
/* Write to DAC CR */
DAC->CR = tmpreg1;
}
/*******************************************************************************
* Function Name : DAC_StructInit
* Description : Fills each DAC_InitStruct member with its default value.
* Input : - DAC_InitStruct : pointer to a DAC_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
{
/*--------------- Reset DAC init structure parameters values -----------------*/
/* Initialize the DAC_Trigger member */
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
/* Initialize the DAC_WaveGeneration member */
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
/* Initialize the DAC_OutputBuffer member */
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
}
/*******************************************************************************
* Function Name : DAC_Cmd
* Description : Enables or disables the specified DAC channel.
* Input - DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* - DAC_Channel_1: DAC Channel1 selected
* - DAC_Channel_2: DAC Channel2 selected
* - NewState: new state of the DAC channel.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DAC_Cmd(u32 DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel */
DAC->CR |= CR_EN_Set << DAC_Channel;
}
else
{
/* Disable the selected DAC channel */
DAC->CR &= ~(CR_EN_Set << DAC_Channel);
}
}
/*******************************************************************************
* Function Name : DAC_DMACmd
* Description : Enables or disables the specified DAC channel DMA request.
* Input - DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* - DAC_Channel_1: DAC Channel1 selected
* - DAC_Channel_2: DAC Channel2 selected
* - NewState: new state of the selected DAC channel DMA request.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DAC_DMACmd(u32 DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel DMA request */
DAC->CR |= CR_DMAEN_Set << DAC_Channel;
}
else
{
/* Disable the selected DAC channel DMA request */
DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);
}
}
/*******************************************************************************
* Function Name : DAC_SoftwareTriggerCmd
* Description : Enables or disables the selected DAC channel software trigger.
* Input - DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* - DAC_Channel_1: DAC Channel1 selected
* - DAC_Channel_2: DAC Channel2 selected
* - NewState: new state of the selected DAC channel software trigger.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DAC_SoftwareTriggerCmd(u32 DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for the selected DAC channel */
DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);
}
else
{
/* Disable software trigger for the selected DAC channel */
DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));
}
}
/*******************************************************************************
* Function Name : DAC_DualSoftwareTriggerCmd
* Description : Enables or disables simultaneously the two DAC channels software
* triggers.
* Input - NewState: new state of the DAC channels software triggers.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for both DAC channels */
DAC->SWTRIGR |= DUAL_SWTRIG_Set ;
}
else
{
/* Disable software trigger for both DAC channels */
DAC->SWTRIGR &= DUAL_SWTRIG_Reset;
}
}
/*******************************************************************************
* Function Name : DAC_WaveGenerationCmd
* Description : Enables or disables the selected DAC channel wave generation.
* Input - DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* - DAC_Channel_1: DAC Channel1 selected
* - DAC_Channel_2: DAC Channel2 selected
* - DAC_Wave: Specifies the wave type to enable or disable.
* This parameter can be one of the following values:
* - DAC_Wave_Noise: noise wave generation
* - DAC_Wave_Triangle: triangle wave generation
* - NewState: new state of the selected DAC channel wave generation.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DAC_WaveGenerationCmd(u32 DAC_Channel, u32 DAC_Wave, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_WAVE(DAC_Wave));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected wave generation for the selected DAC channel */
DAC->CR |= DAC_Wave << DAC_Channel;
}
else
{
/* Disable the selected wave generation for the selected DAC channel */
DAC->CR &= ~(DAC_Wave << DAC_Channel);
}
}
/*******************************************************************************
* Function Name : DAC_SetChannel1Data
* Description : Set the specified data holding register value for DAC channel1.
* Input : - DAC_Align: Specifies the data alignement for DAC channel1.
* This parameter can be one of the following values:
* - DAC_Align_8b_R: 8bit right data alignement selected
* - DAC_Align_12b_L: 12bit left data alignement selected
* - DAC_Align_12b_R: 12bit right data alignement selected
* - Data : Data to be loaded in the selected data holding
* register.
* Output : None
* Return : None
*******************************************************************************/
void DAC_SetChannel1Data(u32 DAC_Align, u16 Data)
{
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
/* Set the DAC channel1 selected data holding register */
*((vu32 *)(DAC_BASE + DHR12R1_Offset + DAC_Align)) = (u32)Data;
}
/*******************************************************************************
* Function Name : DAC_SetChannel2Data
* Description : Set the specified data holding register value for DAC channel2.
* Input : - DAC_Align: Specifies the data alignement for DAC channel2.
* This parameter can be one of the following values:
* - DAC_Align_8b_R: 8bit right data alignement selected
* - DAC_Align_12b_L: 12bit left data alignement selected
* - DAC_Align_12b_R: 12bit right data alignement selected
* - Data : Data to be loaded in the selected data holding
* register.
* Output : None
* Return : None
*******************************************************************************/
void DAC_SetChannel2Data(u32 DAC_Align, u16 Data)
{
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
/* Set the DAC channel2 selected data holding register */
*((vu32 *)(DAC_BASE + DHR12R2_Offset + DAC_Align)) = (u32)Data;
}
/*******************************************************************************
* Function Name : DAC_SetDualChannelData
* Description : Set the specified data holding register value for dual channel
* DAC.
* Input : - DAC_Align: Specifies the data alignement for dual channel DAC.
* This parameter can be one of the following values:
* - DAC_Align_8b_R: 8bit right data alignement selected
* - DAC_Align_12b_L: 12bit left data alignement selected
* - DAC_Align_12b_R: 12bit right data alignement selected
* - Data2: Data for DAC Channel2 to be loaded in the selected data
* holding register.
* - Data1: Data for DAC Channel1 to be loaded in the selected data
* holding register.
* Output : None
* Return : None
*******************************************************************************/
void DAC_SetDualChannelData(u32 DAC_Align, u16 Data2, u16 Data1)
{
u32 data = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (DAC_Align == DAC_Align_8b_R)
{
data = ((u32)Data2 << 8) | Data1;
}
else
{
data = ((u32)Data2 << 16) | Data1;
}
/* Set the dual DAC selected data holding register */
*((vu32 *)(DAC_BASE + DHR12RD_Offset + DAC_Align)) = data;
}
/*******************************************************************************
* Function Name : DAC_GetDataOutputValue
* Description : Returns the last data output value of the selected DAC cahnnel.
* Input - DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* - DAC_Channel_1: DAC Channel1 selected
* - DAC_Channel_2: DAC Channel2 selected
* Output : None
* Return : The selected DAC channel data output value.
*******************************************************************************/
u16 DAC_GetDataOutputValue(u32 DAC_Channel)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
/* Returns the DAC channel data output register value */
return (u16) (*(vu32*)(DAC_BASE + DOR_Offset + ((u32)DAC_Channel >> 2)));
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f10x_dac.c
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file provides all the DAC firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dac.h"
#include "stm32f10x_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup DAC
* @brief DAC driver modules
* @{
*/
/** @defgroup DAC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_Defines
* @{
*/
/* DAC EN mask */
#define CR_EN_Set ((uint32_t)0x00000001)
/* DAC DMAEN mask */
#define CR_DMAEN_Set ((uint32_t)0x00001000)
/* CR register Mask */
#define CR_CLEAR_Mask ((uint32_t)0x00000FFE)
/* DAC SWTRIG mask */
#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001)
/* DAC Dual Channels SWTRIG masks */
#define DUAL_SWTRIG_Set ((uint32_t)0x00000003)
#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC)
/* DHR registers offsets */
#define DHR12R1_Offset ((uint32_t)0x00000008)
#define DHR12R2_Offset ((uint32_t)0x00000014)
#define DHR12RD_Offset ((uint32_t)0x00000020)
/* DOR register offset */
#define DOR_Offset ((uint32_t)0x0000002C)
/**
* @}
*/
/** @defgroup DAC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_Functions
* @{
*/
/**
* @brief Deinitializes the DAC peripheral registers to their default reset values.
* @param None
* @retval None
*/
void DAC_DeInit(void)
{
/* Enable DAC reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
/* Release DAC from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
}
/**
* @brief Initializes the DAC peripheral according to the specified
* parameters in the DAC_InitStruct.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
* contains the configuration information for the specified DAC channel.
* @retval None
*/
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
/*---------------------------- DAC CR Configuration --------------------------*/
/* Get the DAC CR value */
tmpreg1 = DAC->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);
/* Configure for the selected DAC channel: buffer output, trigger, wave genration,
mask/amplitude for wave genration */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set WAVEx bits according to DAC_WaveGeneration value */
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << DAC_Channel;
/* Write to DAC CR */
DAC->CR = tmpreg1;
}
/**
* @brief Fills each DAC_InitStruct member with its default value.
* @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
{
/*--------------- Reset DAC init structure parameters values -----------------*/
/* Initialize the DAC_Trigger member */
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
/* Initialize the DAC_WaveGeneration member */
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
/* Initialize the DAC_OutputBuffer member */
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
}
/**
* @brief Enables or disables the specified DAC channel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the DAC channel.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel */
DAC->CR |= CR_EN_Set << DAC_Channel;
}
else
{
/* Disable the selected DAC channel */
DAC->CR &= ~(CR_EN_Set << DAC_Channel);
}
}
/**
* @brief Enables or disables the specified DAC channel DMA request.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel DMA request.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel DMA request */
DAC->CR |= CR_DMAEN_Set << DAC_Channel;
}
else
{
/* Disable the selected DAC channel DMA request */
DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);
}
}
/**
* @brief Enables or disables the selected DAC channel software trigger.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel software trigger.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for the selected DAC channel */
DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);
}
else
{
/* Disable software trigger for the selected DAC channel */
DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));
}
}
/**
* @brief Enables or disables simultaneously the two DAC channels software
* triggers.
* @param NewState: new state of the DAC channels software triggers.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for both DAC channels */
DAC->SWTRIGR |= DUAL_SWTRIG_Set ;
}
else
{
/* Disable software trigger for both DAC channels */
DAC->SWTRIGR &= DUAL_SWTRIG_Reset;
}
}
/**
* @brief Enables or disables the selected DAC channel wave generation.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_Wave: Specifies the wave type to enable or disable.
* This parameter can be one of the following values:
* @arg DAC_Wave_Noise: noise wave generation
* @arg DAC_Wave_Triangle: triangle wave generation
* @param NewState: new state of the selected DAC channel wave generation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_WAVE(DAC_Wave));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected wave generation for the selected DAC channel */
DAC->CR |= DAC_Wave << DAC_Channel;
}
else
{
/* Disable the selected wave generation for the selected DAC channel */
DAC->CR &= ~(DAC_Wave << DAC_Channel);
}
}
/**
* @brief Set the specified data holding register value for DAC channel1.
* @param DAC_Align: Specifies the data alignement for DAC channel1.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignement selected
* @arg DAC_Align_12b_L: 12bit left data alignement selected
* @arg DAC_Align_12b_R: 12bit right data alignement selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None
*/
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R1_Offset + DAC_Align;
/* Set the DAC channel1 selected data holding register */
*(__IO uint32_t *) tmp = Data;
}
/**
* @brief Set the specified data holding register value for DAC channel2.
* @param DAC_Align: Specifies the data alignement for DAC channel2.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignement selected
* @arg DAC_Align_12b_L: 12bit left data alignement selected
* @arg DAC_Align_12b_R: 12bit right data alignement selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None
*/
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R2_Offset + DAC_Align;
/* Set the DAC channel2 selected data holding register */
*(__IO uint32_t *)tmp = Data;
}
/**
* @brief Set the specified data holding register value for dual channel
* DAC.
* @param DAC_Align: Specifies the data alignement for dual channel DAC.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignement selected
* @arg DAC_Align_12b_L: 12bit left data alignement selected
* @arg DAC_Align_12b_R: 12bit right data alignement selected
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
* holding register.
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
* holding register.
* @retval None
*/
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
{
uint32_t data = 0, tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (DAC_Align == DAC_Align_8b_R)
{
data = ((uint32_t)Data2 << 8) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16) | Data1;
}
tmp = (uint32_t)DAC_BASE;
tmp += DHR12RD_Offset + DAC_Align;
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
}
/**
* @brief Returns the last data output value of the selected DAC cahnnel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
tmp = (uint32_t) DAC_BASE ;
tmp += DOR_Offset + ((uint32_t)DAC_Channel >> 2);
/* Returns the DAC channel data output register value */
return (uint16_t) (*(__IO uint32_t*) tmp);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_dbgmcu.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the DBGMCU firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dbgmcu.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define IDCODE_DEVID_Mask ((u32)0x00000FFF)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : DBGMCU_GetREVID
* Description : Returns the device revision identifier.
* Input : None
* Output : None
* Return : Device revision identifier
*******************************************************************************/
u32 DBGMCU_GetREVID(void)
{
return(DBGMCU->IDCODE >> 16);
}
/*******************************************************************************
* Function Name : DBGMCU_GetDEVID
* Description : Returns the device identifier.
* Input : None
* Output : None
* Return : Device identifier
*******************************************************************************/
u32 DBGMCU_GetDEVID(void)
{
return(DBGMCU->IDCODE & IDCODE_DEVID_Mask);
}
/*******************************************************************************
* Function Name : DBGMCU_Config
* Description : Configures the specified peripheral and low power mode behavior
* when the MCU under Debug mode.
* Input : - DBGMCU_Periph: specifies the peripheral and low power mode.
* This parameter can be any combination of the following values:
* - DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
* - DBGMCU_STOP: Keep debugger connection during STOP mode
* - DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
* - DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
* - DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
* - DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
* - DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
* - DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
* - DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
* - DBGMCU_CAN_STOP: Debug CAN stopped when Core is halted
* - DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped
* when Core is halted
* - DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped
* when Core is halted
* - DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
* - DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
* - DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
* - DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
* - NewState: new state of the specified peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DBGMCU_Config(u32 DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->CR |= DBGMCU_Periph;
}
else
{
DBGMCU->CR &= ~DBGMCU_Periph;
}
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f10x_dbgmcu.c
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file provides all the DBGMCU firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dbgmcu.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup DBGMCU
* @brief DBGMCU driver modules
* @{
*/
/** @defgroup DBGMCU_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_Defines
* @{
*/
#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF)
/**
* @}
*/
/** @defgroup DBGMCU_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_Functions
* @{
*/
/**
* @brief Returns the device revision identifier.
* @param None
* @retval Device revision identifier
*/
uint32_t DBGMCU_GetREVID(void)
{
return(DBGMCU->IDCODE >> 16);
}
/**
* @brief Returns the device identifier.
* @param None
* @retval Device identifier
*/
uint32_t DBGMCU_GetDEVID(void)
{
return(DBGMCU->IDCODE & IDCODE_DEVID_Mask);
}
/**
* @brief Configures the specified peripheral and low power mode behavior
* when the MCU under Debug mode.
* @param DBGMCU_Periph: specifies the peripheral and low power mode.
* This parameter can be any combination of the following values:
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
* @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
* @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
* @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
* @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
* @param NewState: new state of the specified peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->CR |= DBGMCU_Periph;
}
else
{
DBGMCU->CR &= ~DBGMCU_Periph;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_exti.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the EXTI firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_exti.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define EXTI_LineNone ((u32)0x00000) /* No interrupt selected */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : EXTI_DeInit
* Description : Deinitializes the EXTI peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI_DeInit(void)
{
EXTI->IMR = 0x00000000;
EXTI->EMR = 0x00000000;
EXTI->RTSR = 0x00000000;
EXTI->FTSR = 0x00000000;
EXTI->PR = 0x0007FFFF;
}
/*******************************************************************************
* Function Name : EXTI_Init
* Description : Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* that contains the configuration information for the EXTI
* peripheral.
* Output : None
* Return : None
*******************************************************************************/
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
{
/* Check the parameters */
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
/* Clear EXTI line configuration */
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
*(vu32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)|= EXTI_InitStruct->EXTI_Line;
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
/* Select the trigger for the selected external interrupts */
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{
/* Rising Falling edge */
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
}
else
{
*(vu32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Trigger)|= EXTI_InitStruct->EXTI_Line;
}
}
else
{
/* Disable the selected external lines */
*(vu32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)&= ~EXTI_InitStruct->EXTI_Line;
}
}
/*******************************************************************************
* Function Name : EXTI_StructInit
* Description : Fills each EXTI_InitStruct member with its reset value.
* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LineNone;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/*******************************************************************************
* Function Name : EXTI_GenerateSWInterrupt
* Description : Generates a Software interrupt.
* Input : - EXTI_Line: specifies the EXTI lines to be enabled or
* disabled.
* This parameter can be any combination of EXTI_Linex where
* x can be (0..18).
* Output : None
* Return : None
*******************************************************************************/
void EXTI_GenerateSWInterrupt(u32 EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->SWIER |= EXTI_Line;
}
/*******************************************************************************
* Function Name : EXTI_GetFlagStatus
* Description : Checks whether the specified EXTI line flag is set or not.
* Input : - EXTI_Line: specifies the EXTI line flag to check.
* This parameter can be:
* - EXTI_Linex: External interrupt line x where x(0..18)
* Output : None
* Return : The new state of EXTI_Line (SET or RESET).
*******************************************************************************/
FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
if ((EXTI->PR & EXTI_Line) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : EXTI_ClearFlag
* Description : Clears the EXTI's line pending flags.
* Input : - EXTI_Line: specifies the EXTI lines flags to clear.
* This parameter can be any combination of EXTI_Linex where
* x can be (0..18).
* Output : None
* Return : None
*******************************************************************************/
void EXTI_ClearFlag(u32 EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->PR = EXTI_Line;
}
/*******************************************************************************
* Function Name : EXTI_GetITStatus
* Description : Checks whether the specified EXTI line is asserted or not.
* Input : - EXTI_Line: specifies the EXTI line to check.
* This parameter can be:
* - EXTI_Linex: External interrupt line x where x(0..18)
* Output : None
* Return : The new state of EXTI_Line (SET or RESET).
*******************************************************************************/
ITStatus EXTI_GetITStatus(u32 EXTI_Line)
{
ITStatus bitstatus = RESET;
u32 enablestatus = 0;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
enablestatus = EXTI->IMR & EXTI_Line;
if (((EXTI->PR & EXTI_Line) != (u32)RESET) && (enablestatus != (u32)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : EXTI_ClearITPendingBit
* Description : Clears the EXTI's line pending bits.
* Input : - EXTI_Line: specifies the EXTI lines to clear.
* This parameter can be any combination of EXTI_Linex where
* x can be (0..18).
* Output : None
* Return : None
*******************************************************************************/
void EXTI_ClearITPendingBit(u32 EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->PR = EXTI_Line;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f10x_exti.c
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file provides all the EXTI firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_exti.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup EXTI
* @brief EXTI driver modules
* @{
*/
/** @defgroup EXTI_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Private_Defines
* @{
*/
#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */
/**
* @}
*/
/** @defgroup EXTI_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Private_Functions
* @{
*/
/**
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
* @param None
* @retval None
*/
void EXTI_DeInit(void)
{
EXTI->IMR = 0x00000000;
EXTI->EMR = 0x00000000;
EXTI->RTSR = 0x00000000;
EXTI->FTSR = 0x00000000;
EXTI->PR = 0x000FFFFF;
}
/**
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* that contains the configuration information for the EXTI peripheral.
* @retval None
*/
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
{
uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
tmp = (uint32_t)EXTI_BASE;
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
/* Clear EXTI line configuration */
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
/* Select the trigger for the selected external interrupts */
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{
/* Rising Falling edge */
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
}
else
{
tmp = (uint32_t)EXTI_BASE;
tmp += EXTI_InitStruct->EXTI_Trigger;
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
}
}
else
{
tmp += EXTI_InitStruct->EXTI_Mode;
/* Disable the selected external lines */
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
}
}
/**
* @brief Fills each EXTI_InitStruct member with its reset value.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LineNone;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/**
* @brief Generates a Software interrupt.
* @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
* @retval None
*/
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->SWIER |= EXTI_Line;
}
/**
* @brief Checks whether the specified EXTI line flag is set or not.
* @param EXTI_Line: specifies the EXTI line flag to check.
* This parameter can be:
* @arg EXTI_Linex: External interrupt line x where x(0..19)
* @retval The new state of EXTI_Line (SET or RESET).
*/
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the EXTI<EFBFBD>s line pending flags.
* @param EXTI_Line: specifies the EXTI lines flags to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
* @retval None
*/
void EXTI_ClearFlag(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->PR = EXTI_Line;
}
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param EXTI_Line: specifies the EXTI line to check.
* This parameter can be:
* @arg EXTI_Linex: External interrupt line x where x(0..19)
* @retval The new state of EXTI_Line (SET or RESET).
*/
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
enablestatus = EXTI->IMR & EXTI_Line;
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the EXTI<EFBFBD>s line pending bits.
* @param EXTI_Line: specifies the EXTI lines to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
* @retval None
*/
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->PR = EXTI_Line;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_iwdg.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the IWDG firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_iwdg.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ---------------------- IWDG registers bit mask ------------------------ */
/* KR register bit mask */
#define KR_KEY_Reload ((u16)0xAAAA)
#define KR_KEY_Enable ((u16)0xCCCC)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : IWDG_WriteAccessCmd
* Description : Enables or disables write access to IWDG_PR and IWDG_RLR
* registers.
* Input : - IWDG_WriteAccess: new state of write access to IWDG_PR and
* IWDG_RLR registers.
* This parameter can be one of the following values:
* - IWDG_WriteAccess_Enable: Enable write access to
* IWDG_PR and IWDG_RLR registers
* - IWDG_WriteAccess_Disable: Disable write access to
* IWDG_PR and IWDG_RLR registers
* Output : None
* Return : None
*******************************************************************************/
void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess)
{
/* Check the parameters */
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
IWDG->KR = IWDG_WriteAccess;
}
/*******************************************************************************
* Function Name : IWDG_SetPrescaler
* Description : Sets IWDG Prescaler value.
* Input : - IWDG_Prescaler: specifies the IWDG Prescaler value.
* This parameter can be one of the following values:
* - IWDG_Prescaler_4: IWDG prescaler set to 4
* - IWDG_Prescaler_8: IWDG prescaler set to 8
* - IWDG_Prescaler_16: IWDG prescaler set to 16
* - IWDG_Prescaler_32: IWDG prescaler set to 32
* - IWDG_Prescaler_64: IWDG prescaler set to 64
* - IWDG_Prescaler_128: IWDG prescaler set to 128
* - IWDG_Prescaler_256: IWDG prescaler set to 256
* Output : None
* Return : None
*******************************************************************************/
void IWDG_SetPrescaler(u8 IWDG_Prescaler)
{
/* Check the parameters */
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
IWDG->PR = IWDG_Prescaler;
}
/*******************************************************************************
* Function Name : IWDG_SetReload
* Description : Sets IWDG Reload value.
* Input : - Reload: specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
* Output : None
* Return : None
*******************************************************************************/
void IWDG_SetReload(u16 Reload)
{
/* Check the parameters */
assert_param(IS_IWDG_RELOAD(Reload));
IWDG->RLR = Reload;
}
/*******************************************************************************
* Function Name : IWDG_ReloadCounter
* Description : Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void IWDG_ReloadCounter(void)
{
IWDG->KR = KR_KEY_Reload;
}
/*******************************************************************************
* Function Name : IWDG_Enable
* Description : Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
* disabled).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void IWDG_Enable(void)
{
IWDG->KR = KR_KEY_Enable;
}
/*******************************************************************************
* Function Name : IWDG_GetFlagStatus
* Description : Checks whether the specified IWDG flag is set or not.
* Input : - IWDG_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - IWDG_FLAG_PVU: Prescaler Value Update on going
* - IWDG_FLAG_RVU: Reload Value Update on going
* Output : None
* Return : The new state of IWDG_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
if ((IWDG->SR & IWDG_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f10x_iwdg.c
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file provides all the IWDG firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_iwdg.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup IWDG
* @brief IWDG driver modules
* @{
*/
/** @defgroup IWDG_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Private_Defines
* @{
*/
/* ---------------------- IWDG registers bit mask ----------------------------*/
/* KR register bit mask */
#define KR_KEY_Reload ((uint16_t)0xAAAA)
#define KR_KEY_Enable ((uint16_t)0xCCCC)
/**
* @}
*/
/** @defgroup IWDG_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Private_Functions
* @{
*/
/**
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
* This parameter can be one of the following values:
* @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
* @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
* @retval None
*/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
{
/* Check the parameters */
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
IWDG->KR = IWDG_WriteAccess;
}
/**
* @brief Sets IWDG Prescaler value.
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
* This parameter can be one of the following values:
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
* @retval None
*/
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
{
/* Check the parameters */
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
IWDG->PR = IWDG_Prescaler;
}
/**
* @brief Sets IWDG Reload value.
* @param Reload: specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
* @retval None
*/
void IWDG_SetReload(uint16_t Reload)
{
/* Check the parameters */
assert_param(IS_IWDG_RELOAD(Reload));
IWDG->RLR = Reload;
}
/**
* @brief Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param None
* @retval None
*/
void IWDG_ReloadCounter(void)
{
IWDG->KR = KR_KEY_Reload;
}
/**
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param None
* @retval None
*/
void IWDG_Enable(void)
{
IWDG->KR = KR_KEY_Enable;
}
/**
* @brief Checks whether the specified IWDG flag is set or not.
* @param IWDG_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg IWDG_FLAG_PVU: Prescaler Value Update on going
* @arg IWDG_FLAG_RVU: Reload Value Update on going
* @retval The new state of IWDG_FLAG (SET or RESET).
*/
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_lib.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all peripherals pointers initialization.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#define EXT
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
#ifdef DEBUG
/*******************************************************************************
* Function Name : debug
* Description : This function initialize peripherals pointers.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void debug(void)
{
/************************************* ADC ************************************/
#ifdef _ADC1
ADC1 = (ADC_TypeDef *) ADC1_BASE;
#endif /*_ADC1 */
#ifdef _ADC2
ADC2 = (ADC_TypeDef *) ADC2_BASE;
#endif /*_ADC2 */
#ifdef _ADC3
ADC3 = (ADC_TypeDef *) ADC3_BASE;
#endif /*_ADC3 */
/************************************* BKP ************************************/
#ifdef _BKP
BKP = (BKP_TypeDef *) BKP_BASE;
#endif /*_BKP */
/************************************* CAN ************************************/
#ifdef _CAN
CAN = (CAN_TypeDef *) CAN_BASE;
#endif /*_CAN */
/************************************* CRC ************************************/
#ifdef _CRC
CRC = (CRC_TypeDef *) CRC_BASE;
#endif /*_CRC */
/************************************* DAC ************************************/
#ifdef _DAC
DAC = (DAC_TypeDef *) DAC_BASE;
#endif /*_DAC */
/************************************* DBGMCU**********************************/
#ifdef _DBGMCU
DBGMCU = (DBGMCU_TypeDef *) DBGMCU_BASE;
#endif /*_DBGMCU */
/************************************* DMA ************************************/
#ifdef _DMA
DMA1 = (DMA_TypeDef *) DMA1_BASE;
DMA2 = (DMA_TypeDef *) DMA2_BASE;
#endif /*_DMA */
#ifdef _DMA1_Channel1
DMA1_Channel1 = (DMA_Channel_TypeDef *) DMA1_Channel1_BASE;
#endif /*_DMA1_Channel1 */
#ifdef _DMA1_Channel2
DMA1_Channel2 = (DMA_Channel_TypeDef *) DMA1_Channel2_BASE;
#endif /*_DMA1_Channel2 */
#ifdef _DMA1_Channel3
DMA1_Channel3 = (DMA_Channel_TypeDef *) DMA1_Channel3_BASE;
#endif /*_DMA1_Channel3 */
#ifdef _DMA1_Channel4
DMA1_Channel4 = (DMA_Channel_TypeDef *) DMA1_Channel4_BASE;
#endif /*_DMA1_Channel4 */
#ifdef _DMA1_Channel5
DMA1_Channel5 = (DMA_Channel_TypeDef *) DMA1_Channel5_BASE;
#endif /*_DMA1_Channel5 */
#ifdef _DMA1_Channel6
DMA1_Channel6 = (DMA_Channel_TypeDef *) DMA1_Channel6_BASE;
#endif /*_DMA1_Channel6 */
#ifdef _DMA1_Channel7
DMA1_Channel7 = (DMA_Channel_TypeDef *) DMA1_Channel7_BASE;
#endif /*_DMA1_Channel7 */
#ifdef _DMA2_Channel1
DMA2_Channel1 = (DMA_Channel_TypeDef *) DMA2_Channel1_BASE;
#endif /*_DMA2_Channel1 */
#ifdef _DMA2_Channel2
DMA2_Channel2 = (DMA_Channel_TypeDef *) DMA2_Channel2_BASE;
#endif /*_DMA2_Channel2 */
#ifdef _DMA2_Channel3
DMA2_Channel3 = (DMA_Channel_TypeDef *) DMA2_Channel3_BASE;
#endif /*_DMA2_Channel3 */
#ifdef _DMA2_Channel4
DMA2_Channel4 = (DMA_Channel_TypeDef *) DMA2_Channel4_BASE;
#endif /*_DMA2_Channel4 */
#ifdef _DMA2_Channel5
DMA2_Channel5 = (DMA_Channel_TypeDef *) DMA2_Channel5_BASE;
#endif /*_DMA2_Channel5 */
/************************************* EXTI ***********************************/
#ifdef _EXTI
EXTI = (EXTI_TypeDef *) EXTI_BASE;
#endif /*_EXTI */
/************************************* FLASH and Option Bytes *****************/
#ifdef _FLASH
FLASH = (FLASH_TypeDef *) FLASH_R_BASE;
OB = (OB_TypeDef *) OB_BASE;
#endif /*_FLASH */
/************************************* FSMC ***********************************/
#ifdef _FSMC
FSMC_Bank1 = (FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE;
FSMC_Bank1E = (FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE;
FSMC_Bank2 = (FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE;
FSMC_Bank3 = (FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE;
FSMC_Bank4 = (FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE;
#endif /*_FSMC */
/************************************* GPIO ***********************************/
#ifdef _GPIOA
GPIOA = (GPIO_TypeDef *) GPIOA_BASE;
#endif /*_GPIOA */
#ifdef _GPIOB
GPIOB = (GPIO_TypeDef *) GPIOB_BASE;
#endif /*_GPIOB */
#ifdef _GPIOC
GPIOC = (GPIO_TypeDef *) GPIOC_BASE;
#endif /*_GPIOC */
#ifdef _GPIOD
GPIOD = (GPIO_TypeDef *) GPIOD_BASE;
#endif /*_GPIOD */
#ifdef _GPIOE
GPIOE = (GPIO_TypeDef *) GPIOE_BASE;
#endif /*_GPIOE */
#ifdef _GPIOF
GPIOF = (GPIO_TypeDef *) GPIOF_BASE;
#endif /*_GPIOF */
#ifdef _GPIOG
GPIOG = (GPIO_TypeDef *) GPIOG_BASE;
#endif /*_GPIOG */
#ifdef _AFIO
AFIO = (AFIO_TypeDef *) AFIO_BASE;
#endif /*_AFIO */
/************************************* I2C ************************************/
#ifdef _I2C1
I2C1 = (I2C_TypeDef *) I2C1_BASE;
#endif /*_I2C1 */
#ifdef _I2C2
I2C2 = (I2C_TypeDef *) I2C2_BASE;
#endif /*_I2C2 */
/************************************* IWDG ***********************************/
#ifdef _IWDG
IWDG = (IWDG_TypeDef *) IWDG_BASE;
#endif /*_IWDG */
/************************************* NVIC ***********************************/
#ifdef _NVIC
NVIC = (NVIC_TypeDef *) NVIC_BASE;
SCB = (SCB_TypeDef *) SCB_BASE;
#endif /*_NVIC */
/************************************* PWR ************************************/
#ifdef _PWR
PWR = (PWR_TypeDef *) PWR_BASE;
#endif /*_PWR */
/************************************* RCC ************************************/
#ifdef _RCC
RCC = (RCC_TypeDef *) RCC_BASE;
#endif /*_RCC */
/************************************* RTC ************************************/
#ifdef _RTC
RTC = (RTC_TypeDef *) RTC_BASE;
#endif /*_RTC */
/************************************* SDIO ***********************************/
#ifdef _SDIO
SDIO = (SDIO_TypeDef *) SDIO_BASE;
#endif /*_SDIO */
/************************************* SPI ************************************/
#ifdef _SPI1
SPI1 = (SPI_TypeDef *) SPI1_BASE;
#endif /*_SPI1 */
#ifdef _SPI2
SPI2 = (SPI_TypeDef *) SPI2_BASE;
#endif /*_SPI2 */
#ifdef _SPI3
SPI3 = (SPI_TypeDef *) SPI3_BASE;
#endif /*_SPI3 */
/************************************* SysTick ********************************/
#ifdef _SysTick
SysTick = (SysTick_TypeDef *) SysTick_BASE;
#endif /*_SysTick */
/************************************* TIM ************************************/
#ifdef _TIM1
TIM1 = (TIM_TypeDef *) TIM1_BASE;
#endif /*_TIM1 */
#ifdef _TIM2
TIM2 = (TIM_TypeDef *) TIM2_BASE;
#endif /*_TIM2 */
#ifdef _TIM3
TIM3 = (TIM_TypeDef *) TIM3_BASE;
#endif /*_TIM3 */
#ifdef _TIM4
TIM4 = (TIM_TypeDef *) TIM4_BASE;
#endif /*_TIM4 */
#ifdef _TIM5
TIM5 = (TIM_TypeDef *) TIM5_BASE;
#endif /*_TIM5 */
#ifdef _TIM6
TIM6 = (TIM_TypeDef *) TIM6_BASE;
#endif /*_TIM6 */
#ifdef _TIM7
TIM7 = (TIM_TypeDef *) TIM7_BASE;
#endif /*_TIM7 */
#ifdef _TIM8
TIM8 = (TIM_TypeDef *) TIM8_BASE;
#endif /*_TIM8 */
/************************************* USART **********************************/
#ifdef _USART1
USART1 = (USART_TypeDef *) USART1_BASE;
#endif /*_USART1 */
#ifdef _USART2
USART2 = (USART_TypeDef *) USART2_BASE;
#endif /*_USART2 */
#ifdef _USART3
USART3 = (USART_TypeDef *) USART3_BASE;
#endif /*_USART3 */
#ifdef _UART4
UART4 = (USART_TypeDef *) UART4_BASE;
#endif /*_UART4 */
#ifdef _UART5
UART5 = (USART_TypeDef *) UART5_BASE;
#endif /*_UART5 */
/************************************* WWDG ***********************************/
#ifdef _WWDG
WWDG = (WWDG_TypeDef *) WWDG_BASE;
#endif /*_WWDG */
}
#endif /* DEBUG*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

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src/platform/stm32/FWLib/library/src/stm32f10x_nvic.c
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@ -1,751 +0,0 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_nvic.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the NVIC firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_nvic.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define AIRCR_VECTKEY_MASK ((u32)0x05FA0000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : NVIC_DeInit
* Description : Deinitializes the NVIC peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_DeInit(void)
{
u32 index = 0;
NVIC->ICER[0] = 0xFFFFFFFF;
NVIC->ICER[1] = 0x0FFFFFFF;
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICPR[1] = 0x0FFFFFFF;
for(index = 0; index < 0x0F; index++)
{
NVIC->IPR[index] = 0x00000000;
}
}
/*******************************************************************************
* Function Name : NVIC_SCBDeInit
* Description : Deinitializes the SCB peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SCBDeInit(void)
{
u32 index = 0x00;
SCB->ICSR = 0x0A000000;
SCB->VTOR = 0x00000000;
SCB->AIRCR = AIRCR_VECTKEY_MASK;
SCB->SCR = 0x00000000;
SCB->CCR = 0x00000000;
for(index = 0; index < 0x03; index++)
{
SCB->SHPR[index] = 0;
}
SCB->SHCSR = 0x00000000;
SCB->CFSR = 0xFFFFFFFF;
SCB->HFSR = 0xFFFFFFFF;
SCB->DFSR = 0xFFFFFFFF;
}
/*******************************************************************************
* Function Name : NVIC_PriorityGroupConfig
* Description : Configures the priority grouping: pre-emption priority
* and subpriority.
* Input : - NVIC_PriorityGroup: specifies the priority grouping bits
* length. This parameter can be one of the following values:
* - NVIC_PriorityGroup_0: 0 bits for pre-emption priority
* 4 bits for subpriority
* - NVIC_PriorityGroup_1: 1 bits for pre-emption priority
* 3 bits for subpriority
* - NVIC_PriorityGroup_2: 2 bits for pre-emption priority
* 2 bits for subpriority
* - NVIC_PriorityGroup_3: 3 bits for pre-emption priority
* 1 bits for subpriority
* - NVIC_PriorityGroup_4: 4 bits for pre-emption priority
* 0 bits for subpriority
* Output : None
* Return : None
*******************************************************************************/
void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
}
/*******************************************************************************
* Function Name : NVIC_Init
* Description : Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct.
* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure
* that contains the configuration information for the
* specified NVIC peripheral.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00;
u32 tmppre = 0, tmpsub = 0x0F;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority --------------------------------*/
tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08;
tmppre = (0x4 - tmppriority);
tmpsub = tmpsub >> tmppriority;
tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
tmppriority = tmppriority << 0x04;
tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
tmpreg = NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)];
tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
tmpreg &= ~tmpmask;
tmppriority &= tmpmask;
tmpreg |= tmppriority;
NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg;
/* Enable the Selected IRQ Channels --------------------------------------*/
NVIC->ISER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
(u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
}
else
{
/* Disable the Selected IRQ Channels -------------------------------------*/
NVIC->ICER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
(u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
}
}
/*******************************************************************************
* Function Name : NVIC_StructInit
* Description : Fills each NVIC_InitStruct member with its default value.
* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure which
* will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct)
{
/* NVIC_InitStruct members default value */
NVIC_InitStruct->NVIC_IRQChannel = 0x00;
NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00;
NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00;
NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE;
}
/*******************************************************************************
* Function Name : NVIC_SETPRIMASK
* Description : Enables the PRIMASK priority: Raises the execution priority to 0.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SETPRIMASK(void)
{
__SETPRIMASK();
}
/*******************************************************************************
* Function Name : NVIC_RESETPRIMASK
* Description : Disables the PRIMASK priority.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_RESETPRIMASK(void)
{
__RESETPRIMASK();
}
/*******************************************************************************
* Function Name : NVIC_SETFAULTMASK
* Description : Enables the FAULTMASK priority: Raises the execution priority to -1.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SETFAULTMASK(void)
{
__SETFAULTMASK();
}
/*******************************************************************************
* Function Name : NVIC_RESETFAULTMASK
* Description : Disables the FAULTMASK priority.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_RESETFAULTMASK(void)
{
__RESETFAULTMASK();
}
/*******************************************************************************
* Function Name : NVIC_BASEPRICONFIG
* Description : The execution priority can be changed from 15 (lowest
configurable priority) to 1. Writing a zero value will disable
* the mask of execution priority.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_BASEPRICONFIG(u32 NewPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_BASE_PRI(NewPriority));
__BASEPRICONFIG(NewPriority << 0x04);
}
/*******************************************************************************
* Function Name : NVIC_GetBASEPRI
* Description : Returns the BASEPRI mask value.
* Input : None
* Output : None
* Return : BASEPRI register value
*******************************************************************************/
u32 NVIC_GetBASEPRI(void)
{
return (__GetBASEPRI());
}
/*******************************************************************************
* Function Name : NVIC_GetCurrentPendingIRQChannel
* Description : Returns the current pending IRQ channel identifier.
* Input : None
* Output : None
* Return : Pending IRQ Channel Identifier.
*******************************************************************************/
u16 NVIC_GetCurrentPendingIRQChannel(void)
{
return ((u16)((SCB->ICSR & (u32)0x003FF000) >> 0x0C));
}
/*******************************************************************************
* Function Name : NVIC_GetIRQChannelPendingBitStatus
* Description : Checks whether the specified IRQ Channel pending bit is set
* or not.
* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to check.
* Output : None
* Return : The new state of IRQ Channel pending bit(SET or RESET).
*******************************************************************************/
ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel)
{
ITStatus pendingirqstatus = RESET;
u32 tmp = 0x00;
/* Check the parameters */
assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
if (((NVIC->ISPR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp)
{
pendingirqstatus = SET;
}
else
{
pendingirqstatus = RESET;
}
return pendingirqstatus;
}
/*******************************************************************************
* Function Name : NVIC_SetIRQChannelPendingBit
* Description : Sets the NVIC's interrupt pending bit.
* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to Set.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel)
{
/* Check the parameters */
assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
*(vu32*) 0xE000EF00 = (u32)NVIC_IRQChannel;
}
/*******************************************************************************
* Function Name : NVIC_ClearIRQChannelPendingBit
* Description : Clears the NVIC's interrupt pending bit.
* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to clear.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel)
{
/* Check the parameters */
assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
NVIC->ICPR[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F);
}
/*******************************************************************************
* Function Name : NVIC_GetCurrentActiveHandler
* Description : Returns the current active Handler (IRQ Channel and
* SystemHandler) identifier.
* Input : None
* Output : None
* Return : Active Handler Identifier.
*******************************************************************************/
u16 NVIC_GetCurrentActiveHandler(void)
{
return ((u16)(SCB->ICSR & (u32)0x3FF));
}
/*******************************************************************************
* Function Name : NVIC_GetIRQChannelActiveBitStatus
* Description : Checks whether the specified IRQ Channel active bit is set
* or not.
* Input : - NVIC_IRQChannel: specifies the interrupt active bit to check.
* Output : None
* Return : The new state of IRQ Channel active bit(SET or RESET).
*******************************************************************************/
ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel)
{
ITStatus activeirqstatus = RESET;
u32 tmp = 0x00;
/* Check the parameters */
assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
if (((NVIC->IABR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp )
{
activeirqstatus = SET;
}
else
{
activeirqstatus = RESET;
}
return activeirqstatus;
}
/*******************************************************************************
* Function Name : NVIC_GetCPUID
* Description : Returns the ID number, the version number and the implementation
* details of the Cortex-M3 core.
* Input : None
* Output : None
* Return : CPU ID.
*******************************************************************************/
u32 NVIC_GetCPUID(void)
{
return (SCB->CPUID);
}
/*******************************************************************************
* Function Name : NVIC_SetVectorTable
* Description : Sets the vector table location and Offset.
* Input : - NVIC_VectTab: specifies if the vector table is in RAM or
* FLASH memory.
* This parameter can be one of the following values:
* - NVIC_VectTab_RAM
* - NVIC_VectTab_FLASH
* - Offset: Vector Table base offset field.
* This value must be a multiple of 0x100.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)
{
/* Check the parameters */
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
assert_param(IS_NVIC_OFFSET(Offset));
SCB->VTOR = NVIC_VectTab | (Offset & (u32)0x1FFFFF80);
}
/*******************************************************************************
* Function Name : NVIC_GenerateSystemReset
* Description : Generates a system reset.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_GenerateSystemReset(void)
{
SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x04;
}
/*******************************************************************************
* Function Name : NVIC_GenerateCoreReset
* Description : Generates a Core (Core + NVIC) reset.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_GenerateCoreReset(void)
{
SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x01;
}
/*******************************************************************************
* Function Name : NVIC_SystemLPConfig
* Description : Selects the condition for the system to enter low power mode.
* Input : - LowPowerMode: Specifies the new mode for the system to enter
* low power mode.
* This parameter can be one of the following values:
* - NVIC_LP_SEVONPEND
* - NVIC_LP_SLEEPDEEP
* - NVIC_LP_SLEEPONEXIT
* - NewState: new state of LP condition.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_NVIC_LP(LowPowerMode));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SCB->SCR |= LowPowerMode;
}
else
{
SCB->SCR &= (u32)(~(u32)LowPowerMode);
}
}
/*******************************************************************************
* Function Name : NVIC_SystemHandlerConfig
* Description : Enables or disables the specified System Handlers.
* Input : - SystemHandler: specifies the system handler to be enabled
* or disabled.
* This parameter can be one of the following values:
* - SystemHandler_MemoryManage
* - SystemHandler_BusFault
* - SystemHandler_UsageFault
* - NewState: new state of specified System Handlers.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState)
{
u32 tmpreg = 0x00;
/* Check the parameters */
assert_param(IS_CONFIG_SYSTEM_HANDLER(SystemHandler));
assert_param(IS_FUNCTIONAL_STATE(NewState));
tmpreg = (u32)0x01 << (SystemHandler & (u32)0x1F);
if (NewState != DISABLE)
{
SCB->SHCSR |= tmpreg;
}
else
{
SCB->SHCSR &= ~tmpreg;
}
}
/*******************************************************************************
* Function Name : NVIC_SystemHandlerPriorityConfig
* Description : Configures the specified System Handlers priority.
* Input : - SystemHandler: specifies the system handler to be
* enabled or disabled.
* This parameter can be one of the following values:
* - SystemHandler_MemoryManage
* - SystemHandler_BusFault
* - SystemHandler_UsageFault
* - SystemHandler_SVCall
* - SystemHandler_DebugMonitor
* - SystemHandler_PSV
* - SystemHandler_SysTick
* - SystemHandlerPreemptionPriority: new priority group of the
* specified system handlers.
* - SystemHandlerSubPriority: new sub priority of the specified
* system handlers.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
u8 SystemHandlerSubPriority)
{
u32 tmp1 = 0x00, tmp2 = 0xFF, handlermask = 0x00;
u32 tmppriority = 0x00;
/* Check the parameters */
assert_param(IS_PRIORITY_SYSTEM_HANDLER(SystemHandler));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(SystemHandlerPreemptionPriority));
assert_param(IS_NVIC_SUB_PRIORITY(SystemHandlerSubPriority));
tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08;
tmp1 = (0x4 - tmppriority);
tmp2 = tmp2 >> tmppriority;
tmppriority = (u32)SystemHandlerPreemptionPriority << tmp1;
tmppriority |= SystemHandlerSubPriority & tmp2;
tmppriority = tmppriority << 0x04;
tmp1 = SystemHandler & (u32)0xC0;
tmp1 = tmp1 >> 0x06;
tmp2 = (SystemHandler >> 0x08) & (u32)0x03;
tmppriority = tmppriority << (tmp2 * 0x08);
handlermask = (u32)0xFF << (tmp2 * 0x08);
SCB->SHPR[tmp1] &= ~handlermask;
SCB->SHPR[tmp1] |= tmppriority;
}
/*******************************************************************************
* Function Name : NVIC_GetSystemHandlerPendingBitStatus
* Description : Checks whether the specified System handlers pending bit is
* set or not.
* Input : - SystemHandler: specifies the system handler pending bit to
* check.
* This parameter can be one of the following values:
* - SystemHandler_MemoryManage
* - SystemHandler_BusFault
* - SystemHandler_SVCall
* Output : None
* Return : The new state of System Handler pending bit(SET or RESET).
*******************************************************************************/
ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler)
{
ITStatus bitstatus = RESET;
u32 tmp = 0x00, tmppos = 0x00;
/* Check the parameters */
assert_param(IS_GET_PENDING_SYSTEM_HANDLER(SystemHandler));
tmppos = (SystemHandler >> 0x0A);
tmppos &= (u32)0x0F;
tmppos = (u32)0x01 << tmppos;
tmp = SCB->SHCSR & tmppos;
if (tmp == tmppos)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : NVIC_SetSystemHandlerPendingBit
* Description : Sets System Handler pending bit.
* Input : - SystemHandler: specifies the system handler pending bit
* to be set.
* This parameter can be one of the following values:
* - SystemHandler_NMI
* - SystemHandler_PSV
* - SystemHandler_SysTick
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler)
{
u32 tmp = 0x00;
/* Check the parameters */
assert_param(IS_SET_PENDING_SYSTEM_HANDLER(SystemHandler));
/* Get the System Handler pending bit position */
tmp = SystemHandler & (u32)0x1F;
/* Set the corresponding System Handler pending bit */
SCB->ICSR |= ((u32)0x01 << tmp);
}
/*******************************************************************************
* Function Name : NVIC_ClearSystemHandlerPendingBit
* Description : Clears System Handler pending bit.
* Input : - SystemHandler: specifies the system handler pending bit to
* be clear.
* This parameter can be one of the following values:
* - SystemHandler_PSV
* - SystemHandler_SysTick
* Output : None
* Return : None
*******************************************************************************/
void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler)
{
u32 tmp = 0x00;
/* Check the parameters */
assert_param(IS_CLEAR_SYSTEM_HANDLER(SystemHandler));
/* Get the System Handler pending bit position */
tmp = SystemHandler & (u32)0x1F;
/* Clear the corresponding System Handler pending bit */
SCB->ICSR |= ((u32)0x01 << (tmp - 0x01));
}
/*******************************************************************************
* Function Name : NVIC_GetSystemHandlerActiveBitStatus
* Description : Checks whether the specified System handlers active bit is
* set or not.
* Input : - SystemHandler: specifies the system handler active bit to
* check.
* This parameter can be one of the following values:
* - SystemHandler_MemoryManage
* - SystemHandler_BusFault
* - SystemHandler_UsageFault
* - SystemHandler_SVCall
* - SystemHandler_DebugMonitor
* - SystemHandler_PSV
* - SystemHandler_SysTick
* Output : None
* Return : The new state of System Handler active bit(SET or RESET).
*******************************************************************************/
ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler)
{
ITStatus bitstatus = RESET;
u32 tmp = 0x00, tmppos = 0x00;
/* Check the parameters */
assert_param(IS_GET_ACTIVE_SYSTEM_HANDLER(SystemHandler));
tmppos = (SystemHandler >> 0x0E) & (u32)0x0F;
tmppos = (u32)0x01 << tmppos;
tmp = SCB->SHCSR & tmppos;
if (tmp == tmppos)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : NVIC_GetFaultHandlerSources
* Description : Returns the system fault handlers sources.
* Input : - SystemHandler: specifies the system handler to get its fault
* sources.
* This parameter can be one of the following values:
* - SystemHandler_HardFault
* - SystemHandler_MemoryManage
* - SystemHandler_BusFault
* - SystemHandler_UsageFault
* - SystemHandler_DebugMonitor
* Output : None
* Return : Source of the fault handler.
*******************************************************************************/
u32 NVIC_GetFaultHandlerSources(u32 SystemHandler)
{
u32 faultsources = 0x00;
u32 tmpreg = 0x00, tmppos = 0x00;
/* Check the parameters */
assert_param(IS_FAULT_SOURCE_SYSTEM_HANDLER(SystemHandler));
tmpreg = (SystemHandler >> 0x12) & (u32)0x03;
tmppos = (SystemHandler >> 0x14) & (u32)0x03;
if (tmpreg == 0x00)
{
faultsources = SCB->HFSR;
}
else if (tmpreg == 0x01)
{
faultsources = SCB->CFSR >> (tmppos * 0x08);
if (tmppos != 0x02)
{
faultsources &= (u32)0x0F;
}
else
{
faultsources &= (u32)0xFF;
}
}
else
{
faultsources = SCB->DFSR;
}
return faultsources;
}
/*******************************************************************************
* Function Name : NVIC_GetFaultAddress
* Description : Returns the address of the location that generated a fault
* handler.
* Input : - SystemHandler: specifies the system handler to get its
* fault address.
* This parameter can be one of the following values:
* - SystemHandler_MemoryManage
* - SystemHandler_BusFault
* Output : None
* Return : Fault address.
*******************************************************************************/
u32 NVIC_GetFaultAddress(u32 SystemHandler)
{
u32 faultaddress = 0x00;
u32 tmp = 0x00;
/* Check the parameters */
assert_param(IS_FAULT_ADDRESS_SYSTEM_HANDLER(SystemHandler));
tmp = (SystemHandler >> 0x16) & (u32)0x01;
if (tmp == 0x00)
{
faultaddress = SCB->MMFAR;
}
else
{
faultaddress = SCB->BFAR;
}
return faultaddress;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

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@ -1,280 +1,311 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_pwr.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the PWR firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* --------- PWR registers bit address in the alias region ---------- */
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of DBP bit */
#define CR_OFFSET (PWR_OFFSET + 0x00)
#define DBP_BitNumber 0x08
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
/* Alias word address of PVDE bit */
#define PVDE_BitNumber 0x04
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of EWUP bit */
#define CSR_OFFSET (PWR_OFFSET + 0x04)
#define EWUP_BitNumber 0x08
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
/* ------------------ PWR registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_PDDS_Set ((u32)0x00000002)
#define CR_DS_Mask ((u32)0xFFFFFFFC)
#define CR_CWUF_Set ((u32)0x00000004)
#define CR_PLS_Mask ((u32)0xFFFFFF1F)
/* --------- Cortex System Control register bit mask ---------------- */
/* Cortex System Control register address */
#define SCB_SysCtrl ((u32)0xE000ED10)
/* SLEEPDEEP bit mask */
#define SysCtrl_SLEEPDEEP_Set ((u32)0x00000004)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : PWR_DeInit
* Description : Deinitializes the PWR peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void PWR_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
}
/*******************************************************************************
* Function Name : PWR_BackupAccessCmd
* Description : Enables or disables access to the RTC and backup registers.
* Input : - NewState: new state of the access to the RTC and backup
* registers. This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void PWR_BackupAccessCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_DBP_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : PWR_PVDCmd
* Description : Enables or disables the Power Voltage Detector(PVD).
* Input : - NewState: new state of the PVD.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void PWR_PVDCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_PVDE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : PWR_PVDLevelConfig
* Description : Configures the voltage threshold detected by the Power Voltage
* Detector(PVD).
* Input : - PWR_PVDLevel: specifies the PVD detection level
* This parameter can be one of the following values:
* - PWR_PVDLevel_2V2: PVD detection level set to 2.2V
* - PWR_PVDLevel_2V3: PVD detection level set to 2.3V
* - PWR_PVDLevel_2V4: PVD detection level set to 2.4V
* - PWR_PVDLevel_2V5: PVD detection level set to 2.5V
* - PWR_PVDLevel_2V6: PVD detection level set to 2.6V
* - PWR_PVDLevel_2V7: PVD detection level set to 2.7V
* - PWR_PVDLevel_2V8: PVD detection level set to 2.8V
* - PWR_PVDLevel_2V9: PVD detection level set to 2.9V
* Output : None
* Return : None
*******************************************************************************/
void PWR_PVDLevelConfig(u32 PWR_PVDLevel)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
tmpreg = PWR->CR;
/* Clear PLS[7:5] bits */
tmpreg &= CR_PLS_Mask;
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
tmpreg |= PWR_PVDLevel;
/* Store the new value */
PWR->CR = tmpreg;
}
/*******************************************************************************
* Function Name : PWR_WakeUpPinCmd
* Description : Enables or disables the WakeUp Pin functionality.
* Input : - NewState: new state of the WakeUp Pin functionality.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void PWR_WakeUpPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CSR_EWUP_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : PWR_EnterSTOPMode
* Description : Enters STOP mode.
* Input : - PWR_Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* - PWR_Regulator_ON: STOP mode with regulator ON
* - PWR_Regulator_LowPower: STOP mode with
* regulator in low power mode
* - PWR_STOPEntry: specifies if STOP mode in entered with WFI or
* WFE instruction.
* This parameter can be one of the following values:
* - PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
* - PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
* Output : None
* Return : None
*******************************************************************************/
void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDS bits */
tmpreg &= CR_DS_Mask;
/* Set LPDS bit according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
*(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
}
/*******************************************************************************
* Function Name : PWR_EnterSTANDBYMode
* Description : Enters STANDBY mode.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void PWR_EnterSTANDBYMode(void)
{
/* Clear Wake-up flag */
PWR->CR |= CR_CWUF_Set;
/* Select STANDBY mode */
PWR->CR |= CR_PDDS_Set;
/* Set SLEEPDEEP bit of Cortex System Control Register */
*(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
/* Request Wait For Interrupt */
__WFI();
}
/*******************************************************************************
* Function Name : PWR_GetFlagStatus
* Description : Checks whether the specified PWR flag is set or not.
* Input : - PWR_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - PWR_FLAG_WU: Wake Up flag
* - PWR_FLAG_SB: StandBy flag
* - PWR_FLAG_PVDO: PVD Output
* Output : None
* Return : The new state of PWR_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
if ((PWR->CSR & PWR_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/*******************************************************************************
* Function Name : PWR_ClearFlag
* Description : Clears the PWR's pending flags.
* Input : - PWR_FLAG: specifies the flag to clear.
* This parameter can be one of the following values:
* - PWR_FLAG_WU: Wake Up flag
* - PWR_FLAG_SB: StandBy flag
* Output : None
* Return : None
*******************************************************************************/
void PWR_ClearFlag(u32 PWR_FLAG)
{
/* Check the parameters */
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
PWR->CR |= PWR_FLAG << 2;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f10x_pwr.c
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file provides all the PWR firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup PWR
* @brief PWR driver modules
* @{
*/
/** @defgroup PWR_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Private_Defines
* @{
*/
/* --------- PWR registers bit address in the alias region ---------- */
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of DBP bit */
#define CR_OFFSET (PWR_OFFSET + 0x00)
#define DBP_BitNumber 0x08
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
/* Alias word address of PVDE bit */
#define PVDE_BitNumber 0x04
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of EWUP bit */
#define CSR_OFFSET (PWR_OFFSET + 0x04)
#define EWUP_BitNumber 0x08
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
/* ------------------ PWR registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_PDDS_Set ((uint32_t)0x00000002)
#define CR_DS_Mask ((uint32_t)0xFFFFFFFC)
#define CR_CWUF_Set ((uint32_t)0x00000004)
#define CR_PLS_Mask ((uint32_t)0xFFFFFF1F)
/* --------- Cortex System Control register bit mask ---------------- */
/* Cortex System Control register address */
#define SCB_SysCtrl ((uint32_t)0xE000ED10)
/* SLEEPDEEP bit mask */
#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004)
/**
* @}
*/
/** @defgroup PWR_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Private_Functions
* @{
*/
/**
* @brief Deinitializes the PWR peripheral registers to their default reset values.
* @param None
* @retval None
*/
void PWR_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
}
/**
* @brief Enables or disables access to the RTC and backup registers.
* @param NewState: new state of the access to the RTC and backup registers.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_BackupAccessCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
}
/**
* @brief Enables or disables the Power Voltage Detector(PVD).
* @param NewState: new state of the PVD.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_PVDCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
}
/**
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
* @param PWR_PVDLevel: specifies the PVD detection level
* This parameter can be one of the following values:
* @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
* @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
* @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
* @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
* @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
* @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
* @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
* @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
* @retval None
*/
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
tmpreg = PWR->CR;
/* Clear PLS[7:5] bits */
tmpreg &= CR_PLS_Mask;
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
tmpreg |= PWR_PVDLevel;
/* Store the new value */
PWR->CR = tmpreg;
}
/**
* @brief Enables or disables the WakeUp Pin functionality.
* @param NewState: new state of the WakeUp Pin functionality.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_WakeUpPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
}
/**
* @brief Enters STOP mode.
* @param PWR_Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PWR_Regulator_ON: STOP mode with regulator ON
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
* @retval None
*/
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDS bits */
tmpreg &= CR_DS_Mask;
/* Set LPDS bit according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
*(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
}
/**
* @brief Enters STANDBY mode.
* @param None
* @retval None
*/
void PWR_EnterSTANDBYMode(void)
{
/* Clear Wake-up flag */
PWR->CR |= CR_CWUF_Set;
/* Select STANDBY mode */
PWR->CR |= CR_PDDS_Set;
/* Set SLEEPDEEP bit of Cortex System Control Register */
*(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM )
__force_stores();
#endif
/* Request Wait For Interrupt */
__WFI();
}
/**
* @brief Checks whether the specified PWR flag is set or not.
* @param PWR_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag
* @arg PWR_FLAG_PVDO: PVD Output
* @retval The new state of PWR_FLAG (SET or RESET).
*/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/**
* @brief Clears the PWR's pending flags.
* @param PWR_FLAG: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag
* @retval None
*/
void PWR_ClearFlag(uint32_t PWR_FLAG)
{
/* Check the parameters */
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
PWR->CR |= PWR_FLAG << 2;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_rtc.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the RTC firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_rtc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define CRL_CNF_Set ((u16)0x0010) /* Configuration Flag Enable Mask */
#define CRL_CNF_Reset ((u16)0xFFEF) /* Configuration Flag Disable Mask */
#define RTC_LSB_Mask ((u32)0x0000FFFF) /* RTC LSB Mask */
#define PRLH_MSB_Mask ((u32)0x000F0000) /* RTC Prescaler MSB Mask */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : RTC_ITConfig
* Description : Enables or disables the specified RTC interrupts.
* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled
* or disabled.
* This parameter can be any combination of the following values:
* - RTC_IT_OW: Overflow interrupt
* - RTC_IT_ALR: Alarm interrupt
* - RTC_IT_SEC: Second interrupt
* - NewState: new state of the specified RTC interrupts.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_RTC_IT(RTC_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
RTC->CRH |= RTC_IT;
}
else
{
RTC->CRH &= (u16)~RTC_IT;
}
}
/*******************************************************************************
* Function Name : RTC_EnterConfigMode
* Description : Enters the RTC configuration mode.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTC_EnterConfigMode(void)
{
/* Set the CNF flag to enter in the Configuration Mode */
RTC->CRL |= CRL_CNF_Set;
}
/*******************************************************************************
* Function Name : RTC_ExitConfigMode
* Description : Exits from the RTC configuration mode.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTC_ExitConfigMode(void)
{
/* Reset the CNF flag to exit from the Configuration Mode */
RTC->CRL &= CRL_CNF_Reset;
}
/*******************************************************************************
* Function Name : RTC_GetCounter
* Description : Gets the RTC counter value.
* Input : None
* Output : None
* Return : RTC counter value.
*******************************************************************************/
u32 RTC_GetCounter(void)
{
u16 tmp = 0;
tmp = RTC->CNTL;
return (((u32)RTC->CNTH << 16 ) | tmp) ;
}
/*******************************************************************************
* Function Name : RTC_SetCounter
* Description : Sets the RTC counter value.
* Input : - CounterValue: RTC counter new value.
* Output : None
* Return : None
*******************************************************************************/
void RTC_SetCounter(u32 CounterValue)
{
RTC_EnterConfigMode();
/* Set RTC COUNTER MSB word */
RTC->CNTH = CounterValue >> 16;
/* Set RTC COUNTER LSB word */
RTC->CNTL = (CounterValue & RTC_LSB_Mask);
RTC_ExitConfigMode();
}
/*******************************************************************************
* Function Name : RTC_SetPrescaler
* Description : Sets the RTC prescaler value.
* Input : - PrescalerValue: RTC prescaler new value.
* Output : None
* Return : None
*******************************************************************************/
void RTC_SetPrescaler(u32 PrescalerValue)
{
/* Check the parameters */
assert_param(IS_RTC_PRESCALER(PrescalerValue));
RTC_EnterConfigMode();
/* Set RTC PRESCALER MSB word */
RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16;
/* Set RTC PRESCALER LSB word */
RTC->PRLL = (PrescalerValue & RTC_LSB_Mask);
RTC_ExitConfigMode();
}
/*******************************************************************************
* Function Name : RTC_SetAlarm
* Description : Sets the RTC alarm value.
* Input : - AlarmValue: RTC alarm new value.
* Output : None
* Return : None
*******************************************************************************/
void RTC_SetAlarm(u32 AlarmValue)
{
RTC_EnterConfigMode();
/* Set the ALARM MSB word */
RTC->ALRH = AlarmValue >> 16;
/* Set the ALARM LSB word */
RTC->ALRL = (AlarmValue & RTC_LSB_Mask);
RTC_ExitConfigMode();
}
/*******************************************************************************
* Function Name : RTC_GetDivider
* Description : Gets the RTC divider value.
* Input : None
* Output : None
* Return : RTC Divider value.
*******************************************************************************/
u32 RTC_GetDivider(void)
{
u32 tmp = 0x00;
tmp = ((u32)RTC->DIVH & (u32)0x000F) << 16;
tmp |= RTC->DIVL;
return tmp;
}
/*******************************************************************************
* Function Name : RTC_WaitForLastTask
* Description : Waits until last write operation on RTC registers has finished.
* This function must be called before any write to RTC registers.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTC_WaitForLastTask(void)
{
/* Loop until RTOFF flag is set */
while ((RTC->CRL & RTC_FLAG_RTOFF) == (u16)RESET)
{
}
}
/*******************************************************************************
* Function Name : RTC_WaitForSynchro
* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
* are synchronized with RTC APB clock.
* This function must be called before any read operation after
* an APB reset or an APB clock stop.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTC_WaitForSynchro(void)
{
/* Clear RSF flag */
RTC->CRL &= (u16)~RTC_FLAG_RSF;
/* Loop until RSF flag is set */
while ((RTC->CRL & RTC_FLAG_RSF) == (u16)RESET)
{
}
}
/*******************************************************************************
* Function Name : RTC_GetFlagStatus
* Description : Checks whether the specified RTC flag is set or not.
* Input : - RTC_FLAG: specifies the flag to check.
* This parameter can be one the following values:
* - RTC_FLAG_RTOFF: RTC Operation OFF flag
* - RTC_FLAG_RSF: Registers Synchronized flag
* - RTC_FLAG_OW: Overflow flag
* - RTC_FLAG_ALR: Alarm flag
* - RTC_FLAG_SEC: Second flag
* Output : None
* Return : The new state of RTC_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
if ((RTC->CRL & RTC_FLAG) != (u16)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : RTC_ClearFlag
* Description : Clears the RTC's pending flags.
* Input : - RTC_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* - RTC_FLAG_RSF: Registers Synchronized flag. This flag
* is cleared only after an APB reset or an APB Clock stop.
* - RTC_FLAG_OW: Overflow flag
* - RTC_FLAG_ALR: Alarm flag
* - RTC_FLAG_SEC: Second flag
* Output : None
* Return : None
*******************************************************************************/
void RTC_ClearFlag(u16 RTC_FLAG)
{
/* Check the parameters */
assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
/* Clear the coressponding RTC flag */
RTC->CRL &= (u16)~RTC_FLAG;
}
/*******************************************************************************
* Function Name : RTC_GetITStatus
* Description : Checks whether the specified RTC interrupt has occured or not.
* Input : - RTC_IT: specifies the RTC interrupts sources to check.
* This parameter can be one of the following values:
* - RTC_IT_OW: Overflow interrupt
* - RTC_IT_ALR: Alarm interrupt
* - RTC_IT_SEC: Second interrupt
* Output : None
* Return : The new state of the RTC_IT (SET or RESET).
*******************************************************************************/
ITStatus RTC_GetITStatus(u16 RTC_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_RTC_GET_IT(RTC_IT));
bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
if (((RTC->CRH & RTC_IT) != (u16)RESET) && (bitstatus != (u16)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : RTC_ClearITPendingBit
* Description : Clears the RTC's interrupt pending bits.
* Input : - RTC_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* - RTC_IT_OW: Overflow interrupt
* - RTC_IT_ALR: Alarm interrupt
* - RTC_IT_SEC: Second interrupt
* Output : None
* Return : None
*******************************************************************************/
void RTC_ClearITPendingBit(u16 RTC_IT)
{
/* Check the parameters */
assert_param(IS_RTC_IT(RTC_IT));
/* Clear the coressponding RTC pending bit */
RTC->CRL &= (u16)~RTC_IT;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f10x_rtc.c
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file provides all the RTC firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_rtc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup RTC
* @brief RTC driver modules
* @{
*/
/** @defgroup RTC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup RTC_Private_Defines
* @{
*/
#define CRL_CNF_Set ((uint16_t)0x0010) /*!< Configuration Flag Enable Mask */
#define CRL_CNF_Reset ((uint16_t)0xFFEF) /*!< Configuration Flag Disable Mask */
#define RTC_LSB_Mask ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
#define PRLH_MSB_Mask ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
/**
* @}
*/
/** @defgroup RTC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup RTC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup RTC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup RTC_Private_Functions
* @{
*/
/**
* @brief Enables or disables the specified RTC interrupts.
* @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_OW: Overflow interrupt
* @arg RTC_IT_ALR: Alarm interrupt
* @arg RTC_IT_SEC: Second interrupt
* @param NewState: new state of the specified RTC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_RTC_IT(RTC_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
RTC->CRH |= RTC_IT;
}
else
{
RTC->CRH &= (uint16_t)~RTC_IT;
}
}
/**
* @brief Enters the RTC configuration mode.
* @param None
* @retval None
*/
void RTC_EnterConfigMode(void)
{
/* Set the CNF flag to enter in the Configuration Mode */
RTC->CRL |= CRL_CNF_Set;
}
/**
* @brief Exits from the RTC configuration mode.
* @param None
* @retval None
*/
void RTC_ExitConfigMode(void)
{
/* Reset the CNF flag to exit from the Configuration Mode */
RTC->CRL &= CRL_CNF_Reset;
}
/**
* @brief Gets the RTC counter value.
* @param None
* @retval RTC counter value.
*/
uint32_t RTC_GetCounter(void)
{
uint16_t tmp = 0;
tmp = RTC->CNTL;
return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
}
/**
* @brief Sets the RTC counter value.
* @param CounterValue: RTC counter new value.
* @retval None
*/
void RTC_SetCounter(uint32_t CounterValue)
{
RTC_EnterConfigMode();
/* Set RTC COUNTER MSB word */
RTC->CNTH = CounterValue >> 16;
/* Set RTC COUNTER LSB word */
RTC->CNTL = (CounterValue & RTC_LSB_Mask);
RTC_ExitConfigMode();
}
/**
* @brief Sets the RTC prescaler value.
* @param PrescalerValue: RTC prescaler new value.
* @retval None
*/
void RTC_SetPrescaler(uint32_t PrescalerValue)
{
/* Check the parameters */
assert_param(IS_RTC_PRESCALER(PrescalerValue));
RTC_EnterConfigMode();
/* Set RTC PRESCALER MSB word */
RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16;
/* Set RTC PRESCALER LSB word */
RTC->PRLL = (PrescalerValue & RTC_LSB_Mask);
RTC_ExitConfigMode();
}
/**
* @brief Sets the RTC alarm value.
* @param AlarmValue: RTC alarm new value.
* @retval None
*/
void RTC_SetAlarm(uint32_t AlarmValue)
{
RTC_EnterConfigMode();
/* Set the ALARM MSB word */
RTC->ALRH = AlarmValue >> 16;
/* Set the ALARM LSB word */
RTC->ALRL = (AlarmValue & RTC_LSB_Mask);
RTC_ExitConfigMode();
}
/**
* @brief Gets the RTC divider value.
* @param None
* @retval RTC Divider value.
*/
uint32_t RTC_GetDivider(void)
{
uint32_t tmp = 0x00;
tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
tmp |= RTC->DIVL;
return tmp;
}
/**
* @brief Waits until last write operation on RTC registers has finished.
* @note This function must be called before any write to RTC registers.
* @param None
* @retval None
*/
void RTC_WaitForLastTask(void)
{
/* Loop until RTOFF flag is set */
while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
{
}
}
/**
* @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
* are synchronized with RTC APB clock.
* @note This function must be called before any read operation after an APB reset
* or an APB clock stop.
* @param None
* @retval None
*/
void RTC_WaitForSynchro(void)
{
/* Clear RSF flag */
RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
/* Loop until RSF flag is set */
while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
{
}
}
/**
* @brief Checks whether the specified RTC flag is set or not.
* @param RTC_FLAG: specifies the flag to check.
* This parameter can be one the following values:
* @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
* @arg RTC_FLAG_RSF: Registers Synchronized flag
* @arg RTC_FLAG_OW: Overflow flag
* @arg RTC_FLAG_ALR: Alarm flag
* @arg RTC_FLAG_SEC: Second flag
* @retval The new state of RTC_FLAG (SET or RESET).
*/
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the RTC<EFBFBD>s pending flags.
* @param RTC_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
* an APB reset or an APB Clock stop.
* @arg RTC_FLAG_OW: Overflow flag
* @arg RTC_FLAG_ALR: Alarm flag
* @arg RTC_FLAG_SEC: Second flag
* @retval None
*/
void RTC_ClearFlag(uint16_t RTC_FLAG)
{
/* Check the parameters */
assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
/* Clear the coressponding RTC flag */
RTC->CRL &= (uint16_t)~RTC_FLAG;
}
/**
* @brief Checks whether the specified RTC interrupt has occured or not.
* @param RTC_IT: specifies the RTC interrupts sources to check.
* This parameter can be one of the following values:
* @arg RTC_IT_OW: Overflow interrupt
* @arg RTC_IT_ALR: Alarm interrupt
* @arg RTC_IT_SEC: Second interrupt
* @retval The new state of the RTC_IT (SET or RESET).
*/
ITStatus RTC_GetITStatus(uint16_t RTC_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_RTC_GET_IT(RTC_IT));
bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the RTC<EFBFBD>s interrupt pending bits.
* @param RTC_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg RTC_IT_OW: Overflow interrupt
* @arg RTC_IT_ALR: Alarm interrupt
* @arg RTC_IT_SEC: Second interrupt
* @retval None
*/
void RTC_ClearITPendingBit(uint16_t RTC_IT)
{
/* Check the parameters */
assert_param(IS_RTC_IT(RTC_IT));
/* Clear the coressponding RTC pending bit */
RTC->CRL &= (uint16_t)~RTC_IT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_systick.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the SysTick firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_systick.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ---------------------- SysTick registers bit mask -------------------- */
/* CTRL TICKINT Mask */
#define CTRL_TICKINT_Set ((u32)0x00000002)
#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : SysTick_CLKSourceConfig
* Description : Configures the SysTick clock source.
* Input : - SysTick_CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8
* selected as SysTick clock source.
* - SysTick_CLKSource_HCLK: AHB clock selected as
* SysTick clock source.
* Output : None
* Return : None
*******************************************************************************/
void SysTick_CLKSourceConfig(u32 SysTick_CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}
/*******************************************************************************
* Function Name : SysTick_SetReload
* Description : Sets SysTick Reload value.
* Input : - Reload: SysTick Reload new value.
* This parameter must be a number between 1 and 0xFFFFFF.
* Output : None
* Return : None
*******************************************************************************/
void SysTick_SetReload(u32 Reload)
{
/* Check the parameters */
assert_param(IS_SYSTICK_RELOAD(Reload));
SysTick->LOAD = Reload;
}
/*******************************************************************************
* Function Name : SysTick_CounterCmd
* Description : Enables or disables the SysTick counter.
* Input : - SysTick_Counter: new state of the SysTick counter.
* This parameter can be one of the following values:
* - SysTick_Counter_Disable: Disable counter
* - SysTick_Counter_Enable: Enable counter
* - SysTick_Counter_Clear: Clear counter value to 0
* Output : None
* Return : None
*******************************************************************************/
void SysTick_CounterCmd(u32 SysTick_Counter)
{
/* Check the parameters */
assert_param(IS_SYSTICK_COUNTER(SysTick_Counter));
if (SysTick_Counter == SysTick_Counter_Enable)
{
SysTick->CTRL |= SysTick_Counter_Enable;
}
else if (SysTick_Counter == SysTick_Counter_Disable)
{
SysTick->CTRL &= SysTick_Counter_Disable;
}
else /* SysTick_Counter == SysTick_Counter_Clear */
{
SysTick->VAL = SysTick_Counter_Clear;
}
}
/*******************************************************************************
* Function Name : SysTick_ITConfig
* Description : Enables or disables the SysTick Interrupt.
* Input : - NewState: new state of the SysTick Interrupt.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SysTick_ITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SysTick->CTRL |= CTRL_TICKINT_Set;
}
else
{
SysTick->CTRL &= CTRL_TICKINT_Reset;
}
}
/*******************************************************************************
* Function Name : SysTick_GetCounter
* Description : Gets SysTick counter value.
* Input : None
* Output : None
* Return : SysTick current value
*******************************************************************************/
u32 SysTick_GetCounter(void)
{
return(SysTick->VAL);
}
/*******************************************************************************
* Function Name : SysTick_GetFlagStatus
* Description : Checks whether the specified SysTick flag is set or not.
* Input : - SysTick_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - SysTick_FLAG_COUNT
* - SysTick_FLAG_SKEW
* - SysTick_FLAG_NOREF
* Output : None
* Return : None
*******************************************************************************/
FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG)
{
u32 statusreg = 0, tmp = 0 ;
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_SYSTICK_FLAG(SysTick_FLAG));
/* Get the SysTick register index */
tmp = SysTick_FLAG >> 3;
if (tmp == 2) /* The flag to check is in CTRL register */
{
statusreg = SysTick->CTRL;
}
else /* The flag to check is in CALIB register */
{
statusreg = SysTick->CALIB;
}
if ((statusreg & ((u32)1 << SysTick_FLAG)) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_wwdg.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the WWDG firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_wwdg.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ----------- WWDG registers bit address in the alias region ----------- */
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
/* Alias word address of EWI bit */
#define CFR_OFFSET (WWDG_OFFSET + 0x04)
#define EWI_BitNumber 0x09
#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
/* --------------------- WWDG registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_WDGA_Set ((u32)0x00000080)
/* CFR register bit mask */
#define CFR_WDGTB_Mask ((u32)0xFFFFFE7F)
#define CFR_W_Mask ((u32)0xFFFFFF80)
#define BIT_Mask ((u8)0x7F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : WWDG_DeInit
* Description : Deinitializes the WWDG peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
}
/*******************************************************************************
* Function Name : WWDG_SetPrescaler
* Description : Sets the WWDG Prescaler.
* Input : - WWDG_Prescaler: specifies the WWDG Prescaler.
* This parameter can be one of the following values:
* - WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
* - WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
* - WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
* - WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
* Output : None
* Return : None
*******************************************************************************/
void WWDG_SetPrescaler(u32 WWDG_Prescaler)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
/* Clear WDGTB[1:0] bits */
tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
tmpreg |= WWDG_Prescaler;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/*******************************************************************************
* Function Name : WWDG_SetWindowValue
* Description : Sets the WWDG window value.
* Input : - WindowValue: specifies the window value to be compared to
* the downcounter.
* This parameter value must be lower than 0x80.
* Output : None
* Return : None
*******************************************************************************/
void WWDG_SetWindowValue(u8 WindowValue)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
/* Clear W[6:0] bits */
tmpreg = WWDG->CFR & CFR_W_Mask;
/* Set W[6:0] bits according to WindowValue value */
tmpreg |= WindowValue & BIT_Mask;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/*******************************************************************************
* Function Name : WWDG_EnableIT
* Description : Enables the WWDG Early Wakeup interrupt(EWI).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_EnableIT(void)
{
*(vu32 *) CFR_EWI_BB = (u32)ENABLE;
}
/*******************************************************************************
* Function Name : WWDG_SetCounter
* Description : Sets the WWDG counter value.
* Input : - Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* Output : None
* Return : None
*******************************************************************************/
void WWDG_SetCounter(u8 Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
/* Write to T[6:0] bits to configure the counter value, no need to do
a read-modify-write; writing a 0 to WDGA bit does nothing */
WWDG->CR = Counter & BIT_Mask;
}
/*******************************************************************************
* Function Name : WWDG_Enable
* Description : Enables WWDG and load the counter value.
* - Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_Enable(u8 Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
WWDG->CR = CR_WDGA_Set | Counter;
}
/*******************************************************************************
* Function Name : WWDG_GetFlagStatus
* Description : Checks whether the Early Wakeup interrupt flag is set or not.
* Input : None
* Output : None
* Return : The new state of the Early Wakeup interrupt flag (SET or RESET)
*******************************************************************************/
FlagStatus WWDG_GetFlagStatus(void)
{
return (FlagStatus)(WWDG->SR);
}
/*******************************************************************************
* Function Name : WWDG_ClearFlag
* Description : Clears Early Wakeup interrupt flag.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_ClearFlag(void)
{
WWDG->SR = (u32)RESET;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32f10x_wwdg.c
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file provides all the WWDG firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_wwdg.h"
#include "stm32f10x_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup WWDG
* @brief WWDG driver modules
* @{
*/
/** @defgroup WWDG_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Private_Defines
* @{
*/
/* ----------- WWDG registers bit address in the alias region ----------- */
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
/* Alias word address of EWI bit */
#define CFR_OFFSET (WWDG_OFFSET + 0x04)
#define EWI_BitNumber 0x09
#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
/* --------------------- WWDG registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_WDGA_Set ((uint32_t)0x00000080)
/* CFR register bit mask */
#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
#define CFR_W_Mask ((uint32_t)0xFFFFFF80)
#define BIT_Mask ((uint8_t)0x7F)
/**
* @}
*/
/** @defgroup WWDG_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Private_Functions
* @{
*/
/**
* @brief Deinitializes the WWDG peripheral registers to their default reset values.
* @param None
* @retval None
*/
void WWDG_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
}
/**
* @brief Sets the WWDG Prescaler.
* @param WWDG_Prescaler: specifies the WWDG Prescaler.
* This parameter can be one of the following values:
* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
* @retval None
*/
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
/* Clear WDGTB[1:0] bits */
tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
tmpreg |= WWDG_Prescaler;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/**
* @brief Sets the WWDG window value.
* @param WindowValue: specifies the window value to be compared to the downcounter.
* This parameter value must be lower than 0x80.
* @retval None
*/
void WWDG_SetWindowValue(uint8_t WindowValue)
{
__IO uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
/* Clear W[6:0] bits */
tmpreg = WWDG->CFR & CFR_W_Mask;
/* Set W[6:0] bits according to WindowValue value */
tmpreg |= WindowValue & (uint32_t) BIT_Mask;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/**
* @brief Enables the WWDG Early Wakeup interrupt(EWI).
* @param None
* @retval None
*/
void WWDG_EnableIT(void)
{
*(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
}
/**
* @brief Sets the WWDG counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* @retval None
*/
void WWDG_SetCounter(uint8_t Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
/* Write to T[6:0] bits to configure the counter value, no need to do
a read-modify-write; writing a 0 to WDGA bit does nothing */
WWDG->CR = Counter & BIT_Mask;
}
/**
* @brief Enables WWDG and load the counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* @retval None
*/
void WWDG_Enable(uint8_t Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
WWDG->CR = CR_WDGA_Set | Counter;
}
/**
* @brief Checks whether the Early Wakeup interrupt flag is set or not.
* @param None
* @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
*/
FlagStatus WWDG_GetFlagStatus(void)
{
return (FlagStatus)(WWDG->SR);
}
/**
* @brief Clears Early Wakeup interrupt flag.
* @param None
* @retval None
*/
void WWDG_ClearFlag(void)
{
WWDG->SR = (uint32_t)RESET;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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src/platform/stm32/FWLib/library/src/stm32f10x_wwdg.o Normal file
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2
src/platform/stm32/conf.py
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@ -8,7 +8,7 @@ local_include += ['src/platform/%s/FWLib/library/inc' % platform]
fwlib_files = " ".join(glob.glob("src/platform/%s/FWLib/library/src/*.c" % platform))
#print "FWLib: %s " % fwlib_files
specific_files = "cortexm3_macro.s stm32f10x_vector.c systick.c platform.c stm32f10x_it.c lcd.c lua_lcd.c"
specific_files = "core_cm3.c systick.c system_stm32f10x.c startup_stm32f10x_hd.s platform.c stm32f10x_it.c lcd.c lua_lcd.c"
ldscript = "stm32.ld"

829
src/platform/stm32/core_cm3.c Executable file
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@ -0,0 +1,829 @@
/******************************************************************************
* @file: core_cm3.c
* @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version: V1.20
* @date: 22. May 2009
*----------------------------------------------------------------------------
*
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-Mx
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for armcc */
#define __INLINE __inline /*!< inline keyword for armcc */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for iarcc */
#define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for gcc */
#define __INLINE inline /*!< inline keyword for gcc */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param int16_t value to reverse
* @return int32_t reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* @param none
* @return none
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @param none
* @return uint32_t BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param uint32_t BasePriority
* @return none
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @param none
* @return uint32_t PriMask
*
* Return the state of the priority mask bit from the priority mask
* register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param uint32_t PriMask
* @return none
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @param none
* @return uint32_t FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param uint32_t faultMask value
* @return none
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @param none
* @return uint32_t Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param uint32_t Control value
* @return none
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param uint32_t value to reverse
* @return uint32_t reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive
*
* @param uint8_t* address
* @return uint8_t value of (*address)
*
* Exclusive LDR command
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive
*
* @param uint16_t* address
* @return uint16_t value of (*address)
*
* Exclusive LDR command
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive
*
* @param uint32_t* address
* @return uint32_t value of (*address)
*
* Exclusive LDR command
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive
*
* @param uint8_t *address
* @param uint8_t value to store
* @return uint32_t successful / failed
*
* Exclusive STR command
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive
*
* @param uint16_t *address
* @param uint16_t value to store
* @return uint32_t successful / failed
*
* Exclusive STR command
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive
*
* @param uint32_t *address
* @param uint32_t value to store
* @return uint32_t successful / failed
*
* Exclusive STR command
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, psp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n\t"
"BX lr \n\t" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, msp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n\t"
"BX lr \n\t" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @param none
* @return uint32_t BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param uint32_t BasePriority
* @return none
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @param none
* @return uint32_t PriMask
*
* Return the state of the priority mask bit from the priority mask
* register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param uint32_t PriMask
* @return none
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @param none
* @return uint32_t FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param uint32_t faultMask value
* @return none
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Reverse byte order in integer value
*
* @param uint32_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param int32_t value to reverse
* @return int32_t reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param uint32_t value to reverse
* @return uint32_t reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive
*
* @param uint8_t* address
* @return uint8_t value of (*address)
*
* Exclusive LDR command
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive
*
* @param uint16_t* address
* @return uint16_t value of (*address)
*
* Exclusive LDR command
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive
*
* @param uint32_t* address
* @return uint32_t value of (*address)
*
* Exclusive LDR command
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive
*
* @param uint8_t *address
* @param uint8_t value to store
* @return uint32_t successful / failed
*
* Exclusive STR command
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive
*
* @param uint16_t *address
* @param uint16_t value to store
* @return uint32_t successful / failed
*
* Exclusive STR command
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive
*
* @param uint32_t *address
* @param uint32_t value to store
* @return uint32_t successful / failed
*
* Exclusive STR command
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief Return the Control Register value
*
* @param none
* @return uint32_t Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param uint32_t Control value
* @return none
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif

1367
src/platform/stm32/core_cm3.h Executable file
View File

File diff suppressed because it is too large Load Diff

2
src/platform/stm32/fonts.h
View File

@ -18,7 +18,7 @@
#define __FONTS_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
#include "stm32f10x.h"
/* Exported types ------------------------------------------------------------*/
/* ASCII Table: each character is 16 column (16dots large)

2
src/platform/stm32/lcd.h
View File

@ -19,7 +19,7 @@
#define __LCD_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
#include "stm32f10x.h"
extern void Delay(u32 nCount);

223
src/platform/stm32/platform.c
View File

@ -19,22 +19,7 @@
#include "utils.h"
// Platform specific includes
#include "stm32f10x_lib.h"
#include "stm32f10x_map.h"
#include "stm32f10x_type.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_rcc.h"
#include "stm32f10x_nvic.h"
#include "stm32f10x_dbgmcu.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_adc.h"
#include "stm32f10x_pwr.h"
#include "stm32f10x_usart.h"
#include "stm32f10x_spi.h"
#include "stm32f10x_systick.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_conf.h"
#include "systick.h"
#include "stm32f10x.h"
// Clock data
// IMPORTANT: if you change these, make sure to modify RCC_Configuration() too!
@ -50,6 +35,7 @@ static void RCC_Configuration(void);
static void NVIC_Configuration(void);
static void timers_init();
static void pwms_init();
static void uarts_init();
static void spis_init();
static void pios_init();
@ -65,7 +51,7 @@ int platform_init()
NVIC_Configuration();
// Enable SysTick timer.
SysTick_Config();
SysTick_Config(720000);
// Setup PIO
pios_init();
@ -79,6 +65,9 @@ int platform_init()
// Setup timers
timers_init();
// Setup PWMs
pwms_init();
// Setup ADCs
adcs_init();
@ -105,52 +94,7 @@ int platform_init()
*******************************************************************************/
static void RCC_Configuration(void)
{
ErrorStatus HSEStartUpStatus;
/* RCC system reset(for debug purpose) */
RCC_DeInit();
/* Enable HSE */
RCC_HSEConfig(RCC_HSE_ON);
/* Wait till HSE is ready */
HSEStartUpStatus = RCC_WaitForHSEStartUp();
if(HSEStartUpStatus == SUCCESS)
{
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
/* Flash 2 wait state */
FLASH_SetLatency(FLASH_Latency_2);
/* HCLK = SYSCLK */
RCC_HCLKConfig(RCC_SYSCLK_Div1);
/* PCLK2 = HCLK */
RCC_PCLK2Config(RCC_HCLK_Div1);
/* PCLK1 = HCLK/2 */
RCC_PCLK1Config(RCC_HCLK_Div2);
/* PLLCLK = 8MHz * 9 = 72 MHz */
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
/* Enable PLL */
RCC_PLLCmd(ENABLE);
/* Wait till PLL is ready */
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
{
}
/* Select PLL as system clock source */
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
/* Wait till PLL is used as system clock source */
while(RCC_GetSYSCLKSource() != 0x08)
{
}
}
SystemInit();
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
}
@ -173,7 +117,6 @@ static void NVIC_Configuration(void)
{
NVIC_InitTypeDef nvic_init_structure;
NVIC_DeInit();
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x20000000 */
@ -186,11 +129,8 @@ static void NVIC_Configuration(void)
/* Configure the NVIC Preemption Priority Bits */
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
/* Configure the SysTick handler priority */
NVIC_SystemHandlerPriorityConfig(SystemHandler_SysTick, 0, 0);
#ifdef BUILD_ADC
nvic_init_structure_adc.NVIC_IRQChannel = DMA1_Channel1_IRQChannel;
nvic_init_structure_adc.NVIC_IRQChannel = DMA1_Channel1_IRQn;
nvic_init_structure_adc.NVIC_IRQChannelPreemptionPriority = 1;
nvic_init_structure_adc.NVIC_IRQChannelSubPriority = 3;
nvic_init_structure_adc.NVIC_IRQChannelCmd = DISABLE;
@ -199,7 +139,7 @@ static void NVIC_Configuration(void)
#if defined( BUF_ENABLE_UART ) && defined( CON_BUF_SIZE )
/* Enable the USART1 Interrupt */
nvic_init_structure.NVIC_IRQChannel = USART1_IRQChannel;
nvic_init_structure.NVIC_IRQChannel = USART1_IRQn;
nvic_init_structure.NVIC_IRQChannelSubPriority = 0;
nvic_init_structure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&nvic_init_structure);
@ -313,7 +253,7 @@ pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
void cans_init( void )
{
/* CAN Periph clock enable */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
}
/* BS1 BS2 SJW Pre
@ -347,7 +287,7 @@ u32 platform_can_setup( unsigned id, u32 clock )
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init( GPIOB, &GPIO_InitStructure );
GPIO_PinRemapConfig( GPIO_Remap1_CAN, ENABLE );
GPIO_PinRemapConfig( GPIO_Remap1_CAN1, ENABLE );
// Select baud rate up to requested rate, except for below min, where min is selected
if ( clock >= can_baud_rate[ CAN_BAUD_COUNT - 1 ] ) // round down to peak rate if >= peak rate
@ -362,8 +302,8 @@ u32 platform_can_setup( unsigned id, u32 clock )
}
/* Deinitialize CAN Peripheral */
CAN_DeInit();
CAN_StructInit(&CAN_InitStructure);
CAN_DeInit( CAN1 );
CAN_StructInit( &CAN_InitStructure );
/* CAN cell init */
CAN_InitStructure.CAN_TTCM=DISABLE;
@ -377,7 +317,7 @@ u32 platform_can_setup( unsigned id, u32 clock )
CAN_InitStructure.CAN_BS1=can_baud_bs1[ cbaudidx ];
CAN_InitStructure.CAN_BS2=can_baud_bs2[ cbaudidx ];
CAN_InitStructure.CAN_Prescaler=can_baud_pre[ cbaudidx ];
CAN_Init( &CAN_InitStructure );
CAN_Init( CAN1, &CAN_InitStructure );
/* CAN filter init */
CAN_FilterInitStructure.CAN_FilterNumber=0;
@ -435,7 +375,7 @@ void platform_can_send( unsigned id, u32 canid, u8 idtype, u8 len, const u8 *dat
d = ( char * )TxMessage.Data;
DUFF_DEVICE_8( len, *d++ = *s++ );
CAN_Transmit( &TxMessage );
CAN_Transmit( CAN1, &TxMessage );
}
void USB_LP_CAN_RX0_IRQHandler(void)
@ -472,14 +412,14 @@ void platform_can_recv( unsigned id, u32 *canid, u8 *idtype, u8 *len, u8 *data )
u32 i = 0;
// Check up to 256 times for message
while( ( CAN_MessagePending(CAN_FIFO0) < 1 ) && ( i++ != 0xFF ) );
while( ( CAN_MessagePending(CAN1, CAN_FIFO0) < 1 ) && ( i++ != 0xFF ) );
RxMessage.StdId=0x00;
RxMessage.IDE=CAN_ID_STD;
RxMessage.DLC=0;
RxMessage.Data[0]=0x00;
RxMessage.Data[1]=0x00;
CAN_Receive(CAN_FIFO0, &RxMessage);
CAN_Receive(CAN1, CAN_FIFO0, &RxMessage);
if( RxMessage.IDE == CAN_ID_STD )
{
@ -759,7 +699,6 @@ static void timers_init()
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseStructure.TIM_RepetitionCounter = 0x0000;
TIM_TimeBaseInit( timer[ i ], &TIM_TimeBaseStructure );
TIM_Cmd( timer[ i ], ENABLE );
}
}
@ -811,6 +750,7 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
{
case PLATFORM_TIMER_OP_START:
TIM_SetCounter( ptimer, 0 );
TIM_Cmd( ptimer, ENABLE );
for( dummy = 0; dummy < 200; dummy ++ );
break;
@ -838,6 +778,133 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
return res;
}
// ****************************************************************************
// PWMs
// Using Timer 8 (5 in eLua)
#define PWM_TIMER_ID 5
static const u16 pwm_gpio_pins[] = { GPIO_Pin_6, GPIO_Pin_7, GPIO_Pin_8, GPIO_Pin_9 };
static void pwms_init()
{
//
}
// Helper function: return the PWM clock
// NOTE: Can't find a function to query for the period set for the timer, therefore using the struct.
// This may require adjustment if driver libraries are updated.
static u32 platform_pwm_get_clock()
{
return ( platform_s_timer_op( PWM_TIMER_ID, PLATFORM_TIMER_OP_GET_CLOCK, 0 ) / ( timer[ PWM_TIMER_ID ]->ARR + 1 ) );
}
// Helper function: set the PWM clock
static u32 platform_pwm_set_clock( u32 clock )
{
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
TIM_TypeDef* ptimer = timer[ PWM_TIMER_ID ];
/* Time base configuration */
TIM_TimeBaseStructure.TIM_Period = 999; //(TIM_GET_BASE_CLK( PWM_TIMER_ID ) / clock) - 1;
TIM_TimeBaseStructure.TIM_Prescaler = 0;
TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Down;
TIM_TimeBaseStructure.TIM_RepetitionCounter = 0x0000;
TIM_TimeBaseInit( ptimer, &TIM_TimeBaseStructure );
return ( TIM_GET_BASE_CLK( PWM_TIMER_ID ) / ( TIM_TimeBaseStructure.TIM_Period + 1 ) ) ;
}
u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
{
TIM_OCInitTypeDef TIM_OCInitStructure;
TIM_TypeDef* ptimer = timer[ PWM_TIMER_ID ];
TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
u32 clock;
TIM_Cmd(ptimer, DISABLE);
clock = platform_pwm_set_clock( frequency );
TIM_Cmd( ptimer, ENABLE );
// Set up PIO for output
platform_pio_op( 2, pwm_gpio_pins[ id ], PLATFORM_IO_PIN_DIR_OUTPUT );
/* PWM Mode configuration */
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable;
TIM_OCInitStructure.TIM_Pulse = 125; //( u16 )( duty / 100 * ( timer[ PWM_TIMER_ID ]->ARR + 1 ) )
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
switch ( id )
{
case 0:
TIM_OC1Init( ptimer, &TIM_OCInitStructure );
TIM_OC1PreloadConfig( ptimer, TIM_OCPreload_Enable );
clock = 0;
break;
case 1:
TIM_OC2Init( ptimer, &TIM_OCInitStructure );
TIM_OC2PreloadConfig( ptimer, TIM_OCPreload_Enable );
clock = 1;
break;
case 2:
TIM_OC3Init( ptimer, &TIM_OCInitStructure );
TIM_OC3PreloadConfig( ptimer, TIM_OCPreload_Enable );
clock = 2;
break;
case 3:
TIM_OC4Init( ptimer, &TIM_OCInitStructure );
TIM_OC4PreloadConfig( ptimer, TIM_OCPreload_Enable ) ;
clock = 3;
break;
default:
return 4;
}
TIM_ARRPreloadConfig( ptimer, ENABLE );
TIM_SelectOCxM( ptimer, TIM_Channel_1, TIM_OCMode_PWM1 );
TIM_CtrlPWMOutputs(ptimer, ENABLE);
ptimer->EGR |= TIM_EventSource_Update;
return clock;
}
u32 platform_pwm_op( unsigned id, int op, u32 data )
{
u32 res = 0;
switch( op )
{
case PLATFORM_PWM_OP_SET_CLOCK:
res = platform_pwm_set_clock( data );
break;
case PLATFORM_PWM_OP_GET_CLOCK:
res = platform_pwm_get_clock();
break;
case PLATFORM_PWM_OP_START:
timer[ PWM_TIMER_ID ]->CCER |= ( ( u16 )1 << 4*id );
break;
case PLATFORM_PWM_OP_STOP:
timer[ PWM_TIMER_ID ]->CCER &= ~( ( u16 )1 << 4*id );
break;
}
return res;
}
// *****************************************************************************
// CPU specific functions

5
src/platform/stm32/platform_conf.h
View File

@ -6,7 +6,7 @@
#include "auxmods.h"
#include "type.h"
#include "stacks.h"
#include "stm32f10x_lib.h"
#include "stm32f10x.h"
// *****************************************************************************
// Define here what components you want for this platform
@ -55,6 +55,7 @@ LUALIB_API int ( luaopen_lcd )( lua_State* L );
_ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
_ROM( AUXLIB_ADC, luaopen_adc, adc_map )\
_ROM( AUXLIB_CAN, luaopen_can, can_map )\
_ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
_ROM( AUXLIB_LUARPC, luaopen_luarpc, rpc_map )\
LCDLINE\
_ROM( LUA_MATHLIBNAME, luaopen_math, math_map )
@ -95,7 +96,7 @@ LUALIB_API int ( luaopen_lcd )( lua_State* L );
#define NUM_SPI 2
#define NUM_UART 5
#define NUM_TIMER 6
#define NUM_PWM 0
#define NUM_PWM 4
#define NUM_ADC 16
#define NUM_CAN 1

7
src/platform/stm32/stm32.ld
View File

@ -22,6 +22,7 @@ SECTIONS
*(.gnu.linkonce.r.*)
. = ALIGN(4);
_etext = .;
_sidata = _etext;
PROVIDE(etext = .);
_fini = . ;
*(.fini)
@ -31,7 +32,7 @@ SECTIONS
.data : AT (_etext)
{
. = ALIGN(4);
_data = .;
_sdata = .;
*(.ramfunc .ramfunc.* .fastrun .fastrun.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
@ -52,7 +53,9 @@ SECTIONS
__exidx_end = .;
.bss (NOLOAD) : {
_bss = .;
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)

216
src/platform/stm32/stm32f10x_conf.h
View File

@ -1,174 +1,76 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_conf.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : Library configuration file.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file Project/Template/stm32f10x_conf.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief Library configuration file.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CONF_H
#define __STM32F10x_CONF_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_type.h"
/* Uncomment the line below to enable peripheral header file inclusion */
#include "stm32f10x_adc.h"
/* #include "stm32f10x_bkp.h" */
#include "stm32f10x_can.h"
/* #include "stm32f10x_crc.h" */
/* #include "stm32f10x_dac.h" */
/* #include "stm32f10x_dbgmcu.h" */
#include "stm32f10x_dma.h"
// #include "stm32f10x_exti.h"
#include "stm32f10x_flash.h"
#include "stm32f10x_fsmc.h"
#include "stm32f10x_gpio.h"
/* #include "stm32f10x_i2c.h" */
/* #include "stm32f10x_iwdg.h" */
/* #include "stm32f10x_pwr.h" */
#include "stm32f10x_rcc.h"
/* #include "stm32f10x_rtc.h" */
/* #include "stm32f10x_sdio.h" */
#include "stm32f10x_spi.h"
#include "stm32f10x_tim.h"
#include "stm32f10x_usart.h"
/* #include "stm32f10x_wwdg.h" */
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Uncomment the line below to compile the library in DEBUG mode, this will expanse
the "assert_param" macro in the firmware library code (see "Exported macro"
section below) */
/* #define DEBUG 1*/
/* Comment the line below to disable the specific peripheral inclusion */
/************************************* ADC ************************************/
#define _ADC
#define _ADC1
#define _ADC2
#define _ADC3
/************************************* BKP ************************************/
#define _BKP
/************************************* CAN ************************************/
#define _CAN
/************************************* CRC ************************************/
#define _CRC
/************************************* DAC ************************************/
#define _DAC
/************************************* DBGMCU *********************************/
#define _DBGMCU
/************************************* DMA ************************************/
#define _DMA
#define _DMA1_Channel1
#define _DMA1_Channel2
#define _DMA1_Channel3
#define _DMA1_Channel4
#define _DMA1_Channel5
#define _DMA1_Channel6
#define _DMA1_Channel7
#define _DMA2_Channel1
#define _DMA2_Channel2
#define _DMA2_Channel3
#define _DMA2_Channel4
#define _DMA2_Channel5
/************************************* EXTI ***********************************/
#define _EXTI
/************************************* FLASH and Option Bytes *****************/
#define _FLASH
/* Uncomment the line below to enable FLASH program/erase/protections functions,
otherwise only FLASH configuration (latency, prefetch, half cycle) functions
are enabled */
/* #define _FLASH_PROG */
/************************************* FSMC ***********************************/
#define _FSMC
/************************************* GPIO ***********************************/
#define _GPIO
#define _GPIOA
#define _GPIOB
#define _GPIOC
#define _GPIOD
#define _GPIOE
#define _GPIOF
#define _GPIOG
#define _AFIO
/************************************* I2C ************************************/
#define _I2C
#define _I2C1
#define _I2C2
/************************************* IWDG ***********************************/
#define _IWDG
/************************************* NVIC ***********************************/
#define _NVIC
/************************************* PWR ************************************/
#define _PWR
/************************************* RCC ************************************/
#define _RCC
/************************************* RTC ************************************/
#define _RTC
/************************************* SDIO ***********************************/
#define _SDIO
/************************************* SPI ************************************/
#define _SPI
#define _SPI1
#define _SPI2
#define _SPI3
/************************************* SysTick ********************************/
#define _SysTick
/************************************* TIM ************************************/
#define _TIM
#define _TIM1
#define _TIM2
#define _TIM3
#define _TIM4
#define _TIM5
#define _TIM6
#define _TIM7
#define _TIM8
/************************************* USART **********************************/
#define _USART
#define _USART1
#define _USART2
#define _USART3
#define _UART4
#define _UART5
/************************************* WWDG ***********************************/
#define _WWDG
/* In the following line adjust the value of External High Speed oscillator (HSE)
used in your application */
#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/
/* In the following line adjust the External High Speed oscillator (HSE) Startup
Timeout value */
#define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */
/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
/* #define USE_FULL_ASSERT 1 */
/* Exported macro ------------------------------------------------------------*/
#ifdef DEBUG
/*******************************************************************************
* Macro Name : assert_param
* Description : The assert_param macro is used for function's parameters check.
* It is used only if the library is compiled in DEBUG mode.
* Input : - expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* Return : None
*******************************************************************************/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__))
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(u8* file, u32 line);
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* DEBUG */
#endif /* USE_FULL_ASSERT */
#endif /* __STM32F10x_CONF_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

915
src/platform/stm32/stm32f10x_it.c
View File

@ -1,24 +1,31 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_it.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : Main Interrupt Service Routines.
* This file provides template for all exceptions handler
* and peripherals interrupt service routine.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file Project/Template/stm32f10x_it.c
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief Main Interrupt Service Routines.
* This file provides template for all exceptions handler and
* peripherals interrupt service routine.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_it.h"
#include "platform.h"
#include "systick.h"
/** @addtogroup Template_Project
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@ -27,801 +34,145 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : NMIException
* Description : This function handles NMI exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NMIException(void)
/******************************************************************************/
/* Cortex-M3 Processor Exceptions Handlers */
/******************************************************************************/
/**
* @brief This function handles NMI exception.
* @param None
* @retval None
*/
void NMI_Handler(void)
{
}
/*******************************************************************************
* Function Name : HardFaultException
* Description : This function handles Hard Fault exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void HardFaultException(void)
/**
* @brief This function handles Hard Fault exception.
* @param None
* @retval None
*/
void HardFault_Handler(void)
{
/* Go to infinite loop when Hard Fault exception occurs */
while (1)
{
platform_uart_send(0, ' ');
platform_uart_send(0, 'H');
platform_uart_send(0, 'F');
platform_uart_send(0, '!');
}
/* Go to infinite loop when Hard Fault exception occurs */
while (1)
{
platform_uart_send(0, ' ');
platform_uart_send(0, 'H');
platform_uart_send(0, 'F');
platform_uart_send(0, '!');
}
}
/*******************************************************************************
* Function Name : MemManageException
* Description : This function handles Memory Manage exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void MemManageException(void)
/**
* @brief This function handles Memory Manage exception.
* @param None
* @retval None
*/
void MemManage_Handler(void)
{
/* Go to infinite loop when Memory Manage exception occurs */
while (1)
{
platform_uart_send(0, ' ');
platform_uart_send(0, 'M');
platform_uart_send(0, 'M');
platform_uart_send(0, '!');
}
/* Go to infinite loop when Memory Manage exception occurs */
while (1)
{
platform_uart_send(0, ' ');
platform_uart_send(0, 'M');
platform_uart_send(0, 'M');
platform_uart_send(0, '!');
}
}
/*******************************************************************************
* Function Name : BusFaultException
* Description : This function handles Bus Fault exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void BusFaultException(void)
/**
* @brief This function handles Bus Fault exception.
* @param None
* @retval None
*/
void BusFault_Handler(void)
{
/* Go to infinite loop when Bus Fault exception occurs */
while (1)
{
platform_uart_send(0, ' ');
platform_uart_send(0, 'B');
platform_uart_send(0, 'F');
platform_uart_send(0, '!');
}
/* Go to infinite loop when Bus Fault exception occurs */
while (1)
{
platform_uart_send(0, ' ');
platform_uart_send(0, 'B');
platform_uart_send(0, 'F');
platform_uart_send(0, '!');
}
}
/*******************************************************************************
* Function Name : UsageFaultException
* Description : This function handles Usage Fault exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void UsageFaultException(void)
/**
* @brief This function handles Usage Fault exception.
* @param None
* @retval None
*/
void UsageFault_Handler(void)
{
/* Go to infinite loop when Usage Fault exception occurs */
while (1)
{
platform_uart_send(0, ' ');
platform_uart_send(0, 'U');
platform_uart_send(0, 'F');
platform_uart_send(0, '!');
}
/* Go to infinite loop when Usage Fault exception occurs */
while (1)
{
platform_uart_send(0, ' ');
platform_uart_send(0, 'U');
platform_uart_send(0, 'F');
platform_uart_send(0, '!');
}
}
/*******************************************************************************
* Function Name : DebugMonitor
* Description : This function handles Debug Monitor exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DebugMonitor(void)
/**
* @brief This function handles SVCall exception.
* @param None
* @retval None
*/
void SVC_Handler(void)
{
}
/*******************************************************************************
* Function Name : SVCHandler
* Description : This function handles SVCall exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SVCHandler(void)
/**
* @brief This function handles Debug Monitor exception.
* @param None
* @retval None
*/
void DebugMon_Handler(void)
{
}
/*******************************************************************************
* Function Name : PendSVC
* Description : This function handles PendSVC exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void PendSVC(void)
/**
* @brief This function handles PendSVC exception.
* @param None
* @retval None
*/
void PendSV_Handler(void)
{
}
/*******************************************************************************
* Function Name : SysTickHandler
* Description : This function handles SysTick Handler.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SysTickHandler(void)
/**
* @brief This function handles SysTick Handler.
* @param None
* @retval None
*/
void SysTick_Handler(void)
{
/* Decrement the TimingDelay variable */
Decrement_TimingDelay();
/* Decrement the TimingDelay variable */
Decrement_TimingDelay();
}
/*******************************************************************************
* Function Name : WWDG_IRQHandler
* Description : This function handles WWDG interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_IRQHandler(void)
{
}
/******************************************************************************/
/* STM32F10x Peripherals Interrupt Handlers */
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
/* available peripheral interrupt handler's name please refer to the startup */
/* file (startup_stm32f10x_xx.s). */
/******************************************************************************/
/*******************************************************************************
* Function Name : PVD_IRQHandler
* Description : This function handles PVD interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void PVD_IRQHandler(void)
/**
* @brief This function handles PPP interrupt request.
* @param None
* @retval None
*/
/*void PPP_IRQHandler(void)
{
}
}*/
/*******************************************************************************
* Function Name : TAMPER_IRQHandler
* Description : This function handles Tamper interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TAMPER_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : RTC_IRQHandler
* Description : This function handles RTC global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTC_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : FLASH_IRQHandler
* Description : This function handles Flash interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void FLASH_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : RCC_IRQHandler
* Description : This function handles RCC interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RCC_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI0_IRQHandler
* Description : This function handles External interrupt Line 0 request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI0_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI1_IRQHandler
* Description : This function handles External interrupt Line 1 request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI2_IRQHandler
* Description : This function handles External interrupt Line 2 request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI3_IRQHandler
* Description : This function handles External interrupt Line 3 request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI4_IRQHandler
* Description : This function handles External interrupt Line 4 request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI4_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA1_Channel1_IRQHandler
* Description : This function handles DMA1 Channel 1 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
/**
* @}
*/
extern void DMA1_Channel1_IRQHandler(void);
/*******************************************************************************
* Function Name : DMA1_Channel2_IRQHandler
* Description : This function handles DMA1 Channel 2 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA1_Channel3_IRQHandler
* Description : This function handles DMA1 Channel 3 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA1_Channel4_IRQHandler
* Description : This function handles DMA1 Channel 4 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel4_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA1_Channel5_IRQHandler
* Description : This function handles DMA1 Channel 5 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel5_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA1_Channel6_IRQHandler
* Description : This function handles DMA1 Channel 6 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel6_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA1_Channel7_IRQHandler
* Description : This function handles DMA1 Channel 7 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel7_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : ADC1_2_IRQHandler
* Description : This function handles ADC1 and ADC2 global interrupts requests.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ADC1_2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : USB_HP_CAN_TX_IRQHandler
* Description : This function handles USB High Priority or CAN TX interrupts
* requests.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USB_HP_CAN_TX_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : USB_LP_CAN_RX0_IRQHandler
* Description : This function handles USB Low Priority or CAN RX0 interrupts
* requests.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USB_LP_CAN_RX0_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : CAN_RX1_IRQHandler
* Description : This function handles CAN RX1 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void CAN_RX1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : CAN_SCE_IRQHandler
* Description : This function handles CAN SCE interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void CAN_SCE_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI9_5_IRQHandler
* Description : This function handles External lines 9 to 5 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI9_5_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM1_BRK_IRQHandler
* Description : This function handles TIM1 Break interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM1_BRK_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM1_UP_IRQHandler
* Description : This function handles TIM1 overflow and update interrupt
* request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM1_UP_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM1_TRG_COM_IRQHandler
* Description : This function handles TIM1 Trigger and commutation interrupts
* requests.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM1_TRG_COM_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM1_CC_IRQHandler
* Description : This function handles TIM1 capture compare interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM1_CC_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM2_IRQHandler
* Description : This function handles TIM2 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM3_IRQHandler
* Description : This function handles TIM3 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM4_IRQHandler
* Description : This function handles TIM4 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM4_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : I2C1_EV_IRQHandler
* Description : This function handles I2C1 Event interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void I2C1_EV_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : I2C1_ER_IRQHandler
* Description : This function handles I2C1 Error interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void I2C1_ER_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : I2C2_EV_IRQHandler
* Description : This function handles I2C2 Event interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void I2C2_EV_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : I2C2_ER_IRQHandler
* Description : This function handles I2C2 Error interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void I2C2_ER_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : SPI1_IRQHandler
* Description : This function handles SPI1 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SPI1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : SPI2_IRQHandler
* Description : This function handles SPI2 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SPI2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : USART1_IRQHandler
* Description : This function handles USART1 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
extern void USART1_IRQHandler(void);
/*******************************************************************************
* Function Name : USART2_IRQHandler
* Description : This function handles USART2 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USART2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : USART3_IRQHandler
* Description : This function handles USART3 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USART3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI15_10_IRQHandler
* Description : This function handles External lines 15 to 10 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI15_10_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : RTCAlarm_IRQHandler
* Description : This function handles RTC Alarm interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTCAlarm_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : USBWakeUp_IRQHandler
* Description : This function handles USB WakeUp interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USBWakeUp_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM8_BRK_IRQHandler
* Description : This function handles TIM8 Break interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM8_BRK_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM8_UP_IRQHandler
* Description : This function handles TIM8 overflow and update interrupt
* request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM8_UP_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM8_TRG_COM_IRQHandler
* Description : This function handles TIM8 Trigger and commutation interrupts
* requests.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM8_TRG_COM_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM8_CC_IRQHandler
* Description : This function handles TIM8 capture compare interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM8_CC_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : ADC3_IRQHandler
* Description : This function handles ADC3 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ADC3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : FSMC_IRQHandler
* Description : This function handles FSMC global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void FSMC_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : SDIO_IRQHandler
* Description : This function handles SDIO global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SDIO_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM5_IRQHandler
* Description : This function handles TIM5 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM5_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : SPI3_IRQHandler
* Description : This function handles SPI3 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SPI3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : UART4_IRQHandler
* Description : This function handles UART4 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void UART4_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : UART5_IRQHandler
* Description : This function handles UART5 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void UART5_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM6_IRQHandler
* Description : This function handles TIM6 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM6_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM7_IRQHandler
* Description : This function handles TIM7 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM7_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA2_Channel1_IRQHandler
* Description : This function handles DMA2 Channel 1 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA2_Channel1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA2_Channel2_IRQHandler
* Description : This function handles DMA2 Channel 2 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA2_Channel2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA2_Channel3_IRQHandler
* Description : This function handles DMA2 Channel 3 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA2_Channel3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA2_Channel4_5_IRQHandler
* Description : This function handles DMA2 Channel 4 and DMA2 Channel 5
* interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA2_Channel4_5_IRQHandler(void)
{
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

117
src/platform/stm32/stm32f10x_it.h
View File

@ -1,100 +1,47 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_it.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains the headers of the interrupt handlers.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/**
******************************************************************************
* @file ADC/3ADCs_DMA/stm32f10x_it.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_IT_H
#define __STM32F10x_IT_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
#include "stm32f10x.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NMIException(void);
void HardFaultException(void);
void MemManageException(void);
void BusFaultException(void);
void UsageFaultException(void);
void DebugMonitor(void);
void SVCHandler(void);
void PendSVC(void);
void SysTickHandler(void);
void WWDG_IRQHandler(void);
void PVD_IRQHandler(void);
void TAMPER_IRQHandler(void);
void RTC_IRQHandler(void);
void FLASH_IRQHandler(void);
void RCC_IRQHandler(void);
void EXTI0_IRQHandler(void);
void EXTI1_IRQHandler(void);
void EXTI2_IRQHandler(void);
void EXTI3_IRQHandler(void);
void EXTI4_IRQHandler(void);
void DMA1_Channel1_IRQHandler(void);
void DMA1_Channel2_IRQHandler(void);
void DMA1_Channel3_IRQHandler(void);
void DMA1_Channel4_IRQHandler(void);
void DMA1_Channel5_IRQHandler(void);
void DMA1_Channel6_IRQHandler(void);
void DMA1_Channel7_IRQHandler(void);
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void ADC1_2_IRQHandler(void);
void USB_HP_CAN_TX_IRQHandler(void);
void USB_LP_CAN_RX0_IRQHandler(void);
void CAN_RX1_IRQHandler(void);
void CAN_SCE_IRQHandler(void);
void EXTI9_5_IRQHandler(void);
void TIM1_BRK_IRQHandler(void);
void TIM1_UP_IRQHandler(void);
void TIM1_TRG_COM_IRQHandler(void);
void TIM1_CC_IRQHandler(void);
void TIM2_IRQHandler(void);
void TIM3_IRQHandler(void);
void TIM4_IRQHandler(void);
void I2C1_EV_IRQHandler(void);
void I2C1_ER_IRQHandler(void);
void I2C2_EV_IRQHandler(void);
void I2C2_ER_IRQHandler(void);
void SPI1_IRQHandler(void);
void SPI2_IRQHandler(void);
void USART1_IRQHandler(void);
void USART2_IRQHandler(void);
void USART3_IRQHandler(void);
void EXTI15_10_IRQHandler(void);
void RTCAlarm_IRQHandler(void);
void USBWakeUp_IRQHandler(void);
void TIM8_BRK_IRQHandler(void);
void TIM8_UP_IRQHandler(void);
void TIM8_TRG_COM_IRQHandler(void);
void TIM8_CC_IRQHandler(void);
void ADC3_IRQHandler(void);
void FSMC_IRQHandler(void);
void SDIO_IRQHandler(void);
void TIM5_IRQHandler(void);
void SPI3_IRQHandler(void);
void UART4_IRQHandler(void);
void UART5_IRQHandler(void);
void TIM6_IRQHandler(void);
void TIM7_IRQHandler(void);
void DMA2_Channel1_IRQHandler(void);
void DMA2_Channel2_IRQHandler(void);
void DMA2_Channel3_IRQHandler(void);
void DMA2_Channel4_5_IRQHandler(void);
void DMA1_Channel1_IRQHandler(void);
void USART1_IRQHandler(void);
#endif /* __STM32F10x_IT_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

214
src/platform/stm32/stm32f10x_vector.c
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@ -1,214 +0,0 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_vector.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : STM32F10x vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure external SRAM mounted on STM3210E-EVAL board
* to be used as data memory (optional, to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
#include "stm32f10x_it.h"
/* Private typedef -----------------------------------------------------------*/
typedef void( *intfunc )( void );
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
/* Private define ------------------------------------------------------------*/
/* Uncomment the following line if you need to use external SRAM mounted on
STM3210E-EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/* Private macro -------------------------------------------------------------*/
extern unsigned long _etext;
/* start address for the initialization values of the .data section.
defined in linker script */
/* start address for the .data section. defined in linker script */
extern unsigned long _data;
/* end address for the .data section. defined in linker script */
extern unsigned long _edata;
/* start address for the .bss section. defined in linker script */
extern unsigned long _bss;
/* end address for the .bss section. defined in linker script */
extern unsigned long _ebss;
/* init value for the stack pointer. defined in linker script */
extern void _estack;
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
void Reset_Handler(void) __attribute__((__interrupt__));
extern int main(void);
/* Private functions ---------------------------------------------------------*/
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) =
{
&_estack, /* The initial stack pointer*/
Reset_Handler, /* The reset handler*/
NMIException,
HardFaultException,
MemManageException,
BusFaultException,
UsageFaultException,
0, 0, 0, 0, /* Reserved */
SVCHandler,
DebugMonitor,
0, /* Reserved */
PendSVC,
SysTickHandler,
WWDG_IRQHandler,
PVD_IRQHandler,
TAMPER_IRQHandler,
RTC_IRQHandler,
FLASH_IRQHandler,
RCC_IRQHandler,
EXTI0_IRQHandler,
EXTI1_IRQHandler,
EXTI2_IRQHandler,
EXTI3_IRQHandler,
EXTI4_IRQHandler,
DMA1_Channel1_IRQHandler,
DMA1_Channel2_IRQHandler,
DMA1_Channel3_IRQHandler,
DMA1_Channel4_IRQHandler,
DMA1_Channel5_IRQHandler,
DMA1_Channel6_IRQHandler,
DMA1_Channel7_IRQHandler,
ADC1_2_IRQHandler,
USB_HP_CAN_TX_IRQHandler,
USB_LP_CAN_RX0_IRQHandler,
CAN_RX1_IRQHandler,
CAN_SCE_IRQHandler,
EXTI9_5_IRQHandler,
TIM1_BRK_IRQHandler,
TIM1_UP_IRQHandler,
TIM1_TRG_COM_IRQHandler,
TIM1_CC_IRQHandler,
TIM2_IRQHandler,
TIM3_IRQHandler,
TIM4_IRQHandler,
I2C1_EV_IRQHandler,
I2C1_ER_IRQHandler,
I2C2_EV_IRQHandler,
I2C2_ER_IRQHandler,
SPI1_IRQHandler,
SPI2_IRQHandler,
USART1_IRQHandler,
USART2_IRQHandler,
USART3_IRQHandler,
EXTI15_10_IRQHandler,
RTCAlarm_IRQHandler,
USBWakeUp_IRQHandler,
TIM8_BRK_IRQHandler,
TIM8_UP_IRQHandler,
TIM8_TRG_COM_IRQHandler,
TIM8_CC_IRQHandler,
ADC3_IRQHandler,
FSMC_IRQHandler,
SDIO_IRQHandler,
TIM5_IRQHandler,
SPI3_IRQHandler,
UART4_IRQHandler,
UART5_IRQHandler,
TIM6_IRQHandler,
TIM7_IRQHandler,
DMA2_Channel1_IRQHandler,
DMA2_Channel2_IRQHandler,
DMA2_Channel3_IRQHandler,
DMA2_Channel4_5_IRQHandler,
};
/*******************************************************************************
* Function Name : Reset_Handler
* Description : This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* Input :
* Output :
* Return :
*******************************************************************************/
void Reset_Handler(void)
{
unsigned long *pulSrc, *pulDest;
#ifdef DATA_IN_ExtSRAM
/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
required, then adjust the Register Addresses*/
/* Enable FSMC clock */
*(vu32 *)0x40021014 = 0x00000114;
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
*(vu32 *)0x40021018 = 0x000001E0;
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
/*---------------- SRAM Address lines configuration -------------------------*/
/*---------------- NOE and NWE configuration --------------------------------*/
/*---------------- NE3 configuration ----------------------------------------*/
/*---------------- NBL0, NBL1 configuration ---------------------------------*/
*(vu32 *)0x40011400 = 0x44BB44BB;
*(vu32 *)0x40011404 = 0xBBBBBBBB;
*(vu32 *)0x40011800 = 0xB44444BB;
*(vu32 *)0x40011804 = 0xBBBBBBBB;
*(vu32 *)0x40011C00 = 0x44BBBBBB;
*(vu32 *)0x40011C04 = 0xBBBB4444;
*(vu32 *)0x40012000 = 0x44BBBBBB;
*(vu32 *)0x40012004 = 0x44444B44;
/*---------------- FSMC Configuration ---------------------------------------*/
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
*(vu32 *)0xA0000010 = 0x00001011;
*(vu32 *)0xA0000014 = 0x00000200;
#endif /*DATA_IN_ExtSRAM*/
/* Copy the data segment initializers from flash to SRAM */
pulSrc = &_etext;
for(pulDest = &_data; pulDest < &_edata; )
{
*(pulDest++) = *(pulSrc++);
}
/* Zero fill the bss segment. */
for(pulDest = &_bss; pulDest < &_ebss; )
{
*(pulDest++) = 0;
}
/* Call the application's entry point.*/
main();
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

930
src/platform/stm32/system_stm32f10x.c Executable file
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@ -0,0 +1,930 @@
/**
******************************************************************************
* @file system_stm32f10x.c
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
******************************************************************************
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f10x_system
* @{
*/
/** @addtogroup STM32F10x_System_Private_Includes
* @{
*/
#include "stm32f10x.h"
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_Defines
* @{
*/
/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
frequency (after reset the HSI is used as SYSCLK source)
IMPORTANT NOTE:
==============
1. After each device reset the HSI is used as System clock source.
2. Please make sure that the selected System clock doesn't exceed your device's
maximum frequency.
3. If none of the define below is enabled, the HSI is used as System clock
source.
4. The System clock configuration functions provided within this file assume that:
- For Low, Medium and High density devices an external 8MHz crystal is
used to drive the System clock.
- For Connectivity line devices an external 25MHz crystal is used to drive
the System clock.
If you are using different crystal you have to adapt those functions accordingly.
*/
/* #define SYSCLK_FREQ_HSE HSE_Value */
/* #define SYSCLK_FREQ_24MHz 24000000 */
/* #define SYSCLK_FREQ_36MHz 36000000 */
/* #define SYSCLK_FREQ_48MHz 48000000 */
/* #define SYSCLK_FREQ_56MHz 56000000 */
#define SYSCLK_FREQ_72MHz 72000000
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM3210E-EVAL board (STM32 High density devices) as data memory */
#ifdef STM32F10X_HD
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F10X_HD */
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_Variables
* @{
*/
/*******************************************************************************
* Clock Definitions
*******************************************************************************/
#ifdef SYSCLK_FREQ_HSE
const uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */
const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */
const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */
const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */
#elif defined SYSCLK_FREQ_24MHz
const uint32_t SystemFrequency = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_24MHz; /*!< System clock */
const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_24MHz; /*!< AHB System bus speed */
const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 1 (low) speed */
const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 2 (high) speed */
#elif defined SYSCLK_FREQ_36MHz
const uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */
const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */
const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */
const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */
#elif defined SYSCLK_FREQ_48MHz
const uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */
const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */
const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */
const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */
#elif defined SYSCLK_FREQ_56MHz
const uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */
const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */
const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */
const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */
#elif defined SYSCLK_FREQ_72MHz
const uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */
const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */
const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */
const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */
#else /*!< HSI Selected as System Clock source */
const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */
const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */
const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */
const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */
const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */
#endif
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
#ifdef SYSCLK_FREQ_HSE
static void SetSysClockToHSE(void);
#elif defined SYSCLK_FREQ_24MHz
static void SetSysClockTo24(void);
#elif defined SYSCLK_FREQ_36MHz
static void SetSysClockTo36(void);
#elif defined SYSCLK_FREQ_48MHz
static void SetSysClockTo48(void);
#elif defined SYSCLK_FREQ_56MHz
static void SetSysClockTo56(void);
#elif defined SYSCLK_FREQ_72MHz
static void SetSysClockTo72(void);
#endif
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#ifndef STM32F10X_CL
RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* STM32F10X_CL */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
#ifndef STM32F10X_CL
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#else
/* Reset PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEBFFFFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#endif /* STM32F10X_CL */
/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
SetSysClock();
}
/**
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
* @param None
* @retval None
*/
static void SetSysClock(void)
{
#ifdef SYSCLK_FREQ_HSE
SetSysClockToHSE();
#elif defined SYSCLK_FREQ_24MHz
SetSysClockTo24();
#elif defined SYSCLK_FREQ_36MHz
SetSysClockTo36();
#elif defined SYSCLK_FREQ_48MHz
SetSysClockTo48();
#elif defined SYSCLK_FREQ_56MHz
SetSysClockTo56();
#elif defined SYSCLK_FREQ_72MHz
SetSysClockTo72();
#endif
/* If none of the define above is enabled, the HSI is used as System clock
source (default after reset) */
}
/**
* @brief Setup the external memory controller. Called in startup_stm32f10x.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f10x_xx.s/.c before jump to main.
* This function configures the external SRAM mounted on STM3210E-EVAL
* board (STM32 High density devices). This SRAM will be used as program
* data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
required, then adjust the Register Addresses */
/* Enable FSMC clock */
RCC->AHBENR = 0x00000114;
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
RCC->APB2ENR = 0x000001E0;
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
/*---------------- SRAM Address lines configuration -------------------------*/
/*---------------- NOE and NWE configuration --------------------------------*/
/*---------------- NE3 configuration ----------------------------------------*/
/*---------------- NBL0, NBL1 configuration ---------------------------------*/
GPIOD->CRL = 0x44BB44BB;
GPIOD->CRH = 0xBBBBBBBB;
GPIOE->CRL = 0xB44444BB;
GPIOE->CRH = 0xBBBBBBBB;
GPIOF->CRL = 0x44BBBBBB;
GPIOF->CRH = 0xBBBB4444;
GPIOG->CRL = 0x44BBBBBB;
GPIOG->CRH = 0x44444B44;
/*---------------- FSMC Configuration ---------------------------------------*/
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
FSMC_Bank1->BTCR[4] = 0x00001011;
FSMC_Bank1->BTCR[5] = 0x00000200;
}
#endif /* DATA_IN_ExtSRAM */
#ifdef SYSCLK_FREQ_HSE
/**
* @brief Selects HSE as System clock source and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockToHSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 0 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
#ifndef STM32F10X_CL
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#else
if (HSE_Value <= 24000000)
{
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
}
else
{
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
}
#endif /* STM32F10X_CL */
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
/* Select HSE as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
/* Wait till HSE is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
/* Go to infinite loop */
while (1)
{
}
}
}
#elif defined SYSCLK_FREQ_24MHz
/**
* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockTo24(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 0 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL6);
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
#else
/* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
/* Go to infinite loop */
while (1)
{
}
}
}
#elif defined SYSCLK_FREQ_36MHz
/**
* @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockTo36(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL9);
/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
#else
/* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
/* Go to infinite loop */
while (1)
{
}
}
}
#elif defined SYSCLK_FREQ_48MHz
/**
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockTo48(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
/* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL6);
#else
/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
/* Go to infinite loop */
while (1)
{
}
}
}
#elif defined SYSCLK_FREQ_56MHz
/**
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockTo56(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
/* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL7);
#else
/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
/* Go to infinite loop */
while (1)
{
}
}
}
#elif defined SYSCLK_FREQ_72MHz
/**
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockTo72(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL9);
#else
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
/* Go to infinite loop */
while (1)
{
}
}
}
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

100
src/platform/stm32/system_stm32f10x.h Executable file
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@ -0,0 +1,100 @@
/**
******************************************************************************
* @file system_stm32f10x.h
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f10x_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F10X_H
#define __SYSTEM_STM32F10X_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F10x_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_types
* @{
*/
extern const uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
extern const uint32_t SystemFrequency_SysClk; /*!< System clock */
extern const uint32_t SystemFrequency_AHBClk; /*!< AHB System bus speed */
extern const uint32_t SystemFrequency_APB1Clk; /*!< APB Peripheral Bus 1 (low) speed */
extern const uint32_t SystemFrequency_APB2Clk; /*!< APB Peripheral Bus 2 (high) speed */
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F10X_H */
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

48
src/platform/stm32/systick.c
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@ -1,55 +1,9 @@
#include <stdio.h>
#include "stm32f10x_lib.h"
#include "stm32f10x_systick.h"
#include "stm32f10x.h"
static vu32 TimingDelay = 0;
/*******************************************************************************
* Function Name : SysTick_Config
* Description : Configure a SysTick Base time to 10 ms.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SysTick_Config(void)
{
/* Configure HCLK clock as SysTick clock source */
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
/* SysTick interrupt each 100 Hz with HCLK equal to 72MHz */
SysTick_SetReload(720000);
/* Enable the SysTick Interrupt */
SysTick_ITConfig(ENABLE);
}
/*******************************************************************************
* Function Name : Delay
* Description : Inserts a delay time.
* Input : nCount: specifies the delay time length (time base 10 ms).
* Output : None
* Return : None
*******************************************************************************/
void Delay(u32 nCount)
{
printf("Delay(%u)\n", (unsigned)nCount);
TimingDelay = nCount;
/* Enable the SysTick Counter */
SysTick_CounterCmd(SysTick_Counter_Enable);
while(TimingDelay != 0)
{
}
/* Disable the SysTick Counter */
SysTick_CounterCmd(SysTick_Counter_Disable);
/* Clear the SysTick Counter */
SysTick_CounterCmd(SysTick_Counter_Clear);
}
/*******************************************************************************
* Function Name : Decrement_TimingDelay
* Description : Decrements the TimingDelay variable.

3
src/platform/stm32/systick.h
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@ -1,8 +1,7 @@
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
void SysTick_Config(void);
void Delay(u32 nCount);
/* void Delay(u32 nCount);*/
void Decrement_TimingDelay(void);
#endif

2
src/platform/stm32/type.h
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@ -1,7 +1,7 @@
#ifndef __TYPE_H__
#define __TYPE_H__
#include "stm32f10x_type.h"
#include "stm32f10x.h"
#ifndef NULL
#define NULL ((void *)0)