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XMC4300 relax kit: Initial support for running eLua

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This commit is contained in:
Raman 2019-02-05 22:41:21 +05:30
parent 2ce33d3b58
commit 111abf3b9d
8 changed files with 149 additions and 19 deletions
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40
boards/known/xmc4300-relax-ethercat.lua Normal file
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@ -0,0 +1,40 @@
-- Infineon XMC4300 EtherCat kit - Version 1.1
--[[
Notes:
1) Again, No SDMMC. That makes me sad! :( We have to kludge on
existing boilerplate in gen/ to get SPI working with an external SD
card adapter.
TODO: SPI pin details?
2) The board simply looks beautiful! It certainly reminds me of the
EK-LM3S8962 days with Edelstoff! :)
--]]
return {
cpu = 'xmc4300f100k256',
components = {
sercon = { uart = 0, speed = 115200 },
wofs = false,
romfs = true,
shell = true,
term = { lines = 25, cols = 80 },
linenoise = { shell_lines = 10, lua_lines = 50 },
xmodem = false,
niffs = false,
},
config = {
egc = { mode = "alloc" },
ram = { internal_rams = 1 },
},
modules = {
generic = { 'all', '-tmr', '-i2c', '-net', '-adc', '-spi', '-uart', '-can', '-pwm', '-rpc', '-fs' },
platform = 'all',
}
}

2
build_data.lua
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@ -116,7 +116,7 @@ local platform_list =
lpc23xx = { cpus = { 'LPC2368' }, arch = 'arm' },
lpc24xx = { cpus = { 'LPC2468' }, arch = 'arm' },
lpc17xx = { cpus = { 'LPC1768', 'LPC1769' }, arch = 'cortexm' },
xmc4000 = { cpus = { 'XMC4400F100X512', 'XMC4500F144K1024', 'XMC4500E144K1024', 'XMC4700F144K2048' }, arch = 'cortexm' },
xmc4000 = { cpus = { 'XMC4400F100X512', 'XMC4500F144K1024', 'XMC4500E144K1024', 'XMC4700F144K2048', 'XMC4300F100K256' }, arch = 'cortexm' },
}
-- Returns the platform of a given CPU

9
src/platform/xmc4000/conf.lua
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@ -22,6 +22,11 @@ if cpu == 'XMC4700F144K2048' then
target_files = " startup_XMC4700.S system_XMC4700.c"
end
if cpu == 'XMC4300F100K256' then
ldscript = "xmc4300_linker_script.ld"
target_files = " startup_XMC4300.S system_XMC4300.c"
end
specific_files = specific_files .. target_files
addi( "src/platform/" .. platform .. "/xmclib/inc" )
@ -62,6 +67,10 @@ if cpu == 'XMC4700F144K2048' then
addm( { "XMC4700_F144x2048" } )
end
if cpu == 'XMC4300F100K256' then
addm( { "XMC4300_F100x256" } )
end
-- Standard GCC Flags
addcf( { '-ffunction-sections', '-fdata-sections', '-fno-strict-aliasing', '-Wall' } )
addlf( { '-nostartfiles','-nostdlib', '-T', ldscript, '-Wl,--gc-sections', '-Wl,--allow-multiple-definition', '-L\"src/platform/xmc4000/xmclib/gui\"' } )

37
src/platform/xmc4000/cpu_xmc4300f100k256.h Normal file
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@ -0,0 +1,37 @@
#ifndef __CPU_XMC4300F100K256_H__
#define __CPU_XMC4300F100K256_H__
#include "stacks.h"
#include "DAVE.h"
// Number of resources (0 if not available/not implemented)
#define NUM_PIO 16
#define NUM_SPI 0
#define NUM_UART 1
#define NUM_TIMER 1
#define NUM_PWM 0
#define NUM_ADC 0
#define NUM_CAN 0
#define NUM_DAC 2
// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used)
#define CPU_FREQUENCY 144000000
// PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
#define PIO_PREFIX '0'
// Pins per port configuration:
// #define PIO_PINS_PER_PORT (n) if each port has the same number of pins, or
// #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array
// Use #define PIO_PINS_PER_PORT 0 if this isn't needed
#define PIO_PIN_ARRAY { 13, 16, 13, 7, 2, 4, 0, 0, 0, 0, 0, 0, 0, 0, 14, 4 }
// Allocator data: define your free memory zones here in two arrays
// (start address and end address)
#define RAM_SIZE 0x10000
#define RAM_BASE 0x20000000
#define INTERNAL_RAM1_FIRST_FREE RAM_BASE
#define INTERNAL_RAM1_LAST_FREE ( RAM_BASE + RAM_SIZE - STACK_SIZE_TOTAL - 1 )
#endif // #ifndef __CPU_XMC4300F100K256_H__

18
src/platform/xmc4000/platform.c
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@ -25,6 +25,10 @@
# include "XMC4700.h"
#endif
#if defined ( XMC4300_F100x256 )
# include "XMC4300.h"
#endif
// Peripheral includes
#include "xmc_dac.h"
@ -88,6 +92,20 @@ static XMC_GPIO_PORT_t *const pio_port[] =
XMC_GPIO_PORT15
};
#elif defined ( ELUA_CPU_XMC4300F100K256 )
static XMC_GPIO_PORT_t *const pio_port[] =
{
XMC_GPIO_PORT0,
XMC_GPIO_PORT1,
XMC_GPIO_PORT2,
XMC_GPIO_PORT3,
XMC_GPIO_PORT4,
XMC_GPIO_PORT5,
XMC_GPIO_PORT14,
XMC_GPIO_PORT15
};
#endif
static void platformh_setup_pins( unsigned port, pio_type pinmask, u8 mask )

9
src/platform/xmc4000/xmc4300_linker_script.ld
View File

@ -61,7 +61,7 @@ OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(Reset_Handler)
stack_size = DEFINED(stack_size) ? stack_size : 2048;
stack_size = DEFINED(stack_size) ? stack_size : 10240;
no_init_size = 64;
MEMORY
@ -79,6 +79,7 @@ SECTIONS
.text :
{
PROVIDE(stext = .);
sText = .;
KEEP(*(.reset));
*(.text .text.* .gnu.linkonce.t.*);
@ -106,7 +107,8 @@ SECTIONS
*(vtable)
. = ALIGN(4);
. = ALIGN(4);
PROVIDE(etext = .);
} > FLASH_1_cached AT > FLASH_1_uncached
.eh_frame_hdr : ALIGN (4)
@ -180,6 +182,7 @@ SECTIONS
. = ALIGN(4);
/* finit data */
_fini = .;
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
@ -240,6 +243,8 @@ SECTIONS
* (.no_init);
} > SRAM_combined
end = .;
/* Heap - Bank1*/
Heap_Bank1_Size = Heap_Bank1_End - Heap_Bank1_Start;

3
src/platform/xmc4000/xmclib/gen/CLOCK_XMC4/clock_xmc4_conf.c
View File

@ -148,8 +148,9 @@ void SystemCoreClockSetup(void)
#ifdef CLOCK_XMC4_EBUCLK_ENABLED
/* EBU divider setting */
#if defined ( XMC4500_E144x1024 )
XMC_SCU_CLOCK_SetEbuClockDivider(1U);
#endif
#endif
}

50
src/platform/xmc4000/xmclib/gen/UART/uart_conf.c
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@ -58,6 +58,26 @@
**********************************************************************************************************************/
#include "uart.h"
/***********************************************************************************************************************
* MACROS
***********************************************************************************************************************/
#if defined ( XMC4300_F100x256 )
# define TX_PIN_PORT_BASE PORT0_BASE
# define RX_PIN_PORT_BASE PORT0_BASE
# define DMA_DEST_PERIPHERAL_RQST_CH 11U
# define DMA_SRC_PERIPHERAL_RQST_CH 12U
# define SELECTED_UART_CHANNEL XMC_UART1_CH0
# define SOURCE_INPUT_SELECT 0
#else
# define TX_PIN_PORT_BASE PORT1_BASE
# define RX_PIN_PORT_BASE PORT1_BASE
# define DMA_DEST_PERIPHERAL_RQST_CH 10U
# define DMA_SRC_PERIPHERAL_RQST_CH 11U
# define SELECTED_UART_CHANNEL XMC_UART0_CH0
# define SOURCE_INPUT_SELECT 1
#endif
/***********************************************************************************************************************
* EXTERN DECLARATIONS
***********************************************************************************************************************/
@ -99,7 +119,7 @@ const XMC_GPIO_CONFIG_t UART_0_tx_pin_config =
/*Transmit pin configuration used for initializing*/
const UART_TX_CONFIG_t UART_0_tx_pin =
{
.port = (XMC_GPIO_PORT_t *)PORT1_BASE,
.port = (XMC_GPIO_PORT_t *)TX_PIN_PORT_BASE,
.config = &UART_0_tx_pin_config,
.pin = 5U
};
@ -116,7 +136,7 @@ const XMC_DMA_CH_CONFIG_t UART_0_tx_dma_ch_config =
.transfer_flow = (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA,
.transfer_type = (uint32_t)XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
.dst_handshaking = (uint32_t)XMC_DMA_CH_DST_HANDSHAKING_HARDWARE,
.dst_peripheral_request = DMA_PERIPHERAL_REQUEST(5U, 10U), /*DMA0_PERIPHERAL_REQUEST_USIC0_SR0_5*/
.dst_peripheral_request = DMA_PERIPHERAL_REQUEST(5U, DMA_DEST_PERIPHERAL_RQST_CH), /*DMA0_PERIPHERAL_REQUEST_USIC0_SR0_5*/
};
const UART_DMA_CONFIG_t UART_0_tx_dma_config =
@ -137,7 +157,7 @@ const XMC_DMA_CH_CONFIG_t UART_0_rx_dma_ch_config =
.transfer_flow = (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA,
.transfer_type = (uint32_t)XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
.src_handshaking = (uint32_t)XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE,
.src_peripheral_request = DMA_PERIPHERAL_REQUEST(2U, 11U), /*DMA0_PERIPHERAL_REQUEST_USIC0_SR1_2*/
.src_peripheral_request = DMA_PERIPHERAL_REQUEST(2U, DMA_SRC_PERIPHERAL_RQST_CH), /*DMA0_PERIPHERAL_REQUEST_USIC0_SR1_2*/
};
const UART_DMA_CONFIG_t UART_0_rx_dma_config =
@ -178,7 +198,7 @@ UART_RUNTIME_t UART_0_runtime =
/*APP handle structure*/
UART_t UART_0 =
{
.channel = XMC_UART0_CH0,
.channel = SELECTED_UART_CHANNEL,
.config = &UART_0_config,
.runtime = &UART_0_runtime
};
@ -204,34 +224,34 @@ UART_STATUS_t UART_0_init()
XMC_DMA_CH_EnableEvent(XMC_DMA0, 4U, XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);
/*Configure Receive pin*/
XMC_GPIO_Init((XMC_GPIO_PORT_t *)PORT1_BASE, 4U, &UART_0_rx_pin_config);
XMC_GPIO_Init((XMC_GPIO_PORT_t *)RX_PIN_PORT_BASE, 4U, &UART_0_rx_pin_config);
/* Initialize USIC channel in UART mode*/
XMC_UART_CH_Init(XMC_UART0_CH0, &UART_0_channel_config);
XMC_UART_CH_Init(SELECTED_UART_CHANNEL, &UART_0_channel_config);
/*Set input source path*/
XMC_USIC_CH_SetInputSource(XMC_UART0_CH0, XMC_USIC_CH_INPUT_DX0, 1U);
XMC_USIC_CH_SetInputSource(SELECTED_UART_CHANNEL, XMC_USIC_CH_INPUT_DX0, SOURCE_INPUT_SELECT);
/* Start UART */
XMC_UART_CH_Start(XMC_UART0_CH0);
XMC_UART_CH_Start(SELECTED_UART_CHANNEL);
/* Initialize UART TX pin */
XMC_GPIO_Init((XMC_GPIO_PORT_t *)PORT1_BASE, 5U, &UART_0_tx_pin_config);
XMC_GPIO_Init((XMC_GPIO_PORT_t *)TX_PIN_PORT_BASE, 5U, &UART_0_tx_pin_config);
/*Set service request for transmit interrupt*/
XMC_USIC_CH_SetInterruptNodePointer(XMC_UART0_CH0, XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER,
XMC_USIC_CH_SetInterruptNodePointer(SELECTED_UART_CHANNEL, XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER,
0U);
/*Set service request for receive interrupt*/
XMC_USIC_CH_SetInterruptNodePointer(XMC_UART0_CH0, XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE,
XMC_USIC_CH_SetInterruptNodePointer(SELECTED_UART_CHANNEL, XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE,
1U);
XMC_USIC_CH_SetInterruptNodePointer(XMC_UART0_CH0, XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE,
XMC_USIC_CH_SetInterruptNodePointer(SELECTED_UART_CHANNEL, XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE,
1U);
/*Set service request for UART protocol events*/
XMC_USIC_CH_SetInterruptNodePointer(XMC_UART0_CH0, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL,
XMC_USIC_CH_SetInterruptNodePointer(SELECTED_UART_CHANNEL, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL,
2U);
/*Register transfer complete event handler*/
XMC_DMA_CH_SetEventHandler(XMC_DMA0, 4U, UART_0_dma_rx_handler);
/*Register transfer complete event handler*/
XMC_DMA_CH_SetEventHandler(XMC_DMA0, 5U, UART_0_dma_tx_handler);
/* make DMA ready for transmission*/
XMC_USIC_CH_TriggerServiceRequest(XMC_UART0_CH0, 0U);
XMC_USIC_CH_TriggerServiceRequest(SELECTED_UART_CHANNEL, 0U);
return status;
}
@ -257,4 +277,4 @@ void UART_0_dma_rx_handler(XMC_DMA_CH_EVENT_t event)
}
/*CODE_BLOCK_END*/