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updated str9-comstick initialization code
This commit is contained in:
Bogdan Marinescu
parent
4759965d3a
commit
2d0652c808
@ -39,11 +39,7 @@ static const GPIO_TypeDef* port_data[] = { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GP
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static const TIM_TypeDef* timer_data[] = { TIM0, TIM1, TIM2, TIM3 };
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static void platform_config_scu()
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{
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FMI_BankRemapConfig(4, 2, 0, 0x80000); /* Set Flash banks size & address */
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FMI_Config(FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE,
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FMI_LVD_ENABLE, FMI_FREQ_HIGH); /* FMI Waite States */
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{
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volatile u16 i = 0xFFFF;
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while (i-- > 0);
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@ -52,13 +48,19 @@ static void platform_config_scu()
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SCU_PLLFactorsConfig(192,25,2); /* PLL = 96 MHz */
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SCU_PLLCmd(ENABLE); /* PLL Enabled */
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SCU_MCLKSourceConfig(SCU_MCLK_PLL); /* MCLK = PLL */
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SCU_PFQBCCmd( ENABLE );
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/* Set the RCLK Clock divider to max speed*/
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SCU_RCLKDivisorConfig(SCU_RCLK_Div1);
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/* Set the PCLK Clock to MCLK/8 */
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SCU_PCLKDivisorConfig(SCU_PCLK_Div8);
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/* Set the HCLK Clock to MCLK/2 */
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SCU_HCLKDivisorConfig(SCU_HCLK_Div2);
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/* Set the HCLK Clock to MCLK */
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SCU_HCLKDivisorConfig(SCU_HCLK_Div1);
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/* Enable VIC clock */
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SCU_AHBPeriphClockConfig(__VIC, ENABLE);
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SCU_AHBPeriphReset(__VIC, DISABLE);
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// Enable the UART clocks
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SCU_APBPeriphClockConfig(__UART_ALL, ENABLE);
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@ -3,8 +3,9 @@
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#ifndef __STACKS_H__
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#define __STACKS_H__
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#define STACK_SIZE_USR 512
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#define STACK_SIZE_IRQ 64
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#define STACK_SIZE_TOTAL ( STACK_SIZE_USR + STACK_SIZE_IRQ )
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#define STACK_SIZE_USR 256
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#define STACK_SIZE_SVC 32
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#define STACK_SIZE_IRQ 32
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#define STACK_SIZE_TOTAL ( STACK_SIZE_USR + STACK_SIZE_SVC + STACK_SIZE_IRQ )
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#endif
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@ -27,10 +27,12 @@
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#*************************************************************************
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# Control Startup Code Operation
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#*************************************************************************
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.equ SRAM_SETUP , 1 /* Enable setup of SRAM */
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.equ SRAM_SETUP , 1 /* Enable setup of SRAM */
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.equ FMI_SETUP , 1 /* Enable FMI Setup */
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.equ CLOCK_SETUP , 1 /* Enable clock setup */
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#*************************************************************************
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# Hardware Definitions
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# Hardware Definitions
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#*************************************************************************
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# Flash Memory Interface (FMI) definitions (Flash banks sizes and addresses)
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@ -42,7 +44,6 @@
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.equ FMI_CR_OFS , 0x18 /* Control Register */
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.equ FMI_SR_OFS , 0x1C /* Status Register */
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.equ FMI_CR_Val , 0x00000018
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.equ FMI_BBSR_Val , 0x00000004
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.equ FMI_BBADR_Val , 0x00000000
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@ -79,7 +80,7 @@
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# Stack definitions
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#*************************************************************************
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.equ Top_Stack, RAM_Base + RAM_Size
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.equ Top_Stack, RAM_Base + RAM_Size
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# NOTE: Startup Code must be linked first at Address at which it expects to run.
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@ -98,11 +99,11 @@ _startup:
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# Exception Vectors
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#*************************************************************************
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Vectors:
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LDR PC, Reset_Addr /* 0x0000 */
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LDR PC, Undef_Addr /* 0x0004 */
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LDR PC, SWI_Addr /* 0x0008 */
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LDR PC, PAbt_Addr /* 0x000C */
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LDR PC, DAbt_Addr /* 0x0010 */
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LDR PC, Reset_Addr /* 0x0000 */
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LDR PC, Undef_Addr /* 0x0004 */
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LDR PC, SWI_Addr /* 0x0008 */
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LDR PC, PAbt_Addr /* 0x000C */
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LDR PC, DAbt_Addr /* 0x0010 */
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NOP /* 0x0014 Reserved Vector */
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LDR PC, [PC, #-0xFF0] /* 0x0018 wraps around address space to 0xFFFFFF030. Vector from VicVECAddr */
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LDR PC, FIQ_Addr /* 0x001C FIQ has no VIC vector slot! */
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@ -112,22 +113,22 @@ Vectors:
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#*************************************************************************
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Reset_Addr: .word Hard_Reset /* CPU reset vector and entry point */
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Undef_Addr: .word Undef_Handler
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Undef_Addr: .word Undefined_Handler
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SWI_Addr: .word SWI_Handler
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PAbt_Addr: .word PAbt_Handler
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DAbt_Addr: .word DAbt_Handler
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.word 0 /* Reserved Address */
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IRQ_Addr: .word IRQ_Handler /* Does not get used due to "LDR PC, [PC, #-0xFF0]" above */
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FIQ_Addr: .word FIQ_Handler
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IRQ_Addr: .word IRQ_Handler /* Does not get used due to "LDR PC, [PC, #-0xFF0]" above */
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FIQ_Addr: .word FIQ_Handler
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# Dummy Interrupt Vector Table (real service routines in INTERRUPT.C)
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Undef_Handler: B Undef_Handler
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SWI_Handler: B SWI_Handler
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PAbt_Handler: B PAbt_Handler
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DAbt_Handler: B DAbt_Handler
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IRQ_Handler: B IRQ_Handler /* should never get here as IRQ is via VIC slot... */
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FIQ_Handler: B FIQ_Handler
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Undefined_Handler: B Undefined_Handler
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SWI_Handler: B SWI_Handler
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PAbt_Handler: B PAbt_Handler
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DAbt_Handler: B DAbt_Handler
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IRQ_Handler: B IRQ_Handler /* should never get here as IRQ is via VIC slot... */
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FIQ_Handler: B FIQ_Handler
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#*************************************************************************
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@ -135,6 +136,8 @@ FIQ_Handler: B FIQ_Handler
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#*************************************************************************
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Hard_Reset:
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StartupDelay 900000
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#*************************************************************************
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# Setup SRAM Size
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@ -146,6 +149,90 @@ Hard_Reset:
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.ENDIF
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#*************************************************************************
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# Setup Flash Memory Interface (FMI)
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.IF FMI_SETUP == 1
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LDR R0, =FMI_BASE
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LDR R1, =FMI_BBSR_Val
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STR R1, [R0, #FMI_BBSR_OFS]
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LDR R1, =FMI_NBBSR_Val
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STR R1, [R0, #FMI_NBBSR_OFS]
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LDR R1, =(FMI_BBADR_Val >> 2)
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STR R1, [R0, #FMI_BBADR_OFS]
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LDR R1, =(FMI_NBBADR_Val >> 2)
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STR R1, [R0, #FMI_NBBADR_OFS]
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LDR R2, =FMI_CR_Val
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STR R2, [R0, #FMI_CR_OFS]
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LDR R2, =FMI_SR_Val
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STR R2, [R0, #FMI_SR_OFS]
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# Write "Write flash configuration" command (60h)
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MOV R0, R1, LSL #2
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MOV R1, #0x60
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STRH R1, [R0, #0]
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# Write "Write flash configuration confirm" command (03h)
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LDR R2, =(FLASH_CFG_Val >> 2)
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ADD R0, R0, R2
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MOV R1, #0x03
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STRH R1, [R0, #0]
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.ENDIF
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#*************************************************************************
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# Setup Clock PLL
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.IF CLOCK_SETUP == 1
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LDR R0, =SCU_BASE
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LDR R1, =0x00020002
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STR R1, [R0, #SCU_CLKCNTR_OFS] /* Select OSC as clock src */
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NOP /* Wait for oscillator stabilisation */
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NOP /* Must be more than 10 oscillator periods */
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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LDR R1, =0x0003C019 /* Disable PLL */
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STR R1, [R0, #SCU_PLLCONF_OFS]
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LDR R1, =SCU_PLLCONF_Val
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STR R1, [R0, #SCU_PLLCONF_OFS] /* Set new PLL values */
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.IF (SCU_PLLCONF_Val & 0x8000) /* See if PLL is being used */
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LDR R1, =SCU_SYSSTAT_LOCK
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PLL_LOCK_LOOP:
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LDR R2,[R0, #SCU_SYSTAT_OFS] /* Wait for PLL lock */
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ANDS R2, R2, R1
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BEQ PLL_LOCK_LOOP
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.ENDIF
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LDR R1, =SCU_PLLCONF_Val
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STR R1, [R0, #SCU_PLLCONF_OFS]
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LDR R1, =SCU_CLKCNTR_Val
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STR R1, [R0, #SCU_CLKCNTR_OFS]
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LDR R1, =SCU_PCGR0_Val /* Enable clock gating */
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STR R1, [R0, #SCU_PCGR0_OFS]
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LDR R1, =SCU_PCGR1_Val
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STR R1, [R0, #SCU_PCGR1_OFS]
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.ENDIF
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#*************************************************************************
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# Compiler Runtime Environment Setup
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#*************************************************************************
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@ -156,13 +243,17 @@ Hard_Reset:
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# Set up Interrupt Mode and set IRQ Mode Stack
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msr CPSR_c, #Mode_IRQ|I_BIT|F_BIT
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mov r13, r0
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sub r0, r0, #STACK_SIZE_IRQ
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mov r13, r0
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sub r0, r0, #STACK_SIZE_IRQ
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# Set up Supervisor Mode and set Supervisor Mode Stack
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msr CPSR_c, #Mode_SVC|I_BIT|F_BIT
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mov r13, r0
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sub r0, r0, #STACK_SIZE_SVC
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# Set up User Mode and set User Mode Stack
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msr CPSR_c, #Mode_USR /* Leave interrupts enabled in user mode */
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mov r13, r0 /* Note: interrupts will not happen until VIC is enabled */
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mov r13, r0 /* Note: interrupts will not happen until VIC is enabled */
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#*************************************************************************
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# Initialise RAM For Compiler Variables
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@ -188,7 +279,6 @@ Hard_Reset:
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forever:
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B forever
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#*************************************************************************
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# END
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#*************************************************************************
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