mirror of
https://github.com/elua/elua.git
synced 2025-01-25 01:02:54 +08:00
Added stm32.pio platform specific module
Also removed the platform specific initialization code, this is now automatic.
This commit is contained in:
Bogdan Marinescu
parent
88257cdc9a
commit
2dff752740
@ -24,6 +24,7 @@ return {
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modules = {
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generic = { 'all', "-i2c", "-net" },
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platform = 'all',
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platform_name = 'stm32'
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},
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}
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@ -199,7 +199,7 @@ function gen_module_list( desc, plconf, platform, boardname )
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local pltabname = mdesc.platform_name or platform
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for m, _ in pairs( gen_list_platform ) do nguards = nguards + #( platform_modules[ m ].guards or {} ) end
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if nguards == 0 then -- nothing to guard
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gstr = gstr .. gen.print_define( "PLATFORM_MODULES_LINE", sf( '_ROM( "%s", luaopen_platform, platform_map )', platform ) )
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gstr = gstr .. gen.print_define( "PLATFORM_MODULES_LINE", sf( '_ROM( "%s", luaopen_platform, platform_map )', pltabname ) )
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gstr = gstr .. gen.print_define( "PS_LIB_TABLE_NAME", sf( '"%s"', pltabname ) )
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gstr = gstr .. gen.print_define( "PLATFORM_MODULES_ENABLE" )
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else
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@ -25,5 +25,7 @@ end
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-- Return an array of all the available platform modules for the given cpu
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function get_platform_modules( board, cpu )
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return { pio = { lib = '"pio"', map = "stm32_pio_map", open = false },
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cpu = { lib = '"cpu"', map = "stm32_cpu_map", open = "luaopen_stm32_cpu" } }
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end
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@ -9,7 +9,7 @@ addi( sf( 'src/platform/%s/FWLib/USB/VCP/inc', platform ) )
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local fwlib_files = utils.get_files( "src/platform/" .. platform .. "/FWLib/library/src", ".*%.c$" )
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fwlib_files = fwlib_files .. " " .. utils.get_files( "src/platform/" .. platform .. "/FWLib/USB/", "%.c$" )
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specific_files = "system_stm32f4xx.c startup_stm32f4xx.s stm32f4xx_it.c platform.c platform_int.c cpu.c"
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specific_files = "system_stm32f4xx.c startup_stm32f4xx.s stm32f4xx_it.c platform.c platform_int.c cpu.c stm32_pio.c"
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local ldscript = "stm32.ld"
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-- Prepend with path
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@ -11,8 +11,6 @@
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#include "auxmods.h"
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#include "cpu.h"
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//Lua: reset()
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static int cpu_reset( lua_State *L )
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{
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@ -193,7 +193,7 @@ static void NVIC_Configuration(void)
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// PIO
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// This is pretty much common code to all STM32 devices.
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// todo: Needs updates to support different processor lines.
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static GPIO_TypeDef * const pio_port[] = { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI };
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GPIO_TypeDef * const pio_port[] = { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI };
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static const u32 pio_port_clk[] = { RCC_AHB1Periph_GPIOA , RCC_AHB1Periph_GPIOB
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, RCC_AHB1Periph_GPIOC , RCC_AHB1Periph_GPIOD , RCC_AHB1Periph_GPIOE
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, RCC_AHB1Periph_GPIOF , RCC_AHB1Periph_GPIOG , RCC_AHB1Periph_GPIOH
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@ -1642,46 +1642,3 @@ int platform_flash_erase_sector( u32 sector_id )
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#endif // #ifdef BUILD_WOFS
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// ****************************************************************************
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// Platform specific modules go here
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#ifdef ENABLE_STM32_CPU
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#define MIN_OPT_LEVEL 2
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#include "lrodefs.h"
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extern const LUA_REG_TYPE stm32_cpu_map[];
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const LUA_REG_TYPE platform_map[] =
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{
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#if LUA_OPTIMIZE_MEMORY > 0
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{ LSTRKEY( "cpu" ), LROVAL( stm32_cpu_map ) },
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#endif
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{ LNILKEY, LNILVAL }
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};
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LUALIB_API int luaopen_platform( lua_State *L )
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{
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#if LUA_OPTIMIZE_MEMORY > 0
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return 0;
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#else // #if LUA_OPTIMIZE_MEMORY > 0
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luaL_register( L, PS_LIB_TABLE_NAME, platform_map );
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// Setup the new tables inside platform table
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lua_newtable( L );
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luaL_register( L, NULL, stm32_cpu_map );
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lua_setfield( L, -2, "cpu" );
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return 1;
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#endif // #if LUA_OPTIMIZE_MEMORY > 0
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}
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#else // #ifdef ENABLE_ENC
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LUALIB_API int luaopen_platform( lua_State *L )
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{
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return 0;
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}
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#endif // #ifdef ENABLE_ENC
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@ -1,212 +0,0 @@
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// eLua platform configuration
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#ifndef __PLATFORM_CONF_H__
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#define __PLATFORM_CONF_H__
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#include "auxmods.h"
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#include "type.h"
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#include "stacks.h"
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#include "stm32f4xx_conf.h"
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#include "elua_int.h"
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#include "sermux.h"
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// *****************************************************************************
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// Define here what components you want for this platform
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#define BUILD_XMODEM
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#define BUILD_SHELL
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#define BUILD_ROMFS
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//#define BUILD_MMCFS
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#define BUILD_TERM
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//#define BUILD_UIP
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//#define BUILD_DHCPC
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//#define BUILD_DNS
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#define BUILD_CON_GENERIC
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#define BUILD_ADC
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#define BUILD_RPC
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//#define BUILD_RFS
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//#define BUILD_CON_TCP
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#define BUILD_LINENOISE
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#define BUILD_C_INT_HANDLERS
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#define BUILD_LUA_INT_HANDLERS
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//#define ENABLE_ENC
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#define ENABLE_STM32_CPU
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#define PLATFORM_HAS_SYSTIMER
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//#define ENABLE_TRACE // Enable the ETM TRACE interface (TRACECLK, TRACE D0-3)
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#define ENABLE_JTAG_SWD // Do NOT remove this unless you really not need JTAG/SWD
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// *****************************************************************************
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// UART/Timer IDs configuration data (used in main.c)
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#define CON_UART_ID 0
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#define CON_UART_SPEED 115200
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#define TERM_LINES 25
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#define TERM_COLS 80
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// *****************************************************************************
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// Auxiliary libraries that will be compiled for this platform
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//#ifdef FORSTM3210E_EVAL
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//#define AUXLIB_LCD "stm3210lcd"
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//LUALIB_API int ( luaopen_lcd )( lua_State* L );
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//#define LCDLINE _ROM( AUXLIB_LCD, luaopen_lcd, lcd_map )
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//#else
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#define LCDLINE
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//#endif
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#ifdef ENABLE_STM32_CPU
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#define PS_LIB_TABLE_NAME "stm32"
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#endif
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#ifdef BUILD_ADC
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#define ADCLINE _ROM( AUXLIB_ADC, luaopen_adc, adc_map )
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#else
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#define ADCLINE
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#endif
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#if defined( ELUA_BOOT_RPC ) && !defined( BUILD_RPC )
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#define BUILD_RPC
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#endif
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#if defined( BUILD_RPC )
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#define RPCLINE _ROM( AUXLIB_RPC, luaopen_rpc, rpc_map )
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#else
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#define RPCLINE
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#endif
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#ifdef PS_LIB_TABLE_NAME
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#define PLATLINE _ROM( PS_LIB_TABLE_NAME, luaopen_platform, platform_map )
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#else
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#define PLATLINE
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#endif
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#define LUA_PLATFORM_LIBS_ROM\
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_ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
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_ROM( AUXLIB_SPI, luaopen_spi, spi_map )\
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_ROM( AUXLIB_PD, luaopen_pd, pd_map )\
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_ROM( AUXLIB_UART, luaopen_uart, uart_map )\
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_ROM( AUXLIB_TERM, luaopen_term, term_map )\
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_ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
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_ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
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_ROM( AUXLIB_CPU, luaopen_cpu, cpu_map )\
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_ROM( AUXLIB_ELUA, luaopen_elua, elua_map )\
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_ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
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ADCLINE\
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_ROM( AUXLIB_CAN, luaopen_can, can_map )\
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_ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
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RPCLINE\
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LCDLINE\
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_ROM( AUXLIB_ELUA, luaopen_elua, elua_map )\
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_ROM( LUA_MATHLIBNAME, luaopen_math, math_map )\
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PLATLINE
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// *****************************************************************************
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// Configuration data
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#define EGC_INITIAL_MODE 1
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// Virtual timers (0 if not used)
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#define VTMR_NUM_TIMERS 4
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#define VTMR_FREQ_HZ 10
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// Number of resources (0 if not available/not implemented)
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#define NUM_PIO 5
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#define NUM_SPI 3
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#define NUM_UART 6
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#define NUM_TIMER 12
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#define NUM_PHYS_TIMER 12
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#define NUM_PWM 4
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#define NUM_ADC 16
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#define NUM_CAN 1
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// Enable RX buffering on UART
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//#define BUF_ENABLE_UART
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//#define CON_BUF_SIZE BUF_SIZE_128
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// ADC Configuration Params
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#define ADC_BIT_RESOLUTION 12
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#define BUF_ENABLE_ADC
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#define ADC_BUF_SIZE BUF_SIZE_2
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// These should be adjusted to support multiple ADC devices
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#define ADC_TIMER_FIRST_ID 0
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#define ADC_NUM_TIMERS 4
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// RPC boot options
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#define RPC_UART_ID CON_UART_ID
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#define RPC_UART_SPEED CON_UART_SPEED
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// MMCFS Support (FatFs on SD/MMC)
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// For STM32F407VGT6 - PA5 = CLK, PA6 = MISO, PA7 = MOSI, PA4 = CS
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#define MMCFS_TICK_HZ 10
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#define MMCFS_TICK_MS ( 1000 / MMCFS_TICK_HZ )
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#define MMCFS_CS_PORT 1
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#define MMCFS_CS_PIN 11
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#define MMCFS_SPI_NUM 1
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// CPU frequency (needed by the CPU module, 0 if not used)
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u32 platform_s_cpu_get_frequency();
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#define CPU_FREQUENCY platform_s_cpu_get_frequency()
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// PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
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#define PIO_PREFIX 'A'
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// Pins per port configuration:
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// #define PIO_PINS_PER_PORT (n) if each port has the same number of pins, or
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// #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array
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// Use #define PIO_PINS_PER_PORT 0 if this isn't needed
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#define PIO_PINS_PER_PORT 16
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// Remote file system data
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#define RFS_BUFFER_SIZE BUF_SIZE_512
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#define RFS_UART_ID 0
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#define RFS_TIMEOUT 100000
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#define RFS_UART_SPEED 115200
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// Linenoise buffer sizes
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#define LINENOISE_HISTORY_SIZE_LUA 50
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#define LINENOISE_HISTORY_SIZE_SHELL 10
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// Allocator data: define your free memory zones here in two arrays
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// (start address and end address)
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// The F4 has 196K in total, but it is split into 3 sections:
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// SRAM (xrw) : ORIGIN = 0x20000000, SIZE = 128K // Major SRAM
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// CCMDATARAM (xrw) : ORIGIN = 0x10000000, SIZE = 64K // Core Coupled Data SRAM
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// BKPSRAM, SIZE = 4K // Backup SRAM
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//
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#define CCMDATARAM_SIZE ( 64 * 1024 )
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#define SRAM_SIZE ( 128 * 1024 )
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#define MEM_START_ADDRESS { ( void* )end, (void* )( CCMDATARAM_BASE ) }
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#define MEM_END_ADDRESS { ( void* )( SRAM_BASE + SRAM_SIZE - STACK_SIZE_TOTAL - 1 ), (void*)( CCMDATARAM_BASE + CCMDATARAM_SIZE - 1 ) }
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// Flash data (only for ELUA_CPU_STM32F407VG for now)
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#ifdef ELUA_CPU_STM32F407VG
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#define INTERNAL_FLASH_SIZE ( 1024 * 1024 )
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#define INTERNAL_FLASH_SECTOR_ARRAY { 16384, 16384, 16384, 16384, 65536, 131072, 131072, 131072, 131072, 131072, 131072, 131072 }
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#define INTERNAL_FLASH_START_ADDRESS 0x08000000
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#define BUILD_WOFS
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#endif // #ifdef ELUA_CPU_STM32F407VG
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// Interrupt queue size
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#define PLATFORM_INT_QUEUE_LOG_SIZE 5
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// Interrupt list
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#define INT_GPIO_POSEDGE ELUA_INT_FIRST_ID
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#define INT_GPIO_NEGEDGE ( ELUA_INT_FIRST_ID + 1 )
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#define INT_TMR_MATCH ( ELUA_INT_FIRST_ID + 2 )
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#define INT_UART_RX ( ELUA_INT_FIRST_ID + 3 )
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#define INT_ELUA_LAST INT_UART_RX
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#define PLATFORM_CPU_CONSTANTS\
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_C( INT_GPIO_POSEDGE ), \
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_C( INT_GPIO_NEGEDGE ), \
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_C( INT_TMR_MATCH ), \
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_C( INT_UART_RX )
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// Conver from GPIO_PinSourceXX to GPIO_Pin_XX
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#define GPIO_SOURCE2PIN(n) (1 << (n))
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#endif // #ifndef __PLATFORM_CONF_H__
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88
src/platform/stm32f4/stm32_pio.c
Normal file
88
src/platform/stm32f4/stm32_pio.c
Normal file
@ -0,0 +1,88 @@
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// STM32 specific PIO support
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#include "lua.h"
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#include "lualib.h"
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#include "lauxlib.h"
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#include "platform.h"
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#include "lrotable.h"
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#include "platform_conf.h"
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#include "auxmods.h"
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#include "stm32f4xx_conf.h"
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#include <string.h>
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#if LUA_OPTIMIZE_MEMORY == 0
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#error stm32.pio can only be compiled with LTR on (optram=true)
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#endif
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#define PIN_FUNC_GPIO ( -1 )
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#define PIN_FUNC_ADC ( -2 )
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#define PIN_FUNC_ALT_FIRST 0
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#define PIN_FUNC_ALT_LAST 15
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extern GPIO_TypeDef * const pio_port[];
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// Lua: stm32.pio.set_function( function, pin1, pin2, ..., pinn )
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// Function can be stm32.pio.GPIO, stm32.pio.AFx (x = 0..15), stm32.pio.ADC
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static int stm32_pio_set_function( lua_State *L )
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{
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int func = luaL_checkinteger( L, 1 ), gpio, pin, port, idx;
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int total = lua_gettop( L ), i;
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GPIO_TypeDef *base;
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if( total == 1 )
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return luaL_error( L, "no pin specified" );
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for( i = 2; i <= total; i ++ )
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{
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gpio = luaL_checkinteger( L, i );
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port = PLATFORM_IO_GET_PORT( gpio );
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pin = PLATFORM_IO_GET_PIN( gpio );
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base = pio_port[ port ];
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if( func == PIN_FUNC_GPIO )
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base->MODER &= ~( 0x03 << ( pin * 2 ) );
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else if( func == PIN_FUNC_ADC )
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base->MODER |= 0x03 << ( pin * 2 );
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else if( func >= PIN_FUNC_ALT_FIRST && func <= PIN_FUNC_ALT_LAST )
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{
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base->MODER &= ~( 0x03 << ( pin * 2 ) );
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base->MODER |= 0x02 << ( pin * 2 );
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if( pin >= 8 )
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{
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pin -= 8;
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idx = 1;
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}
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else
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idx = 0;
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base->AFR[ idx ] &= ~( 0x0F << ( pin * 4 ) );
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base->AFR[ idx ] |= func << ( pin * 4 );
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}
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}
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return 0;
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}
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// Module function map
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#define MIN_OPT_LEVEL 2
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#include "lrodefs.h"
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const LUA_REG_TYPE stm32_pio_map[] =
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{
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{ LSTRKEY( "set_function" ), LFUNCVAL( stm32_pio_set_function ) },
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{ LSTRKEY( "GPIO" ), LNUMVAL( PIN_FUNC_GPIO ) },
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{ LSTRKEY( "ADC" ), LNUMVAL( PIN_FUNC_ADC ) },
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{ LSTRKEY( "AF0" ), LNUMVAL( 0 ) },
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{ LSTRKEY( "AF1" ), LNUMVAL( 1 ) },
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{ LSTRKEY( "AF2" ), LNUMVAL( 2 ) },
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{ LSTRKEY( "AF3" ), LNUMVAL( 3 ) },
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{ LSTRKEY( "AF4" ), LNUMVAL( 4 ) },
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{ LSTRKEY( "AF5" ), LNUMVAL( 5 ) },
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{ LSTRKEY( "AF6" ), LNUMVAL( 6 ) },
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{ LSTRKEY( "AF7" ), LNUMVAL( 7 ) },
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{ LSTRKEY( "AF8" ), LNUMVAL( 8 ) },
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{ LSTRKEY( "AF9" ), LNUMVAL( 9 ) },
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{ LSTRKEY( "AF10" ), LNUMVAL( 10 ) },
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{ LSTRKEY( "AF11" ), LNUMVAL( 11 ) },
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{ LSTRKEY( "AF12" ), LNUMVAL( 12 ) },
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{ LSTRKEY( "AF13" ), LNUMVAL( 13 ) },
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{ LSTRKEY( "AF14" ), LNUMVAL( 14 ) },
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{ LSTRKEY( "AF15" ), LNUMVAL( 15 ) },
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{ LNILKEY, LNILVAL }
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};
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