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LPC17xx modified for the new build system + other changes

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- more flexible specification of the RAM structure in the build configuration file
- fix for allocator choice in build_elua.lua
This commit is contained in:
Bogdan Marinescu 2012-07-14 19:59:42 +03:00
parent f4eeedf162
commit 37e20330e7
16 changed files with 158 additions and 183 deletions
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2
boards/known/elua-puc.lua
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@ -16,7 +16,7 @@ return {
},
config = {
vtmr = { num = 4, freq = 4 },
extmem = { start = { 0xA0000000 }, size = { 8 * 1048576 } }
ram = { ext_start = { 0xA0000000 }, ext_size = { 8 * 1048576 } }
},
modules = {
generic = 'all',

2
boards/known/lpc-h2888.lua
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@ -11,7 +11,7 @@ return {
rpc = { uart = 0, speed = 115200 }
},
config = {
extmem = { start = { "SDRAM_BASE_ADDR" }, size = { "SDRAM_SIZE" } }
ram = { ext_start = { "SDRAM_BASE_ADDR" }, ext_size = { "SDRAM_SIZE" } }
},
modules = {
generic = { 'pio', 'tmr', 'pd', 'uart', 'term', 'pack', 'bit', 'elua', 'cpu', 'rpc', 'math' }

26
boards/known/mbed.lua Normal file
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@ -0,0 +1,26 @@
-- MBEd build configuration
return {
cpu = 'lpc1768',
components = {
sercon = { uart = 0, speed = 115200 },
romfs = true,
shell = true,
term = { lines = 25, cols = 80 },
linenoise = { shell_lines = 10, lua_lines = 50 },
rpc = { uart = 0, speed = 115200 },
adc = { buf_size = 4, first_timer = 0, num_timers = 4 },
xmodem = true,
lpc17xx_semifs = true
},
config = {
egc = { mode = "alloc" },
ram = { internal_rams = 2 }
},
modules = {
generic = 'all',
exclude_generic = { "spi", "can", "i2c", "net" },
platform = 'all',
}
}

14
build_elua.lua
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@ -175,7 +175,7 @@ if bdata.multi_alloc and comp.allocator == "newlib" then
io.write( utils.col_yellow( "[CONFIG] WARNING: your board has non-contigous RAM areas, but you specified an allocator ('newlib') that can't handle this configuration." ) )
print( utils.col_yellow( "Rebuild with another allocator ('multiple' or 'simple')" ) )
end
if comp.allocator == "auto" and bdata.multi_alloc then comp.allocator = "multiple" end
if comp.allocator == "auto" then comp.allocator = bdata.multi_alloc and "multiple" or "newlib" end
comp.cpu = bdata.cpu:upper()
platform = bd.get_platform_of_cpu( comp.cpu )
@ -217,18 +217,6 @@ else
end
end
-- CPU/allocator mapping (if allocator not specified)
-- TODO: this needs to go away too, since the allocator is now automatically inferred
if comp.allocator == 'auto' then
if comp.board:upper() == 'MIZAR32' or comp.cpu:upper() == 'AT32UC3A0128' then
comp.allocator = 'simple'
elseif utils.array_element_index( { 'LPC-H2888', 'ATEVK1100', 'MIZAR32', 'MBED' }, comp.board:upper() ) then
comp.allocator = 'multiple'
else
comp.allocator = 'newlib'
end
end
-- Build the compilation command now
local fscompcmd = ''
if comp.romfs == 'compile' then

62
config/configurations.lua
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@ -11,22 +11,26 @@ local use_multiple_allocator
-------------------------------------------------------------------------------
-- Attribute checkers
local function mem_checker( eldesc, vals )
local function ram_checker( eldesc, vals )
local startvals = vals.MEM_START_ADDRESS and vals.MEM_START_ADDRESS.value
local sizevals = vals.MEM_END_ADDRESS and vals.MEM_END_ADDRESS.value
local ninternal = vals._NUM_INTERNAL_RAMS.value
if ( not startvals or not sizevals ) and ninternal == 0 then
return false, "RAM configuration must be defined in element 'ram' of section 'config'"
end
if not startvals and not sizevals then return true end
if not startvals then
return false, "attribute 'start' must also be specified for element 'extmem' of section 'config'"
return false, "attribute 'ext_start' must also be specified for element 'ram' of section 'config'"
elseif not sizevals then
return false, "attribute 'size' must also be specified for element 'extmem' of section 'config'"
return false, "attribute 'ext_size' must also be specified for element 'ram' of section 'config'"
end
if #startvals == 0 then
return false, "attribute 'start' of element 'extmem' in section 'config' must have at least one element"
return false, "attribute 'ext_start' of element 'ram' in section 'config' must have at least one element"
elseif #sizevals == 0 then
return false, "attribute 'size' of element 'extmem' in section 'config' must have at least one element"
return false, "attribute 'ext_size' of element 'ram' in section 'config' must have at least one element"
end
if #startvals ~= #sizevals then
return false, "attributes 'start' and 'size' of element 'extmem' in section 'config' must have the same number of elements'"
return false, "attributes 'ext_start' and 'ext_size' of element 'ram' in section 'config' must have the same number of elements"
end
return true
end
@ -61,29 +65,38 @@ end
-- Specific generators
-- Automatically generates the MEM_START_ADDRESS and MEM_END_ADDRESS macros
-- Assumes that definitions for INTERNAL_RAM_FIRST_FREE and INTERNAL_RAM_LAST_FREE
-- Assumes that definitions for INTERNAL_RAMx_FIRST_FREE and INTERNAL_RAMx_LAST_FREE
-- exist (they should come from <cpu>.h)
local function mem_generator( desc, vals, generated )
if not vals.MEM_START_ADDRESS and not vals.MEM_END_ADDRESS then
local function ram_generator( desc, vals, generated )
-- Prepare internal memory configuration first
local ninternal = vals._NUM_INTERNAL_RAMS.value
local istart, iend = {}, {}
for i = 1, ninternal do
table.insert( istart, sf( "( u32 )( INTERNAL_RAM%d_FIRST_FREE )", i ) )
table.insert( iend, sf( "( u32 )( INTERNAL_RAM%d_LAST_FREE )", i ) )
end
if not vals.MEM_START_ADDRESS then
-- Generate configuration only for the internal memory
local gstr = gen.print_define( "MEM_START_ADDRESS", "{ ( u32 )( INTERNAL_RAM_FIRST_FREE ) }" )
gstr = gstr .. gen.print_define( "MEM_END_ADDRESS", "{ ( u32 )( INTERNAL_RAM_LAST_FREE ) }" )
local gstr = gen.print_define( "MEM_START_ADDRESS", "{ " .. table.concat( istart, "," ) .. " }" )
gstr = gstr .. gen.print_define( "MEM_END_ADDRESS", "{ " .. table.concat( iend, "," ) .. " }" )
generated.MEM_START_ADDRESS = true
generated.MEM_END_ADDRESS = true
use_multiple_allocator = ninternal > 1
return gstr
end
local function fmtval( s ) return tonumber( s ) and tostring( s ) .. "UL" or ( "( u32 )( " .. s .. " )" ) end
local startvals = vals.MEM_START_ADDRESS.value
local sizevals = vals.MEM_END_ADDRESS.value
table.insert( startvals, 1, "( u32 )( INTERNAL_RAM_FIRST_FREE )" )
table.insert( sizevals, 1, "( u32 )( INTERNAL_RAM_LAST_FREE )" )
for i = 2, #sizevals do
local startvals, sizevals = vals.MEM_START_ADDRESS.value, vals.MEM_END_ADDRESS.value
for i = 1, ninternal do
table.insert( startvals, i, sf( "( u32 )( INTERNAL_RAM%d_FIRST_FREE )", i ) )
table.insert( sizevals, i, sf( "( u32 )( INTERNAL_RAM%d_LAST_FREE )", i ) )
end
for i = ninternal + 1, #sizevals do
sizevals[ i ] = sf( "( %s + %s - 1 )", fmtval( startvals[ i ] ), fmtval( sizevals[ i ] ) )
startvals[ i ] = sf( "( %s )", fmtval( startvals[ i ] ) )
end
use_multiple_allocator = #startvals > 1
local gstr = gen.simple_gen( "MEM_START_ADDRESS", vals, generated )
gstr = gstr .. gen.simple_gen( "MEM_END_ADDRESS", vals, generated )
use_multiple_allocator = #startvals > 1
return gstr
end
@ -139,15 +152,16 @@ function init()
},
}
-- Memory configuration generator
configs.extmem = {
gen = mem_generator,
confcheck = mem_checker,
-- RAM configuration generator
configs.ram = {
gen = ram_generator,
confcheck = ram_checker,
attrs = {
start = at.array_of( at.combine_attr( 'MEM_START_ADDRESS', { at.int_attr( '' ), at.string_attr( '' ) } ) ),
size = at.array_of( at.combine_attr( 'MEM_END_ADDRESS', { at.int_attr( '', 1 ), at.string_attr( '' ) } ) ),
internal_rams = at.int_attr( '_NUM_INTERNAL_RAMS', 0, nil, 1 ),
ext_start = at.array_of( at.combine_attr( 'MEM_START_ADDRESS', { at.int_attr( '' ), at.string_attr( '' ) } ) ),
ext_size = at.array_of( at.combine_attr( 'MEM_END_ADDRESS', { at.int_attr( '', 1 ), at.string_attr( '' ) } ) ),
},
required = {}
required = { internal_rams = 1, ext_start = {}, ext_size = {} }
}
-- All done

4
src/platform/at91sam7x/cpu_at91sam7x256.h
View File

@ -31,8 +31,8 @@
#ifndef SRAM_SIZE
#define SRAM_SIZE 0x10000
#endif
#define INTERNAL_RAM_FIRST_FREE end
#define INTERNAL_RAM_LAST_FREE ( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
#define INTERNAL_RAM1_FIRST_FREE end
#define INTERNAL_RAM1_LAST_FREE ( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
#define PLATFORM_CPU_CONSTANTS_INTS\
_C( INT_UART_RX ),

19
src/platform/lpc17xx/build_config.lua Normal file
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@ -0,0 +1,19 @@
-- This is the platform specific board configuration file
-- It is used by the generic board configuration system (config/)
module( ..., package.seeall )
-- Add specific components to the 'components' table
function add_platform_components( t )
t.lpc17xx_semifs = { macro = "BUILD_SEMIFS" }
end
-- Add specific configuration to the 'configs' table
function add_platform_configs( t )
end
-- Return an array of all the available platform modules for the given cpu
function get_platform_modules( cpu )
return { pio = {} }
end

43
src/platform/lpc17xx/cpu_lpc1768.h Normal file
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@ -0,0 +1,43 @@
// eLua platform configuration
#ifndef __CPU_LPC1768_H__
#define __CPU_LPC1768_H__
#include "stacks.h"
// Number of resources (0 if not available/not implemented)
#define NUM_PIO 5
#define NUM_SPI 0
#define NUM_UART 4
#define NUM_PWM 6
#define NUM_ADC 8
#define NUM_CAN 0
#define NUM_TIMER 4
#define ADC_BIT_RESOLUTION 12
// CPU frequency (needed by the CPU module, 0 if not used)
u32 mbed_get_cpu_frequency();
#define CPU_FREQUENCY mbed_get_cpu_frequency()
// PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
#define PIO_PREFIX '0'
// Pins per port configuration:
// #define PIO_PINS_PER_PORT (n) if each port has the same number of pins, or
// #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array
// Use #define PIO_PINS_PER_PORT 0 if this isn't needed
#define PIO_PINS_PER_PORT 32
// Allocator data: define your free memory zones here in two arrays
// (start address and end address)
#define SRAM_ORIGIN 0x10000000
#define SRAM_SIZE 0x8000
#define SRAM2_ORIGIN 0x2007C000
#define SRAM2_SIZE 0x8000
#define INTERNAL_RAM1_FIRST_FREE end
#define INTERNAL_RAM1_LAST_FREE ( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
#define INTERNAL_RAM2_FIRST_FREE SRAM2_ORIGIN
#define INTERNAL_RAM2_LAST_FREE ( SRAM2_ORIGIN + SRAM2_SIZE - 1 )
#endif // #ifndef __CPU_LPC1768_H__

130
src/platform/lpc17xx/platform_conf.h
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@ -1,130 +0,0 @@
// eLua platform configuration
#ifndef __PLATFORM_CONF_H__
#define __PLATFORM_CONF_H__
#include "auxmods.h"
#include "stacks.h"
#include "type.h"
// *****************************************************************************
// Define here what components you want for this platform
#define BUILD_XMODEM
#define BUILD_SHELL
#define BUILD_ROMFS
#define BUILD_TERM
#define BUILD_CON_GENERIC
#define BUILD_ADC
#define BUILD_SEMIFS
#define BUILD_RPC
#define PLATFORM_HAS_SYSTIMER
// *****************************************************************************
// UART/Timer IDs configuration data (used in main.c)
#define CON_UART_ID 0
#define CON_UART_SPEED 115200
#define TERM_LINES 25
#define TERM_COLS 80
// *****************************************************************************
// Auxiliary libraries that will be compiled for this platform
#ifdef BUILD_ADC
#define ADCLINE _ROM( AUXLIB_ADC, luaopen_adc, adc_map )
#else
#define ADCLINE
#endif
// RPC
#if defined( BUILD_RPC )
#define RPCLINE _ROM( AUXLIB_RPC, luaopen_rpc, rpc_map )
#else
#define RPCLINE
#endif
// The name of the platform specific libs table
#define PS_LIB_TABLE_NAME "mbed"
#define LUA_PLATFORM_LIBS_ROM\
_ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
_ROM( AUXLIB_UART, luaopen_uart, uart_map )\
_ROM( AUXLIB_PD, luaopen_pd, pd_map )\
_ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
ADCLINE\
_ROM( AUXLIB_TERM, luaopen_term, term_map )\
_ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
_ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
_ROM( AUXLIB_CPU, luaopen_cpu, cpu_map )\
_ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
RPCLINE\
_ROM( LUA_MATHLIBNAME, luaopen_math, math_map )\
_ROM( AUXLIB_ELUA, luaopen_elua, elua_map )\
_ROM( PS_LIB_TABLE_NAME, luaopen_platform, platform_map )
// *****************************************************************************
// Configuration data
#define EGC_INITIAL_MODE 1
// Virtual timers (0 if not used)
#define VTMR_NUM_TIMERS 0
#define VTMR_FREQ_HZ 4
// Number of resources (0 if not available/not implemented)
#define NUM_PIO 5
#define NUM_SPI 0
#define NUM_UART 4
#define NUM_PWM 6
#define NUM_ADC 8
#define NUM_CAN 0
// If virtual timers are enabled, the last timer will be used only for them
#if VTMR_NUM_TIMERS == 0
#define NUM_TIMER 4
#else
#define NUM_TIMER 3
#endif
// Enable RX buffering on UART
// [TODO] make this happen
//#define BUF_ENABLE_UART
//#define CON_BUF_SIZE BUF_SIZE_128
// ADC Configuration Params
#define ADC_BIT_RESOLUTION 12
#define BUF_ENABLE_ADC
#define ADC_BUF_SIZE BUF_SIZE_2
// These should be adjusted to support multiple ADC devices
#define ADC_TIMER_FIRST_ID 0
#define ADC_NUM_TIMERS 4
// RPC
#define RPC_UART_ID CON_UART_ID
// CPU frequency (needed by the CPU module, 0 if not used)
u32 mbed_get_cpu_frequency();
#define CPU_FREQUENCY mbed_get_cpu_frequency()
// PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
#define PIO_PREFIX '0'
// Pins per port configuration:
// #define PIO_PINS_PER_PORT (n) if each port has the same number of pins, or
// #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array
// Use #define PIO_PINS_PER_PORT 0 if this isn't needed
#define PIO_PINS_PER_PORT 32
// Allocator data: define your free memory zones here in two arrays
// (start address and end address)
#define SRAM_ORIGIN 0x10000000
#define SRAM_SIZE 0x8000
#define SRAM2_ORIGIN 0x2007C000
#define SRAM2_SIZE 0x8000
#define MEM_START_ADDRESS { ( void* )end, ( void* )SRAM2_ORIGIN }
#define MEM_END_ADDRESS { ( void* )( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 ), ( void* )( SRAM2_ORIGIN + SRAM2_SIZE - 1 ) }
#endif // #ifndef __PLATFORM_CONF_H__

15
src/platform/lpc17xx/platform_generic.h Normal file
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@ -0,0 +1,15 @@
// Generic platform-wide header
#ifndef __PLATFORM_GENERIC_H__
#define __PLATFORM_GENERIC_H__
#define PLATFORM_HAS_SYSTIMER
// If virtual timers are enabled, the last timer will be used only for them
#if VTMR_NUM_TIMERS > 0
#undef NUM_TIMER
#define NUM_TIMER 3
#endif
#endif // #ifndef __PLATFORM_GENERIC_H__

4
src/platform/lpc24xx/cpu_lpc2468.h
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@ -33,8 +33,8 @@
// Internal RAM
#define SRAM_ORIGIN 0x40000000
#define SRAM_SIZE 0x10000 // [TODO]: make this 96k?
#define INTERNAL_RAM_FIRST_FREE end
#define INTERNAL_RAM_LAST_FREE ( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
#define INTERNAL_RAM1_FIRST_FREE end
#define INTERNAL_RAM1_LAST_FREE ( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
// Interrupt list for this CPU
#define PLATFORM_CPU_CONSTANTS_INTS\

4
src/platform/lpc288x/cpu_lpc2888.h
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@ -30,8 +30,8 @@
// (start address and end address)
#define SRAM_ORIGIN 0x00400000
#define SRAM_SIZE 0x10000
#define INTERNAL_RAM_FIRST_FREE end
#define INTERNAL_RAM_LAST_FREE ( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
#define INTERNAL_RAM1_FIRST_FREE end
#define INTERNAL_RAM1_LAST_FREE ( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
#endif // #ifndef __CPU_LPC2888_H__

4
src/platform/sim/cpu_linux.h
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@ -25,8 +25,8 @@
extern void *memory_start_address;
extern void *memory_end_address;
#define MEM_LENGTH (1024 * 1024)
#define INTERNAL_RAM_FIRST_FREE ( void* )memory_start_address
#define INTERNAL_RAM_LAST_FREE ( void* )memory_end_address
#define INTERNAL_RAM1_FIRST_FREE ( void* )memory_start_address
#define INTERNAL_RAM1_LAST_FREE ( void* )memory_end_address
#endif

4
src/platform/stm32/cpu_stm32f103re.h
View File

@ -33,8 +33,8 @@ u32 platform_s_cpu_get_frequency();
// Internal memory data
#define SRAM_SIZE ( 64 * 1024 )
#define INTERNAL_RAM_FIRST_FREE end
#define INTERNAL_RAM_LAST_FREE ( SRAM_BASE + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
#define INTERNAL_RAM1_FIRST_FREE end
#define INTERNAL_RAM1_LAST_FREE ( SRAM_BASE + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
#define INTERNAL_FLASH_SIZE ( 512 * 1024 )
#define INTERNAL_FLASH_SECTOR_SIZE 2048

4
src/platform/str7/cpu_str711fr2.h
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@ -27,8 +27,8 @@
#define SRAM_ORIGIN 0x20000000
#define SRAM_SIZE 0x10000
#define INTERNAL_RAM_FIRST_FREE end
#define INTERNAL_RAM_LAST_FREE ( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
#define INTERNAL_RAM1_FIRST_FREE end
#define INTERNAL_RAM1_LAST_FREE ( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
#endif // #ifndef __CPU_STR711FR2_H__

4
src/platform/str9/cpu_str912faw44.h
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@ -39,8 +39,8 @@ u32 SCU_GetMCLKFreqValue();
// (start address and end address)
#define SRAM_ORIGIN 0x40000000
#define SRAM_SIZE 0x18000
#define INTERNAL_RAM_FIRST_FREE end
#define INTERNAL_RAM_LAST_FREE ( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
#define INTERNAL_RAM1_FIRST_FREE end
#define INTERNAL_RAM1_LAST_FREE ( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 )
#define PLATFORM_CPU_CONSTANTS_INTS\
_C( INT_GPIO_POSEDGE ),\