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https://github.com/elua/elua.git
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Merge pull request #91 from ramangopalan/master
EBU: Invoke EBU initialization for the SDRAM board
This commit is contained in:
Bogdan Marinescu
GitHub
commit
3bb7cf88ce
@ -25,7 +25,7 @@ return {
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xmc45_disp = false,
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wofs = false,
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romfs = true,
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mmcfs = { spi = 0, cs_port = 0, cs_pin = 0 },
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-- mmcfs = { spi = 0, cs_port = 0, cs_pin = 0 },
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shell = true,
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term = { lines = 25, cols = 80 },
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linenoise = { shell_lines = 10, lua_lines = 50 },
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@ -33,7 +33,7 @@ return {
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},
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config = {
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egc = { mode = "alloc" },
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ram = { internal_rams = 3 },
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ram = { internal_rams = 4 },
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},
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modules = {
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generic = { 'all', '-i2c', '-net', '-adc', '-spi', '-uart', '-can', '-pwm', '-rpc' },
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@ -32,11 +32,15 @@
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#define DSRAM2_BASE 0x30000000
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#define PSRAM_SIZE ( 64 * 1024 )
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#define PSRAM_BASE 0x10000000
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#define SDRAM_SIZE ( 8 * 1024 * 1024 )
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#define SDRAM_BASE 0x60000000
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#define INTERNAL_RAM1_FIRST_FREE end
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#define INTERNAL_RAM1_LAST_FREE ( DSRAM1_BASE + DSRAM1_SIZE - STACK_SIZE_TOTAL - 1 )
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#define INTERNAL_RAM2_FIRST_FREE DSRAM2_BASE
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#define INTERNAL_RAM2_LAST_FREE ( DSRAM2_BASE + DSRAM2_SIZE - 1 )
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#define INTERNAL_RAM3_FIRST_FREE PSRAM_BASE
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#define INTERNAL_RAM3_LAST_FREE ( PSRAM_BASE + PSRAM_SIZE - 1 )
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#define INTERNAL_RAM4_FIRST_FREE SDRAM_BASE
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#define INTERNAL_RAM4_LAST_FREE ( SDRAM_BASE + SDRAM_SIZE - 1 )
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#endif // #ifndef __CPU_XMC4500E144K1024_H__
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@ -53,5 +53,31 @@ const LUA_REG_TYPE disp_map[] =
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{ LSTRKEY( "init" ), LFUNCVAL( disp_init ) },
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{ LSTRKEY( "clear" ), LFUNCVAL( disp_clear ) },
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{ LSTRKEY( "print" ), LFUNCVAL( disp_stringDraw ) },
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/* Expose colors from GUI.h */
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{ LSTRKEY( "GUI_BLUE" ), LNUMVAL( GUI_BLUE ) },
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{ LSTRKEY( "GUI_GREEN" ), LNUMVAL( GUI_GREEN ) },
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{ LSTRKEY( "GUI_RED" ), LNUMVAL( GUI_RED ) },
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{ LSTRKEY( "GUI_CYAN" ), LNUMVAL( GUI_CYAN ) },
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{ LSTRKEY( "GUI_MAGENTA" ), LNUMVAL( GUI_MAGENTA ) },
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{ LSTRKEY( "GUI_YELLOW" ), LNUMVAL( GUI_YELLOW ) },
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{ LSTRKEY( "GUI_LIGHTBLUE" ), LNUMVAL( GUI_LIGHTBLUE ) },
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{ LSTRKEY( "GUI_LIGHTGREEN" ), LNUMVAL( GUI_LIGHTGREEN ) },
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{ LSTRKEY( "GUI_LIGHTRED" ), LNUMVAL( GUI_LIGHTRED ) },
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{ LSTRKEY( "GUI_LIGHTCYAN" ), LNUMVAL( GUI_LIGHTCYAN ) },
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{ LSTRKEY( "GUI_LIGHTMAGENTA" ), LNUMVAL( GUI_LIGHTMAGENTA ) },
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{ LSTRKEY( "GUI_LIGHTYELLOW" ), LNUMVAL( GUI_LIGHTYELLOW ) },
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{ LSTRKEY( "GUI_DARKBLUE" ), LNUMVAL( GUI_DARKBLUE ) },
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{ LSTRKEY( "GUI_DARKRED" ), LNUMVAL( GUI_DARKRED ) },
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{ LSTRKEY( "GUI_DARKCYAN" ), LNUMVAL( GUI_DARKCYAN ) },
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{ LSTRKEY( "GUI_DARKMAGENTA" ), LNUMVAL( GUI_DARKMAGENTA ) },
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{ LSTRKEY( "GUI_DARKYELLOW" ), LNUMVAL( GUI_DARKYELLOW ) },
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{ LSTRKEY( "GUI_WHITE" ), LNUMVAL( GUI_WHITE ) },
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{ LSTRKEY( "GUI_LIGHTGRAY" ), LNUMVAL( GUI_LIGHTGRAY ) },
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{ LSTRKEY( "GUI_GRAY" ), LNUMVAL( GUI_GRAY ) },
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{ LSTRKEY( "GUI_DARKGRAY" ), LNUMVAL( GUI_DARKGRAY ) },
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{ LSTRKEY( "GUI_BLACK" ), LNUMVAL( GUI_BLACK ) },
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{ LSTRKEY( "GUI_BROWN" ), LNUMVAL( GUI_BROWN ) },
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{ LSTRKEY( "GUI_ORANGE" ), LNUMVAL( GUI_ORANGE ) },
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{ LSTRKEY( "GUI_TRANSPARENT" ), LNUMVAL( GUI_TRANSPARENT ) },
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{ LNILKEY, LNILVAL }
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};
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@ -90,457 +90,413 @@
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XMC_EBU_t *const ebumodule = (XMC_EBU_t *)EBU;
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XMC_EBU_CONFIG_t ebuobj = {
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.ebu_clk_config.ebu_clock_divide_ratio = XMC_EBU_CLOCK_DIVIDED_BY_2,
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.ebu_clk_config.ebu_div2_clk_mode = XMC_EBU_DIV2_CLK_MODE_ON,
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.ebu_clk_config.ebu_clk_mode = XMC_EBU_CLK_MODE_SYNCHRONOUS_TO_CPU,
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.ebu_mode_config.ebu_sdram_tristate = false,
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.ebu_mode_config.ebu_extlock = false,
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.ebu_mode_config.ebu_arbsync = true,
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.ebu_mode_config.ebu_arbitration_mode = XMC_EBU_ARB_MODE_SOLE_MASTER_MODE,
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.ebu_mode_config.bus_timeout_control = 0xFFU,
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.ebu_mode_config.ebu_ale_mode = XMC_EBU_ALE_OUTPUT_IS_INV_ADV,
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.ebu_free_pins_to_gpio.address_pins_gpio = 0x1ff,
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.ebu_free_pins_to_gpio.adv_pin_gpio = false
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.ebu_clk_config.ebu_clock_divide_ratio = XMC_EBU_CLOCK_DIVIDED_BY_2,
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.ebu_clk_config.ebu_div2_clk_mode = XMC_EBU_DIV2_CLK_MODE_ON,
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.ebu_clk_config.ebu_clk_mode = XMC_EBU_CLK_MODE_SYNCHRONOUS_TO_CPU,
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.ebu_mode_config.ebu_sdram_tristate = false,
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.ebu_mode_config.ebu_extlock = false,
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.ebu_mode_config.ebu_arbsync = true,
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.ebu_mode_config.ebu_arbitration_mode = XMC_EBU_ARB_MODE_SOLE_MASTER_MODE,
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.ebu_mode_config.bus_timeout_control = 0xFFU,
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.ebu_mode_config.ebu_ale_mode = XMC_EBU_ALE_OUTPUT_IS_INV_ADV,
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.ebu_free_pins_to_gpio.address_pins_gpio = 0x1ff,
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.ebu_free_pins_to_gpio.adv_pin_gpio = false
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};
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XMC_EBU_REGION_t ebureadwriteconfig = {
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.read_config.ebu_region_no = 0x0U,
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.read_config.ebu_bus_read_config.ebu_burst_length_sync = 0x4U,
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.read_config.ebu_bus_read_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
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.read_config.ebu_bus_read_config.ebu_burst_flash_clock_feedback = XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE,
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.read_config.ebu_bus_read_config.ebu_device_addressing_mode = XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS,
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.read_config.ebu_bus_read_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
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.read_config.ebu_bus_read_config.address_cycles = 0xFU,
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.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
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.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
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.read_config.ebu_bus_read_config.command_delay_lines = 0xFU,
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.read_config.ebu_bus_read_config.ebu_ext_data = 0x0U,
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.read_config.ebu_bus_read_config.ebu_freq_ext_clk_pin = 0x0U,
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.read_config.ebu_bus_read_config.ebu_recovery_cycles_between_different_regions = 0xFU,
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.read_config.ebu_bus_read_config.ebu_recovery_cycles_after_read_accesses = 0x7U,
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.read_config.ebu_bus_read_config.ebu_programmed_wait_states_for_read_accesses = 0x4U,
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.write_config.ebu_region_no = 0x0U,
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.write_config.ebu_bus_write_config.ebu_burst_length_sync = 0x04U,
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.write_config.ebu_bus_write_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
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.write_config.ebu_bus_write_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
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.write_config.ebu_bus_write_config.address_cycles = 0xFU,
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.write_config.ebu_bus_write_config.address_hold_cycles = 0xFU,
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.write_config.ebu_bus_write_config.command_delay_lines = 0xFU,
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.write_config.ebu_bus_write_config.ebu_ext_data = 0x0U,
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.write_config.ebu_bus_write_config.ebu_freq_ext_clk_pin = 0x0U,
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.write_config.ebu_bus_write_config.ebu_recovery_cycles_between_different_regions = 0xFU,
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.write_config.ebu_bus_write_config.ebu_recovery_cycles_after_write_accesses = 0x7U,
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.write_config.ebu_bus_write_config.ebu_programmed_wait_states_for_write_accesses = 0x4U,
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.read_config.ebu_region_no = 0x0U,
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.read_config.ebu_bus_read_config.ebu_burst_length_sync = 0x4U,
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.read_config.ebu_bus_read_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
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.read_config.ebu_bus_read_config.ebu_burst_flash_clock_feedback = XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE,
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.read_config.ebu_bus_read_config.ebu_device_addressing_mode = XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS,
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.read_config.ebu_bus_read_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
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.read_config.ebu_bus_read_config.address_cycles = 0xFU,
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.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
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.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
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.read_config.ebu_bus_read_config.command_delay_lines = 0xFU,
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.read_config.ebu_bus_read_config.ebu_ext_data = 0x0U,
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.read_config.ebu_bus_read_config.ebu_freq_ext_clk_pin = 0x0U,
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.read_config.ebu_bus_read_config.ebu_recovery_cycles_between_different_regions = 0xFU,
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.read_config.ebu_bus_read_config.ebu_recovery_cycles_after_read_accesses = 0x7U,
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.read_config.ebu_bus_read_config.ebu_programmed_wait_states_for_read_accesses = 0x4U,
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.write_config.ebu_region_no = 0x0U,
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.write_config.ebu_bus_write_config.ebu_burst_length_sync = 0x04U,
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.write_config.ebu_bus_write_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
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.write_config.ebu_bus_write_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
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.write_config.ebu_bus_write_config.address_cycles = 0xFU,
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.write_config.ebu_bus_write_config.address_hold_cycles = 0xFU,
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.write_config.ebu_bus_write_config.command_delay_lines = 0xFU,
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.write_config.ebu_bus_write_config.ebu_ext_data = 0x0U,
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.write_config.ebu_bus_write_config.ebu_freq_ext_clk_pin = 0x0U,
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.write_config.ebu_bus_write_config.ebu_recovery_cycles_between_different_regions = 0xFU,
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.write_config.ebu_bus_write_config.ebu_recovery_cycles_after_write_accesses = 0x7U,
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.write_config.ebu_bus_write_config.ebu_programmed_wait_states_for_write_accesses = 0x4U,
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};
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XMC_EBU_REGION_t ebureadwriteconfig_1 = {
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.read_config.ebu_region_no = 0x1U,
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.read_config.ebu_bus_read_config.ebu_burst_length_sync = 0x4U,
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.read_config.ebu_bus_read_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
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.read_config.ebu_bus_read_config.ebu_burst_flash_clock_feedback = XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE,
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.read_config.ebu_bus_read_config.ebu_device_addressing_mode = XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS,
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.read_config.ebu_bus_read_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
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.read_config.ebu_bus_read_config.address_cycles = 0xFU,
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.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
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.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
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.read_config.ebu_bus_read_config.command_delay_lines = 0xFU,
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.read_config.ebu_bus_read_config.ebu_ext_data = 0x0U,
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.read_config.ebu_bus_read_config.ebu_freq_ext_clk_pin = 0x0U,
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.read_config.ebu_bus_read_config.ebu_recovery_cycles_between_different_regions = 0xFU,
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.read_config.ebu_bus_read_config.ebu_recovery_cycles_after_read_accesses = 0x7U,
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.read_config.ebu_bus_read_config.ebu_programmed_wait_states_for_read_accesses = 0x4U,
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.write_config.ebu_region_no = 0x1U,
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.write_config.ebu_bus_write_config.ebu_burst_length_sync = 0x04U,
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.write_config.ebu_bus_write_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
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.write_config.ebu_bus_write_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
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.write_config.ebu_bus_write_config.address_cycles = 0xFU,
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.write_config.ebu_bus_write_config.address_hold_cycles = 0xFU,
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.write_config.ebu_bus_write_config.command_delay_lines = 0xFU,
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.write_config.ebu_bus_write_config.ebu_ext_data = 0x0U,
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.write_config.ebu_bus_write_config.ebu_freq_ext_clk_pin = 0x0U,
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.write_config.ebu_bus_write_config.ebu_recovery_cycles_between_different_regions = 0xFU,
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.write_config.ebu_bus_write_config.ebu_recovery_cycles_after_write_accesses = 0x7U,
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.write_config.ebu_bus_write_config.ebu_programmed_wait_states_for_write_accesses = 0x4U,
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.read_config.ebu_region_no = 0x1U,
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.read_config.ebu_bus_read_config.ebu_burst_length_sync = 0x4U,
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.read_config.ebu_bus_read_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
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.read_config.ebu_bus_read_config.ebu_burst_flash_clock_feedback = XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE,
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.read_config.ebu_bus_read_config.ebu_device_addressing_mode = XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS,
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.read_config.ebu_bus_read_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
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.read_config.ebu_bus_read_config.address_cycles = 0xFU,
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.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
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.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
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.read_config.ebu_bus_read_config.command_delay_lines = 0xFU,
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.read_config.ebu_bus_read_config.ebu_ext_data = 0x0U,
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.read_config.ebu_bus_read_config.ebu_freq_ext_clk_pin = 0x0U,
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.read_config.ebu_bus_read_config.ebu_recovery_cycles_between_different_regions = 0xFU,
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.read_config.ebu_bus_read_config.ebu_recovery_cycles_after_read_accesses = 0x7U,
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.read_config.ebu_bus_read_config.ebu_programmed_wait_states_for_read_accesses = 0x4U,
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.write_config.ebu_region_no = 0x1U,
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.write_config.ebu_bus_write_config.ebu_burst_length_sync = 0x04U,
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.write_config.ebu_bus_write_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
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.write_config.ebu_bus_write_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
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.write_config.ebu_bus_write_config.address_cycles = 0xFU,
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.write_config.ebu_bus_write_config.address_hold_cycles = 0xFU,
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.write_config.ebu_bus_write_config.command_delay_lines = 0xFU,
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.write_config.ebu_bus_write_config.ebu_ext_data = 0x0U,
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.write_config.ebu_bus_write_config.ebu_freq_ext_clk_pin = 0x0U,
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.write_config.ebu_bus_write_config.ebu_recovery_cycles_between_different_regions = 0xFU,
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.write_config.ebu_bus_write_config.ebu_recovery_cycles_after_write_accesses = 0x7U,
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.write_config.ebu_bus_write_config.ebu_programmed_wait_states_for_write_accesses = 0x4U,
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};
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XMC_EBU_REGION_t ebureadwriteconfig_2 = {
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.read_config.ebu_region_no = 0x2U,
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.read_config.ebu_bus_read_config.ebu_burst_length_sync = 0x4U,
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.read_config.ebu_bus_read_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
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.read_config.ebu_bus_read_config.ebu_burst_flash_clock_feedback = XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE,
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.read_config.ebu_bus_read_config.ebu_device_addressing_mode = XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS,
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.read_config.ebu_bus_read_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
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.read_config.ebu_bus_read_config.address_cycles = 0xFU,
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.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
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.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
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.read_config.ebu_bus_read_config.command_delay_lines = 0xFU,
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.read_config.ebu_bus_read_config.ebu_ext_data = 0x0U,
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.read_config.ebu_bus_read_config.ebu_freq_ext_clk_pin = 0x0U,
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.read_config.ebu_bus_read_config.ebu_recovery_cycles_between_different_regions = 0xFU,
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.read_config.ebu_bus_read_config.ebu_recovery_cycles_after_read_accesses = 0x7U,
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.read_config.ebu_bus_read_config.ebu_programmed_wait_states_for_read_accesses = 0x4U,
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.write_config.ebu_region_no = 0x2U,
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.write_config.ebu_bus_write_config.ebu_burst_length_sync = 0x04U,
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.write_config.ebu_bus_write_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
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.write_config.ebu_bus_write_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
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.write_config.ebu_bus_write_config.address_cycles = 0xFU,
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.write_config.ebu_bus_write_config.address_hold_cycles = 0xFU,
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.write_config.ebu_bus_write_config.command_delay_lines = 0xFU,
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.write_config.ebu_bus_write_config.ebu_ext_data = 0x0U,
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.write_config.ebu_bus_write_config.ebu_freq_ext_clk_pin = 0x0U,
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.write_config.ebu_bus_write_config.ebu_recovery_cycles_between_different_regions = 0xFU,
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.write_config.ebu_bus_write_config.ebu_recovery_cycles_after_write_accesses = 0x7U,
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.write_config.ebu_bus_write_config.ebu_programmed_wait_states_for_write_accesses = 0x4U,
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.read_config.ebu_region_no = 0x2U,
|
||||
.read_config.ebu_bus_read_config.ebu_burst_length_sync = 0x4U,
|
||||
.read_config.ebu_bus_read_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
|
||||
.read_config.ebu_bus_read_config.ebu_burst_flash_clock_feedback = XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE,
|
||||
.read_config.ebu_bus_read_config.ebu_device_addressing_mode = XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS,
|
||||
.read_config.ebu_bus_read_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
|
||||
.read_config.ebu_bus_read_config.address_cycles = 0xFU,
|
||||
.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
|
||||
.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
|
||||
.read_config.ebu_bus_read_config.command_delay_lines = 0xFU,
|
||||
.read_config.ebu_bus_read_config.ebu_ext_data = 0x0U,
|
||||
.read_config.ebu_bus_read_config.ebu_freq_ext_clk_pin = 0x0U,
|
||||
.read_config.ebu_bus_read_config.ebu_recovery_cycles_between_different_regions = 0xFU,
|
||||
.read_config.ebu_bus_read_config.ebu_recovery_cycles_after_read_accesses = 0x7U,
|
||||
.read_config.ebu_bus_read_config.ebu_programmed_wait_states_for_read_accesses = 0x4U,
|
||||
.write_config.ebu_region_no = 0x2U,
|
||||
.write_config.ebu_bus_write_config.ebu_burst_length_sync = 0x04U,
|
||||
.write_config.ebu_bus_write_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
|
||||
.write_config.ebu_bus_write_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
|
||||
.write_config.ebu_bus_write_config.address_cycles = 0xFU,
|
||||
.write_config.ebu_bus_write_config.address_hold_cycles = 0xFU,
|
||||
.write_config.ebu_bus_write_config.command_delay_lines = 0xFU,
|
||||
.write_config.ebu_bus_write_config.ebu_ext_data = 0x0U,
|
||||
.write_config.ebu_bus_write_config.ebu_freq_ext_clk_pin = 0x0U,
|
||||
.write_config.ebu_bus_write_config.ebu_recovery_cycles_between_different_regions = 0xFU,
|
||||
.write_config.ebu_bus_write_config.ebu_recovery_cycles_after_write_accesses = 0x7U,
|
||||
.write_config.ebu_bus_write_config.ebu_programmed_wait_states_for_write_accesses = 0x4U,
|
||||
};
|
||||
|
||||
XMC_EBU_REGION_t ebureadwriteconfig_3 = {
|
||||
|
||||
.read_config.ebu_region_no = 0x3U,
|
||||
.read_config.ebu_bus_read_config.ebu_burst_length_sync = 0x4U,
|
||||
.read_config.ebu_bus_read_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
|
||||
.read_config.ebu_bus_read_config.ebu_burst_flash_clock_feedback = XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE,
|
||||
.read_config.ebu_bus_read_config.ebu_device_addressing_mode = XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS,
|
||||
.read_config.ebu_bus_read_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
|
||||
.read_config.ebu_bus_read_config.address_cycles = 0xFU,
|
||||
.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
|
||||
.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
|
||||
.read_config.ebu_bus_read_config.command_delay_lines = 0xFU,
|
||||
.read_config.ebu_bus_read_config.ebu_ext_data = 0x0U,
|
||||
.read_config.ebu_bus_read_config.ebu_freq_ext_clk_pin = 0x0U,
|
||||
.read_config.ebu_bus_read_config.ebu_recovery_cycles_between_different_regions = 0xFU,
|
||||
.read_config.ebu_bus_read_config.ebu_recovery_cycles_after_read_accesses = 0x7U,
|
||||
.read_config.ebu_bus_read_config.ebu_programmed_wait_states_for_read_accesses = 0x4U,
|
||||
.write_config.ebu_region_no = 0x3U,
|
||||
.write_config.ebu_bus_write_config.ebu_burst_length_sync = 0x04U,
|
||||
.write_config.ebu_bus_write_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
|
||||
.write_config.ebu_bus_write_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
|
||||
.write_config.ebu_bus_write_config.address_cycles = 0xFU,
|
||||
.write_config.ebu_bus_write_config.address_hold_cycles = 0xFU,
|
||||
.write_config.ebu_bus_write_config.command_delay_lines = 0xFU,
|
||||
.write_config.ebu_bus_write_config.ebu_ext_data = 0x0U,
|
||||
.write_config.ebu_bus_write_config.ebu_freq_ext_clk_pin = 0x0U,
|
||||
.write_config.ebu_bus_write_config.ebu_recovery_cycles_between_different_regions = 0xFU,
|
||||
.write_config.ebu_bus_write_config.ebu_recovery_cycles_after_write_accesses = 0x7U,
|
||||
.write_config.ebu_bus_write_config.ebu_programmed_wait_states_for_write_accesses = 0x4U,
|
||||
.read_config.ebu_region_no = 0x3U,
|
||||
.read_config.ebu_bus_read_config.ebu_burst_length_sync = 0x4U,
|
||||
.read_config.ebu_bus_read_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
|
||||
.read_config.ebu_bus_read_config.ebu_burst_flash_clock_feedback = XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE,
|
||||
.read_config.ebu_bus_read_config.ebu_device_addressing_mode = XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS,
|
||||
.read_config.ebu_bus_read_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
|
||||
.read_config.ebu_bus_read_config.address_cycles = 0xFU,
|
||||
.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
|
||||
.read_config.ebu_bus_read_config.address_hold_cycles = 0xFU,
|
||||
.read_config.ebu_bus_read_config.command_delay_lines = 0xFU,
|
||||
.read_config.ebu_bus_read_config.ebu_ext_data = 0x0U,
|
||||
.read_config.ebu_bus_read_config.ebu_freq_ext_clk_pin = 0x0U,
|
||||
.read_config.ebu_bus_read_config.ebu_recovery_cycles_between_different_regions = 0xFU,
|
||||
.read_config.ebu_bus_read_config.ebu_recovery_cycles_after_read_accesses = 0x7U,
|
||||
.read_config.ebu_bus_read_config.ebu_programmed_wait_states_for_read_accesses = 0x4U,
|
||||
.write_config.ebu_region_no = 0x3U,
|
||||
.write_config.ebu_bus_write_config.ebu_burst_length_sync = 0x04U,
|
||||
.write_config.ebu_bus_write_config.ebu_byte_control = XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING,
|
||||
.write_config.ebu_bus_write_config.ebu_device_type = XMC_EBU_DEVICE_TYPE_SDRAM,
|
||||
.write_config.ebu_bus_write_config.address_cycles = 0xFU,
|
||||
.write_config.ebu_bus_write_config.address_hold_cycles = 0xFU,
|
||||
.write_config.ebu_bus_write_config.command_delay_lines = 0xFU,
|
||||
.write_config.ebu_bus_write_config.ebu_ext_data = 0x0U,
|
||||
.write_config.ebu_bus_write_config.ebu_freq_ext_clk_pin = 0x0U,
|
||||
.write_config.ebu_bus_write_config.ebu_recovery_cycles_between_different_regions = 0xFU,
|
||||
.write_config.ebu_bus_write_config.ebu_recovery_cycles_after_write_accesses = 0x7U,
|
||||
.write_config.ebu_bus_write_config.ebu_programmed_wait_states_for_write_accesses = 0x4U,
|
||||
};
|
||||
|
||||
XMC_EBU_SDRAM_CONFIG_t ebusdramcontrol = {
|
||||
.ebu_sdram_clk_mode= XMC_EBU_SDRAM_CLK_MODE_CONTINUOUSLY_RUNS, /**< SDRAM clock mode select */
|
||||
.ebu_sdram_mask_for_bank_tag = XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_22_to_21,//XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_22_to_21, /**< Mask for Bank Tag */
|
||||
.ebu_sdram_mask_for_row_tag = XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_8_to_0, /**< Mask for Row Tag */
|
||||
/**< Row cycle time counter: Insert (CRCE * 8) + CRC + 1 NOP cycles */
|
||||
.ebu_sdram_row_cycle_time_counter = 0x5UL,
|
||||
/**< (CRCD) Number of NOP cycles between a row address and a column address: Insert CRCD + 1 NOP cycles */
|
||||
.ebu_sdram_row_to_column_delay_counter = 0x01U,
|
||||
/**< Number of address bits from bit 0 to be used for column address */
|
||||
.ebu_sdram_width_of_column_address = XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_8_to_0,
|
||||
/**< (CRP) Number of NOP cycles inserted after a precharge command: Insert CRP + 1 NOP cycles */
|
||||
.ebu_row_precharge_time_counter= 0x1U,
|
||||
/**< (CRSC) Number of NOP cycles after a mode register set command: Insert CRSC + 1 NOP cycles */
|
||||
.ebu_mode_register_set_up_time = 0x0U,
|
||||
/**< (CRFSH) Number of refresh commands issued during powerup init sequence: Perform CRFSH + 1 refresh cycles */
|
||||
.ebu_init_refresh_commands_counter = 0x0AU,
|
||||
/**< Number of clock cycles between row activate command and a precharge command */
|
||||
.ebu_row_precharge_delay_counter = 0x0AU, //0x03U,
|
||||
.ebu_sdram_burst_length = XMC_EBU_SDRAM_BURST_LENGTH_4_LOCATION,
|
||||
.ebu_sdram_casclk_mode = 0x3U,
|
||||
.ebu_sdram_cold_start = 0x1U,
|
||||
.ebu_sdram_self_refresh_exit = true,
|
||||
.ebu_sdram_num_refresh_counter_period = 0x2U,
|
||||
.ebu_sdram_num_refresh_cmnds = 0x1U,
|
||||
.ebu_sdram_auto_refresh = 0x1U,
|
||||
.ebu_sdram_self_refresh_exit_delay = 0xFFU,
|
||||
.ebu_sdram_auto_self_refresh = 0x01U,
|
||||
.ebu_sdram_delay_on_power_down_exit = 0x07U
|
||||
.ebu_sdram_clk_mode= XMC_EBU_SDRAM_CLK_MODE_CONTINUOUSLY_RUNS, /**< SDRAM clock mode select */
|
||||
.ebu_sdram_mask_for_bank_tag = XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_22_to_21,//XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_22_to_21, /**< Mask for Bank Tag */
|
||||
.ebu_sdram_mask_for_row_tag = XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_8_to_0, /**< Mask for Row Tag */
|
||||
/**< Row cycle time counter: Insert (CRCE * 8) + CRC + 1 NOP cycles */
|
||||
.ebu_sdram_row_cycle_time_counter = 0x5UL,
|
||||
/**< (CRCD) Number of NOP cycles between a row address and a column address: Insert CRCD + 1 NOP cycles */
|
||||
.ebu_sdram_row_to_column_delay_counter = 0x01U,
|
||||
/**< Number of address bits from bit 0 to be used for column address */
|
||||
.ebu_sdram_width_of_column_address = XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_8_to_0,
|
||||
/**< (CRP) Number of NOP cycles inserted after a precharge command: Insert CRP + 1 NOP cycles */
|
||||
.ebu_row_precharge_time_counter= 0x1U,
|
||||
/**< (CRSC) Number of NOP cycles after a mode register set command: Insert CRSC + 1 NOP cycles */
|
||||
.ebu_mode_register_set_up_time = 0x0U,
|
||||
/**< (CRFSH) Number of refresh commands issued during powerup init sequence: Perform CRFSH + 1 refresh cycles */
|
||||
.ebu_init_refresh_commands_counter = 0x0AU,
|
||||
/**< Number of clock cycles between row activate command and a precharge command */
|
||||
.ebu_row_precharge_delay_counter = 0x0AU, //0x03U,
|
||||
.ebu_sdram_burst_length = XMC_EBU_SDRAM_BURST_LENGTH_4_LOCATION,
|
||||
.ebu_sdram_casclk_mode = 0x3U,
|
||||
.ebu_sdram_cold_start = 0x1U,
|
||||
.ebu_sdram_self_refresh_exit = true,
|
||||
.ebu_sdram_num_refresh_counter_period = 0x2U,
|
||||
.ebu_sdram_num_refresh_cmnds = 0x1U,
|
||||
.ebu_sdram_auto_refresh = 0x1U,
|
||||
.ebu_sdram_self_refresh_exit_delay = 0xFFU,
|
||||
.ebu_sdram_auto_self_refresh = 0x01U,
|
||||
.ebu_sdram_delay_on_power_down_exit = 0x07U
|
||||
};
|
||||
|
||||
#define TEST_SIZE 2097152 //67108864 bits total size (2^26)/32 = 0x0020 0000
|
||||
|
||||
/*Base Address of external RAM memory region */
|
||||
/* Base Address of external RAM memory region */
|
||||
#define EBU_EXT_RAM_REGION_BASE 0x60000000UL
|
||||
|
||||
/*SDRAM base address assignment */
|
||||
/* SDRAM base address assignment */
|
||||
#define SDRAM_BASE EBU_EXT_RAM_REGION_BASE
|
||||
|
||||
//*****************************************************************************
|
||||
// Name: DELAY
|
||||
//
|
||||
// Function: To provide delay
|
||||
//
|
||||
// Return : None
|
||||
//*******************************a**********************************************
|
||||
void DELAY(int n)
|
||||
{
|
||||
int i = 0;
|
||||
for(i = 0; i < n; i++)
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
/* Delay function */
|
||||
static void sdram_delay (int n) {
|
||||
int i = 0;
|
||||
|
||||
for (i = 0; i < n; i++) {
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
// Name: SDRAM_Test
|
||||
//
|
||||
// Function: Initialize and test the SDRAM on CPU board CPU_45B
|
||||
// The SDRAM Clock is equal to the system clock. Can be changed by SCU CLK LLD APIs.
|
||||
// Test time at 120MHz SDRAM clock and TEST_SIZE = 10000000 is about 7 sec
|
||||
//
|
||||
// Return Value 0: Test was ok
|
||||
// Return Value 1: Test failed
|
||||
//*****************************************************************************
|
||||
int32_t SDRAM_Test(void)
|
||||
{
|
||||
uint32_t status = 0;
|
||||
uint32_t mem_add = 0x0;
|
||||
uint32_t i = 0x0;
|
||||
uint32_t value = 0x0;
|
||||
static int32_t sdram_test_helper (void) {
|
||||
uint32_t status = 0;
|
||||
uint32_t mem_add = 0x0;
|
||||
uint32_t i = 0x0;
|
||||
uint32_t value = 0x0;
|
||||
|
||||
/* Writing to SD RAM*/
|
||||
*(volatile uint32_t *)(SDRAM_BASE) = 0x0;
|
||||
*(volatile uint32_t *)(SDRAM_BASE + 0x4) = 0x12345678;
|
||||
*(volatile uint32_t *)(SDRAM_BASE + 0x8) = 0x87654321;
|
||||
*(volatile uint32_t *)(SDRAM_BASE + 0xC) = 0xAAAA5555;
|
||||
*(volatile uint32_t *)(SDRAM_BASE + 0x10) = 0xFF0000FF;
|
||||
/* Writing to SDRAM */
|
||||
*(volatile uint32_t *)(SDRAM_BASE) = 0x0;
|
||||
*(volatile uint32_t *)(SDRAM_BASE + 0x4) = 0x12345678;
|
||||
*(volatile uint32_t *)(SDRAM_BASE + 0x8) = 0x87654321;
|
||||
*(volatile uint32_t *)(SDRAM_BASE + 0xC) = 0xAAAA5555;
|
||||
*(volatile uint32_t *)(SDRAM_BASE + 0x10) = 0xFF0000FF;
|
||||
|
||||
/* Reading from SD RAM*/
|
||||
value = *(volatile uint32_t *)(SDRAM_BASE + 0x0);
|
||||
if (value != 0x0)
|
||||
{
|
||||
status = 1;
|
||||
}
|
||||
value = *(volatile uint32_t *)(SDRAM_BASE + 0x4);
|
||||
if (value != 0x12345678)
|
||||
{
|
||||
status = 1;
|
||||
}
|
||||
value = *(volatile uint32_t *)(SDRAM_BASE + 0x8);
|
||||
if (value != 0x87654321)
|
||||
{
|
||||
status = 1;
|
||||
}
|
||||
value = *(volatile uint32_t *)(SDRAM_BASE + 0xC);
|
||||
if (value != 0xAAAA5555)
|
||||
{
|
||||
status = 1;
|
||||
}
|
||||
value = *(volatile uint32_t *)(SDRAM_BASE + 0x10);
|
||||
if (value != 0xFF0000FF)
|
||||
{
|
||||
status = 1;
|
||||
}
|
||||
/* Reading from SD RAM*/
|
||||
value = *(volatile uint32_t *)(SDRAM_BASE + 0x0);
|
||||
if (value != 0x0) {
|
||||
status = 1;
|
||||
}
|
||||
value = *(volatile uint32_t *)(SDRAM_BASE + 0x4);
|
||||
if (value != 0x12345678) {
|
||||
status = 1;
|
||||
}
|
||||
value = *(volatile uint32_t *)(SDRAM_BASE + 0x8);
|
||||
if (value != 0x87654321) {
|
||||
status = 1;
|
||||
}
|
||||
value = *(volatile uint32_t *)(SDRAM_BASE + 0xC);
|
||||
if (value != 0xAAAA5555) {
|
||||
status = 1;
|
||||
}
|
||||
value = *(volatile uint32_t *)(SDRAM_BASE + 0x10);
|
||||
if (value != 0xFF0000FF) {
|
||||
status = 1;
|
||||
}
|
||||
|
||||
for (i = 0; i < TEST_SIZE; i++) //16777216 total size (2^26)/4
|
||||
{
|
||||
mem_add = SDRAM_BASE + (i*4);
|
||||
*(volatile uint32_t *)mem_add = (i);
|
||||
}
|
||||
for (i = 0; i < TEST_SIZE; i++) { //16777216 total size (2^26)/4
|
||||
mem_add = SDRAM_BASE + (i*4);
|
||||
*(volatile uint32_t *)mem_add = (i);
|
||||
}
|
||||
|
||||
for (i = 0; i < TEST_SIZE ; i++)
|
||||
{
|
||||
mem_add = SDRAM_BASE + (4 * i);
|
||||
value = *(volatile uint32_t *)(mem_add);
|
||||
if ((value != (i)))
|
||||
{
|
||||
status = 1;
|
||||
}
|
||||
}
|
||||
for (i = 0; i < TEST_SIZE ; i++) {
|
||||
mem_add = SDRAM_BASE + (4 * i);
|
||||
value = *(volatile uint32_t *)(mem_add);
|
||||
if ((value != (i))) {
|
||||
status = 1;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Test SDRAM */
|
||||
void sdram_test (void) {
|
||||
uint32_t count = 0x64U;
|
||||
|
||||
if (sdram_test_helper()) {
|
||||
while (count) {
|
||||
XMC_GPIO_ToggleOutput(LED1); /* test fail */
|
||||
sdram_delay(1000000);
|
||||
--count;
|
||||
}
|
||||
} else {
|
||||
XMC_GPIO_SetOutputHigh(LED1); /* test ok (Turn off Pin 5.2) */
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Function to Initialize EBU Registers for Configuration
|
||||
*/
|
||||
void EBU_Init(void)
|
||||
{
|
||||
XMC_EBU_Init(ebumodule, &ebuobj);
|
||||
void EBU_Init (void) {
|
||||
XMC_EBU_Init(ebumodule, &ebuobj);
|
||||
|
||||
XMC_EBU_ConfigureRegion(ebumodule, &ebureadwriteconfig );
|
||||
XMC_EBU_ConfigureRegion(ebumodule, &ebureadwriteconfig_1 );
|
||||
XMC_EBU_ConfigureRegion(ebumodule, &ebureadwriteconfig_2 );
|
||||
XMC_EBU_ConfigureRegion(ebumodule, &ebureadwriteconfig_3 );
|
||||
XMC_EBU_ConfigureRegion(ebumodule, &ebureadwriteconfig);
|
||||
XMC_EBU_ConfigureRegion(ebumodule, &ebureadwriteconfig_1);
|
||||
XMC_EBU_ConfigureRegion(ebumodule, &ebureadwriteconfig_2);
|
||||
XMC_EBU_ConfigureRegion(ebumodule, &ebureadwriteconfig_3);
|
||||
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE,0U);
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE,0U);
|
||||
XMC_EBU_ConfigureSdram(ebumodule, &ebusdramcontrol);
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE,0U);
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE,0U);
|
||||
XMC_EBU_ConfigureSdram(ebumodule, &ebusdramcontrol);
|
||||
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE,1U);
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE,1U);
|
||||
XMC_EBU_ConfigureSdram(ebumodule, &ebusdramcontrol);
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE,1U);
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE,1U);
|
||||
XMC_EBU_ConfigureSdram(ebumodule, &ebusdramcontrol);
|
||||
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE,2U);
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE,2U);
|
||||
XMC_EBU_ConfigureSdram(ebumodule, &ebusdramcontrol);
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE,2U);
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE,2U);
|
||||
XMC_EBU_ConfigureSdram(ebumodule, &ebusdramcontrol);
|
||||
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE,3U);
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE,3U);
|
||||
XMC_EBU_ConfigureSdram(ebumodule, &ebusdramcontrol);
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE,3U);
|
||||
XMC_EBU_AddressSelectEnable(ebumodule,XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE,3U);
|
||||
XMC_EBU_ConfigureSdram(ebumodule, &ebusdramcontrol);
|
||||
}
|
||||
|
||||
/* EBU Port Configuraitons */
|
||||
void EBU_MUX_Init(void)
|
||||
{
|
||||
XMC_GPIO_CONFIG_t config;
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE;
|
||||
/* EBU port configuration */
|
||||
void EBU_MUX_Init (void) {
|
||||
XMC_GPIO_CONFIG_t config;
|
||||
config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
|
||||
config.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;
|
||||
config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE;
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ0, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ0, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ0, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ0, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ1, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ1, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ2, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ2, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ1, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ1, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ3, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ3, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ2, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ2, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ4, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ4, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ3, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ3, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ5, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ5, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ4, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ4, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ6, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ6, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ5, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ5, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ7, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ7, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ6, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ6, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ8, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ8, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ7, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ7, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ9, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ9, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ8, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ8, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ10, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ10, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ9, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ9, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ11, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ11, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ10, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ10, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ12, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ12, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ11, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ11, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ13, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ13, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ12, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ12, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ14, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ14, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ13, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ13, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_DQ15, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ15, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ14, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ14, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_A0, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A0, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A1, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A1, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_DQ15, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_DQ15, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_A2, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A2, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A0, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A0, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_A3, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A3, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A1, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A1, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_A4, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A4, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A2, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A2, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_A5, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A5, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A3, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A3, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_A6, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A6, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A7, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A7, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A4, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A4, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_A8, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A8, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A5, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A5, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_A9, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A9, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A6, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A6, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_A10, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A10, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A7, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A7, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_A11, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A11, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A8, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A8, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_BA0, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_BA0, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A9, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A9, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_BA1, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_BA1, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A10, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A10, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_UDQM, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_UDQM, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_A11, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_A11, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_LDQM, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_LDQM, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_BA0, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_BA0, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_bWE, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_bWE, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_BA1, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_BA1, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_bCS, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_bCS, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_UDQM, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_UDQM, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_CKE, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_CKE, XMC_GPIO_HWCTRL_PERIPHERAL1);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_LDQM, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_LDQM, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_bRAS, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_bRAS, XMC_GPIO_HWCTRL_PERIPHERAL1);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_bWE, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_bWE, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
XMC_GPIO_Init(SDRAM_bCAS, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_bCAS, XMC_GPIO_HWCTRL_PERIPHERAL1);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_bCS, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_bCS, XMC_GPIO_HWCTRL_PERIPHERAL2);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_CKE, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_CKE, XMC_GPIO_HWCTRL_PERIPHERAL1);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_bRAS, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_bRAS, XMC_GPIO_HWCTRL_PERIPHERAL1);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_bCAS, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_bCAS, XMC_GPIO_HWCTRL_PERIPHERAL1);
|
||||
|
||||
XMC_GPIO_Init(SDRAM_CLK, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_CLK, XMC_GPIO_HWCTRL_PERIPHERAL1);
|
||||
XMC_GPIO_Init(SDRAM_CLK, &config);
|
||||
XMC_GPIO_SetHardwareControl(SDRAM_CLK, XMC_GPIO_HWCTRL_PERIPHERAL1);
|
||||
}
|
||||
|
||||
void ebu_main (void) {
|
||||
/* EBU Clock is divided by 2 - To program the divider connecting a parent and its child clock node*/
|
||||
XMC_SCU_CLOCK_SetEbuClockDivider(2U);
|
||||
|
||||
/**
|
||||
*
|
||||
* This example demonstrates proper initialization of external SDRAM and R/W Operation.
|
||||
* Test Result:
|
||||
* SDRAM Test passed: LED will be switch off
|
||||
* SDRAM Test failed: LED is flashing
|
||||
*/
|
||||
void ebu_init(void)
|
||||
{
|
||||
uint32_t count = 0x64U;
|
||||
/* Enable EBU Clock */
|
||||
XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_EBU);
|
||||
|
||||
/* EBU Clock is divided by 2 - To program the divider connecting a parent and its child clock node*/
|
||||
XMC_SCU_CLOCK_SetEbuClockDivider(2U);
|
||||
EBU_MUX_Init();
|
||||
EBU_Init();
|
||||
|
||||
/* Enable EBU Clock */
|
||||
XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_EBU);
|
||||
XMC_GPIO_SetMode(LED1, XMC_GPIO_MODE_OUTPUT_PUSH_PULL);
|
||||
|
||||
EBU_MUX_Init();
|
||||
EBU_Init();
|
||||
|
||||
XMC_GPIO_SetMode(LED1, XMC_GPIO_MODE_OUTPUT_PUSH_PULL);
|
||||
|
||||
if (SDRAM_Test())
|
||||
{
|
||||
while (count)
|
||||
{
|
||||
XMC_GPIO_ToggleOutput(LED1); /* test fail */
|
||||
DELAY(1000000);
|
||||
--count;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
XMC_GPIO_SetOutputHigh(LED1); /* test ok (Turn off Pin 5.2) */
|
||||
}
|
||||
|
||||
//while(1U)
|
||||
//{
|
||||
//}
|
||||
sdram_test();
|
||||
}
|
||||
|
||||
@ -41,6 +41,8 @@ uint8_t recv_byte;
|
||||
// ****************************************************************************
|
||||
// Platform initialization
|
||||
|
||||
extern void ebu_main (void);
|
||||
|
||||
int platform_init()
|
||||
{
|
||||
DAVE_Init();
|
||||
@ -53,6 +55,11 @@ int platform_init()
|
||||
SysTick_Config((uint32_t)(SYSTM001_SYSTICK_INTERVAL * SYSTM001_SYS_CORE_CLOCK * 1000U));
|
||||
NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),10,0));
|
||||
|
||||
/* Initialize the EBU if we're using the XMC45 SDRAM kit */
|
||||
#if defined ( XMC4500_E144x1024 )
|
||||
ebu_main();
|
||||
#endif
|
||||
|
||||
return PLATFORM_OK;
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user