mirror of
https://github.com/elua/elua.git
synced 2025-01-25 01:02:54 +08:00
added the PWM module, so far supported only on LM3S
This commit is contained in:
parent
b38e258040
commit
3ce5487a73
@ -71,7 +71,7 @@ newlib_files = " src/newlib/devman.c src/newlib/stubs.c src/newlib/genstd.c"
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# Lua module files
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module_files = """ src/modules/pio.c src/modules/spi.c src/modules/tmr.c src/modules/pd.c src/modules/uart.c
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src/modules/term.c """
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src/modules/term.c src/modules/pwm.c"""
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# Optimizer flags (speed or size)
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#opt = "-O3"
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@ -141,6 +141,26 @@ void platform_timer_delay( unsigned id, u32 delay_us );
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u32 platform_timer_op( unsigned id, int op, u32 data );
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u32 platform_timer_get_diff_us( unsigned id, timer_data_type end, timer_data_type start );
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// *****************************************************************************
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// PWM subsection
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// There are 16 "virtual" PWM channels (PWM0...PWM15)
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#define PLATFORM_PWM_TOTAL 16
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// PWM operations
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enum
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{
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PLATFORM_PWM_OP_START,
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PLATFORM_PWM_OP_STOP,
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PLATFORM_PWM_OP_SET_CLOCK,
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PLATFORM_PWM_OP_GET_CLOCK
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};
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// The platform PWM functions
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int platform_pwm_exists( unsigned id );
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u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty );
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u32 platform_pwm_op( unsigned id, int op, u32 data );
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// *****************************************************************************
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// Platform data subsection
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// Contains functions for platform identification
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@ -24,6 +24,9 @@ LUALIB_API int ( luaopen_uart )( lua_State* L );
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#define AUXLIB_TERM "term"
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LUALIB_API int ( luaopen_term )( lua_State* L );
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#define AUXLIB_PWM "pwm"
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LUALIB_API int ( luaopen_pwm )( lua_State* L );
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#ifdef ELUA_MOD_CHECK_PARS
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// Helper macros
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103
src/modules/pwm.c
Normal file
103
src/modules/pwm.c
Normal file
@ -0,0 +1,103 @@
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// Module for interfacing with PWM
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#include "lua.h"
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#include "lualib.h"
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#include "lauxlib.h"
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#include "platform.h"
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#include "auxmods.h"
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// Lua: realfrequency = setup( id, frequency, duty )
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static int pwm_setup( lua_State* L )
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{
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u32 freq;
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unsigned duty, id;
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MOD_CHECK_MIN_ARGS( 3 );
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id = luaL_checkinteger( L, 1 );
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freq = luaL_checkinteger( L, 2 );
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duty = luaL_checkinteger( L, 3 );
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if( duty > 100 )
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duty = 100;
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freq = platform_pwm_setup( id, freq, duty );
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lua_pushinteger( L, freq );
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return 1;
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}
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// Lua: start( id )
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static int pwm_start( lua_State* L )
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{
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unsigned id;
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MOD_CHECK_MIN_ARGS( 1 );
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id = luaL_checkinteger( L, 1 );
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platform_pwm_op( id, PLATFORM_PWM_OP_START, 0 );
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return 0;
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}
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// Lua: stop( id )
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static int pwm_stop( lua_State* L )
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{
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unsigned id;
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MOD_CHECK_MIN_ARGS( 1 );
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id = luaL_checkinteger( L, 1 );
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platform_pwm_op( id, PLATFORM_PWM_OP_STOP, 0 );
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return 0;
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}
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// Lua: realclock = setclock( id, clock )
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static int pwm_setclock( lua_State* L )
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{
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unsigned id;
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u32 clk;
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MOD_CHECK_MIN_ARGS( 2 );
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id = luaL_checkinteger( L, 1 );
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clk = luaL_checkinteger( L, 2 );
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clk = platform_pwm_op( id, PLATFORM_PWM_OP_SET_CLOCK, clk );
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lua_pushinteger( L, clk );
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return 1;
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}
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// Lua: clock = getclock( id )
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static int pwm_getclock( lua_State* L )
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{
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unsigned id;
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u32 clk;
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MOD_CHECK_MIN_ARGS( 1 );
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id = luaL_checkinteger( L, 1 );
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clk = platform_pwm_op( id, PLATFORM_PWM_OP_GET_CLOCK, 0 );
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lua_pushinteger( L, clk );
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return 1;
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}
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// Module function map
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static const luaL_reg pwm_map[] =
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{
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{ "setup", pwm_setup },
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{ "start", pwm_start },
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{ "stop", pwm_stop },
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{ "setclock", pwm_setclock },
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{ "getclock", pwm_getclock },
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{ NULL, NULL }
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};
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LUALIB_API int luaopen_pwm( lua_State *L )
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{
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unsigned id;
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char name[ 10 ];
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luaL_register( L, AUXLIB_PWM, pwm_map );
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// Add all PWM interfaces to our module
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for( id = 0; id < PLATFORM_PWM_TOTAL; id ++ )
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if( platform_pwm_exists( id ) )
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{
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sprintf( name, "PWM%d", id );
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lua_pushnumber( L, id );
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lua_setfield( L, -2, name );
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}
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return 1;
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}
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@ -1,6 +1,6 @@
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# Configuration file for the LM3S microcontroller
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specific_files = "startup_gcc.c platform.c usart.c sysctl.c gpio.c ssi.c timer.c"
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specific_files = "startup_gcc.c platform.c usart.c sysctl.c gpio.c ssi.c timer.c pwm.c"
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ldscript = "lm3s.ld"
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# Prepend with path
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src/platform/lm3s/hw_pwm.h
Normal file
677
src/platform/lm3s/hw_pwm.h
Normal file
@ -0,0 +1,677 @@
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//*****************************************************************************
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//
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// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
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//
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// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
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//
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. You may not combine
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// this software with "viral" open-source software in order to form a larger
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// program. Any use in violation of the foregoing restrictions may subject
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// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 2752 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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#ifndef __HW_PWM_H__
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#define __HW_PWM_H__
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//*****************************************************************************
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//
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// The following are defines for the PWM Module Register offsets.
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//
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//*****************************************************************************
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#define PWM_O_CTL 0x00000000 // PWM Master Control register
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#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register
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#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register
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#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register
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#define PWM_O_FAULT 0x00000010 // PWM Output Fault register
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#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register
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#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.
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#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register
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#define PWM_O_STATUS 0x00000020 // PWM Status register
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#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value
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#define PWM_O_0_CTL 0x00000040 // PWM0 Control
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#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger
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// Enable
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#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status
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#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear
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#define PWM_O_0_LOAD 0x00000050 // PWM0 Load
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#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter
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#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A
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#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B
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#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control
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#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control
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#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control
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#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay
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#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band
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// Falling-Edge-Delay
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#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0
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#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period
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#define PWM_O_1_CTL 0x00000080 // PWM1 Control
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#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt Enable
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#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status
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#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear
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#define PWM_O_1_LOAD 0x00000090 // PWM1 Load
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#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter
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#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A
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#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B
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#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control
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#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control
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#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control
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#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay
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#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band
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// Falling-Edge-Delay
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#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0
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#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period
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#define PWM_O_2_CTL 0x000000C0 // PWM2 Control
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#define PWM_O_2_INTEN 0x000000C4 // PWM2 InterruptEnable
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#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status
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#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear
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#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load
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#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter
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#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A
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#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B
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#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control
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#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control
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#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control
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#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay
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#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band
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// Falling-Edge-Delay
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#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0
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#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period
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#define PWM_O_3_CTL 0x00000100 // PWM3 Control
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#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger
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// Enable
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#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status
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#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear
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#define PWM_O_3_LOAD 0x00000110 // PWM3 Load
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#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter
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#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A
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#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B
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#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control
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#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control
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#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control
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#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay
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#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band
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// Falling-Edge-Delay
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#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0
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#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period
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#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense
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#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0
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#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense
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#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0
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#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense
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#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0
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#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense
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#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PWM Master Control
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// register.
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//
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//*****************************************************************************
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#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3.
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#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2.
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#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1.
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#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PWM Time Base Sync
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// register.
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//
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//*****************************************************************************
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#define PWM_SYNC_SYNC3 0x00000008 // Reset generator 3 counter
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#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter
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#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter
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#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PWM Output Enable
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// register.
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//
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//*****************************************************************************
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#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 pin enable
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#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 pin enable
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#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable
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#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable
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#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable
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#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable
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#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable
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#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PWM Inversion register.
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//
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//*****************************************************************************
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#define PWM_INVERT_PWM7INV 0x00000080 // PWM7 pin invert
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#define PWM_INVERT_PWM6INV 0x00000040 // PWM6 pin invert
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#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert
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#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert
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#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert
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#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert
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#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert
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#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PWM Fault register.
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//
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//*****************************************************************************
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#define PWM_FAULT_FAULT7 0x00000080 // PWM7 pin fault
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#define PWM_FAULT_FAULT6 0x00000040 // PWM6 pin fault
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#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault
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#define PWM_FAULT_FAULT4 0x00000010 // PWM4 pin fault
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#define PWM_FAULT_FAULT3 0x00000008 // PWM3 pin fault
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#define PWM_FAULT_FAULT2 0x00000004 // PWM2 pin fault
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#define PWM_FAULT_FAULT1 0x00000002 // PWM1 pin fault
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#define PWM_FAULT_FAULT0 0x00000001 // PWM0 pin fault
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PWM Status register.
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//
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//*****************************************************************************
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#define PWM_STATUS_FAULT3 0x00000008 // Fault3 Interrupt Status.
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#define PWM_STATUS_FAULT2 0x00000004 // Fault2 Interrupt Status.
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#define PWM_STATUS_FAULT1 0x00000002 // Fault1 Interrupt Status.
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#define PWM_STATUS_FAULT0 0x00000001 // Fault0 Interrupt Status.
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//*****************************************************************************
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//
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// The following are defines for the PWM Generator standard offsets.
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//
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//*****************************************************************************
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#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
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#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
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#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
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#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
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#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
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#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
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#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
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#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
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#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
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#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
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#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
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#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
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#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
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#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition
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#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension
|
||||
#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
|
||||
#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
|
||||
#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
|
||||
#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the PWM_X Control Register bit definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input.
|
||||
#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum fault period enabled
|
||||
#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source.
|
||||
#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
|
||||
// the PWMnDBFALL register.
|
||||
#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate
|
||||
#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
|
||||
#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
|
||||
#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode.
|
||||
#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate
|
||||
#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
|
||||
#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
|
||||
#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode.
|
||||
#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate
|
||||
#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
|
||||
#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
|
||||
#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode.
|
||||
#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate
|
||||
#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
|
||||
#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
|
||||
#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode.
|
||||
#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate
|
||||
#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
|
||||
#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
|
||||
#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg
|
||||
#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg
|
||||
#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg
|
||||
#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode
|
||||
#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down
|
||||
#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the PWM Generator extended offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense
|
||||
#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status
|
||||
#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base
|
||||
#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base
|
||||
#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base
|
||||
#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the PWM_X Interrupt/Trigger Enable Register
|
||||
// bit definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D
|
||||
#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U
|
||||
#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D
|
||||
#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U
|
||||
#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD
|
||||
#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0
|
||||
#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D
|
||||
#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U
|
||||
#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D
|
||||
#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U
|
||||
#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD
|
||||
#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the PWM_X Raw Interrupt Status Register bit
|
||||
// definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int
|
||||
#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int
|
||||
#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int
|
||||
#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int
|
||||
#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int
|
||||
#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_INTEN register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3.
|
||||
#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2.
|
||||
#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1.
|
||||
#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable.
|
||||
#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0.
|
||||
#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable.
|
||||
#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable.
|
||||
#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable.
|
||||
#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3.
|
||||
#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2.
|
||||
#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1.
|
||||
#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0.
|
||||
#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted.
|
||||
#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted.
|
||||
#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted.
|
||||
#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted.
|
||||
#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_ISC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted.
|
||||
#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted.
|
||||
#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted.
|
||||
#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted.
|
||||
#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted.
|
||||
#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status.
|
||||
#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status.
|
||||
#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status.
|
||||
#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_ISC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt.
|
||||
#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt.
|
||||
#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt.
|
||||
#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt.
|
||||
#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt.
|
||||
#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_LOAD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value.
|
||||
#define PWM_X_LOAD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_COUNT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_COUNT_M 0x0000FFFF // Counter Value.
|
||||
#define PWM_X_COUNT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_CMPA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value.
|
||||
#define PWM_X_CMPA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_CMPB register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value.
|
||||
#define PWM_X_CMPB_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_GENA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
|
||||
#define PWM_X_GENA_ACTCMPBD_NONE \
|
||||
0x00000000 // Do nothing.
|
||||
#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal.
|
||||
#define PWM_X_GENA_ACTCMPBD_ZERO \
|
||||
0x00000800 // Set the output signal to 0.
|
||||
#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
|
||||
#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
|
||||
#define PWM_X_GENA_ACTCMPBU_NONE \
|
||||
0x00000000 // Do nothing.
|
||||
#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal.
|
||||
#define PWM_X_GENA_ACTCMPBU_ZERO \
|
||||
0x00000200 // Set the output signal to 0.
|
||||
#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
|
||||
#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
|
||||
#define PWM_X_GENA_ACTCMPAD_NONE \
|
||||
0x00000000 // Do nothing.
|
||||
#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal.
|
||||
#define PWM_X_GENA_ACTCMPAD_ZERO \
|
||||
0x00000080 // Set the output signal to 0.
|
||||
#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
|
||||
#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
|
||||
#define PWM_X_GENA_ACTCMPAU_NONE \
|
||||
0x00000000 // Do nothing.
|
||||
#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal.
|
||||
#define PWM_X_GENA_ACTCMPAU_ZERO \
|
||||
0x00000020 // Set the output signal to 0.
|
||||
#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
|
||||
#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load.
|
||||
#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing.
|
||||
#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal.
|
||||
#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
|
||||
#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
|
||||
#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0.
|
||||
#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing.
|
||||
#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert the output signal.
|
||||
#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
|
||||
#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_GENB register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.
|
||||
#define PWM_X_GENB_ACTCMPBD_NONE \
|
||||
0x00000000 // Do nothing.
|
||||
#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal.
|
||||
#define PWM_X_GENB_ACTCMPBD_ZERO \
|
||||
0x00000800 // Set the output signal to 0.
|
||||
#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.
|
||||
#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.
|
||||
#define PWM_X_GENB_ACTCMPBU_NONE \
|
||||
0x00000000 // Do nothing.
|
||||
#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal.
|
||||
#define PWM_X_GENB_ACTCMPBU_ZERO \
|
||||
0x00000200 // Set the output signal to 0.
|
||||
#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.
|
||||
#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.
|
||||
#define PWM_X_GENB_ACTCMPAD_NONE \
|
||||
0x00000000 // Do nothing.
|
||||
#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal.
|
||||
#define PWM_X_GENB_ACTCMPAD_ZERO \
|
||||
0x00000080 // Set the output signal to 0.
|
||||
#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.
|
||||
#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.
|
||||
#define PWM_X_GENB_ACTCMPAU_NONE \
|
||||
0x00000000 // Do nothing.
|
||||
#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal.
|
||||
#define PWM_X_GENB_ACTCMPAU_ZERO \
|
||||
0x00000020 // Set the output signal to 0.
|
||||
#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.
|
||||
#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load.
|
||||
#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing.
|
||||
#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal.
|
||||
#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.
|
||||
#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.
|
||||
#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0.
|
||||
#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing.
|
||||
#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert the output signal.
|
||||
#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.
|
||||
#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay.
|
||||
#define PWM_X_DBRISE_DELAY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay.
|
||||
#define PWM_X_DBFALL_DELAY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value.
|
||||
#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value.
|
||||
#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value.
|
||||
#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value.
|
||||
#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value.
|
||||
#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value.
|
||||
#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value.
|
||||
#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period.
|
||||
#define PWM_X_MINFLTPER_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense.
|
||||
#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense.
|
||||
#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense.
|
||||
#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3.
|
||||
#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2.
|
||||
#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1.
|
||||
#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3.
|
||||
#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2.
|
||||
#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1.
|
||||
#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the PWM Master
|
||||
// Control register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
|
||||
#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
|
||||
#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the PWM Interrupt Register bit
|
||||
// definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the PWM Status
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_STATUS_FAULT 0x00000001 // Fault status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the PWM_X Interrupt Status Register
|
||||
// bit definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
|
||||
#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
|
||||
#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
|
||||
#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
|
||||
#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
|
||||
#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the PWM_X Generator A/B Control
|
||||
// Register bit definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
|
||||
#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
|
||||
#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
|
||||
#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
|
||||
#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
|
||||
#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the PWM_X Generator A/B Control
|
||||
// Register action definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one
|
||||
#define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero
|
||||
#define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal
|
||||
#define PWM_GEN_ACT_NONE 0x00000000 // Do nothing
|
||||
#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
|
||||
#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
|
||||
#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
|
||||
#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
|
||||
#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
|
||||
#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the PWM_X Dead Band Control
|
||||
// Register bit definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the PWM Register reset values.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
|
||||
#define PWM_RV_STATUS 0x00000000 // Status
|
||||
#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
|
||||
#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
|
||||
#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
|
||||
// generator block
|
||||
#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
|
||||
#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
|
||||
// count
|
||||
#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
|
||||
#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
|
||||
#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
|
||||
#define PWM_RV_CTL 0x00000000 // Master control of the PWM module
|
||||
#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
|
||||
// output pins
|
||||
#define PWM_RV_RIS 0x00000000 // Raw interrupt status
|
||||
#define PWM_RV_X_CMPA 0x00000000 // The comparator A value
|
||||
#define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output
|
||||
// pins
|
||||
#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
|
||||
// count
|
||||
#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output
|
||||
// pins
|
||||
#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
|
||||
#define PWM_RV_X_CMPB 0x00000000 // The comparator B value
|
||||
#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
|
||||
#define PWM_RV_INTEN 0x00000000 // Interrupt enable
|
||||
#define PWM_RV_X_COUNT 0x00000000 // The current counter value
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_PWM_H__
|
@ -14,6 +14,7 @@
|
||||
#include "hw_ints.h"
|
||||
#include "hw_memmap.h"
|
||||
#include "hw_types.h"
|
||||
#include "hw_pwm.h"
|
||||
#include "debug.h"
|
||||
#include "gpio.h"
|
||||
#include "interrupt.h"
|
||||
@ -21,6 +22,7 @@
|
||||
#include "usart.h"
|
||||
#include "ssi.h"
|
||||
#include "timer.h"
|
||||
#include "pwm.h"
|
||||
|
||||
// *****************************************************************************
|
||||
// std function
|
||||
@ -39,10 +41,11 @@ static int uart_recv()
|
||||
// Platform initialization
|
||||
|
||||
// forward
|
||||
void timers_init();
|
||||
void uarts_init();
|
||||
void spis_init();
|
||||
void pios_init();
|
||||
static void timers_init();
|
||||
static void uarts_init();
|
||||
static void spis_init();
|
||||
static void pios_init();
|
||||
static void pwms_init();
|
||||
|
||||
int platform_init()
|
||||
{
|
||||
@ -59,7 +62,10 @@ int platform_init()
|
||||
uarts_init();
|
||||
|
||||
// Setup timers
|
||||
timers_init();
|
||||
timers_init();
|
||||
|
||||
// Setup PWMs
|
||||
pwms_init();
|
||||
|
||||
// Set the send/recv functions
|
||||
std_set_send_func( uart_send );
|
||||
@ -91,8 +97,7 @@ static const u8 pio_port_pins[] = { 8, 8, 8, 8,
|
||||
4, 4, 2, 0 };
|
||||
#endif
|
||||
|
||||
|
||||
void pios_init()
|
||||
static void pios_init()
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
@ -183,7 +188,7 @@ static const u8 spi_gpio_pins[] = { GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_
|
||||
// SSIxClk SSIxFss SSIxRx SSIxTx
|
||||
static const u8 spi_gpio_clk_pin[] = { GPIO_PIN_2, GPIO_PIN_0 };
|
||||
|
||||
void spis_init()
|
||||
static void spis_init()
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
@ -250,7 +255,7 @@ static const u32 uart_sysctl[] = { SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYS
|
||||
static const u32 uart_gpio_base[] = { GPIO_PORTA_BASE, GPIO_PORTD_BASE, GPIO_PORTG_BASE };
|
||||
static const u8 uart_gpio_pins[] = { GPIO_PIN_0 | GPIO_PIN_1, GPIO_PIN_2 | GPIO_PIN_3, GPIO_PIN_0 | GPIO_PIN_1 };
|
||||
|
||||
void uarts_init()
|
||||
static void uarts_init()
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
@ -355,7 +360,7 @@ int platform_uart_recv( unsigned id, unsigned timer_id, int timeout )
|
||||
static const u32 timer_base[] = { TIMER0_BASE, TIMER1_BASE, TIMER2_BASE, TIMER3_BASE };
|
||||
static const u32 timer_sysctl[] = { SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3 };
|
||||
|
||||
void timers_init()
|
||||
static void timers_init()
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
@ -430,6 +435,106 @@ u32 platform_timer_get_diff_us( unsigned id, timer_data_type end, timer_data_typ
|
||||
return ( ( u64 )( start - end ) * 1000000 ) / SysCtlClockGet();
|
||||
}
|
||||
|
||||
// ****************************************************************************
|
||||
// PWMs
|
||||
|
||||
#define PLATFORM_NUM_PWMS 6
|
||||
#define PABS( x ) ( ( x ) < 0 ? -( x ) : ( x ) )
|
||||
|
||||
// SYSCTL div data and actual div factors
|
||||
const static u32 pwm_div_ctl[] = { SYSCTL_PWMDIV_1, SYSCTL_PWMDIV_2, SYSCTL_PWMDIV_4, SYSCTL_PWMDIV_8, SYSCTL_PWMDIV_16, SYSCTL_PWMDIV_32, SYSCTL_PWMDIV_64 };
|
||||
const static u8 pwm_div_data[] = { 1, 2, 4, 8, 16, 32, 64 };
|
||||
// Port/pin information for all channels
|
||||
const static u32 pwm_ports[] = { GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE };
|
||||
const static u8 pwm_pins[] = { GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1 };
|
||||
// PWM generators
|
||||
const static u16 pwm_gens[] = { PWM_GEN_0, PWM_GEN_1, PWM_GEN_2 };
|
||||
// PWM outputs
|
||||
const static u16 pwm_outs[] = { PWM_OUT_0, PWM_OUT_1, PWM_OUT_2, PWM_OUT_3, PWM_OUT_4, PWM_OUT_5 };
|
||||
|
||||
static void pwms_init()
|
||||
{
|
||||
SysCtlPeripheralEnable( SYSCTL_PERIPH_PWM );
|
||||
SysCtlPWMClockSet( SYSCTL_PWMDIV_1 );
|
||||
}
|
||||
|
||||
// Helper function: return the PWM clock
|
||||
static u32 platform_pwm_get_clock()
|
||||
{
|
||||
unsigned i;
|
||||
u32 clk;
|
||||
|
||||
clk = SysCtlPWMClockGet();
|
||||
for( i = 0; i < sizeof( pwm_div_ctl ) / sizeof( u32 ); i ++ )
|
||||
if( clk == pwm_div_ctl[ i ] )
|
||||
break;
|
||||
return SysCtlClockGet() / pwm_div_data[ i ];
|
||||
}
|
||||
|
||||
// Helper function: set the PWM clock
|
||||
static u32 platform_pwm_set_clock( u32 clock )
|
||||
{
|
||||
unsigned i, min_i;
|
||||
u32 sysclk;
|
||||
|
||||
sysclk = SysCtlClockGet();
|
||||
for( i = min_i = 0; i < sizeof( pwm_div_data ) / sizeof( u8 ); i ++ )
|
||||
if( PABS( clock - sysclk / pwm_div_data[ i ] ) < PABS( clock - sysclk / pwm_div_data[ min_i ] ) )
|
||||
min_i = i;
|
||||
SysCtlPWMClockSet( pwm_div_ctl[ min_i ] );
|
||||
return sysclk / pwm_div_data[ min_i ];
|
||||
}
|
||||
|
||||
int platform_pwm_exists( unsigned id )
|
||||
{
|
||||
return id < PLATFORM_NUM_PWMS;
|
||||
}
|
||||
|
||||
u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
|
||||
{
|
||||
u32 pwmclk = platform_pwm_get_clock();
|
||||
u32 period;
|
||||
|
||||
// Set pin as PWM
|
||||
GPIOPinTypePWM( pwm_ports[ id ], pwm_pins[ id ] );
|
||||
// Compute period
|
||||
period = pwmclk / frequency;
|
||||
// Set the period
|
||||
PWMGenConfigure( PWM_BASE, pwm_gens[ id >> 1 ], PWM_GEN_MODE_UP_DOWN | PWM_GEN_MODE_NO_SYNC );
|
||||
PWMGenPeriodSet( PWM_BASE, pwm_gens[ id >> 1 ], period );
|
||||
// Set duty cycle
|
||||
PWMPulseWidthSet( PWM_BASE, pwm_outs[ id ], ( period * duty ) / 100 );
|
||||
// Return actual frequency
|
||||
return pwmclk / period;
|
||||
}
|
||||
|
||||
u32 platform_pwm_op( unsigned id, int op, u32 data )
|
||||
{
|
||||
u32 res = 0;
|
||||
|
||||
switch( op )
|
||||
{
|
||||
case PLATFORM_PWM_OP_SET_CLOCK:
|
||||
res = platform_pwm_set_clock( data );
|
||||
|
||||
case PLATFORM_PWM_OP_GET_CLOCK:
|
||||
res = platform_pwm_get_clock();
|
||||
break;
|
||||
|
||||
case PLATFORM_PWM_OP_START:
|
||||
PWMOutputState( PWM_BASE, 1 << id, true );
|
||||
PWMGenEnable( PWM_BASE, pwm_gens[ id >> 1 ] );
|
||||
break;
|
||||
|
||||
case PLATFORM_PWM_OP_STOP:
|
||||
PWMOutputState( PWM_BASE, 1 << id, false );
|
||||
PWMGenDisable( PWM_BASE, pwm_gens[ id >> 1 ] );
|
||||
break;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
// ****************************************************************************
|
||||
// Platform data
|
||||
|
||||
|
@ -11,6 +11,7 @@
|
||||
{ AUXLIB_TMR, luaopen_tmr },\
|
||||
{ AUXLIB_PD, luaopen_pd },\
|
||||
{ AUXLIB_UART, luaopen_uart },\
|
||||
{ AUXLIB_TERM, luaopen_term }
|
||||
{ AUXLIB_TERM, luaopen_term },\
|
||||
{ AUXLIB_PWM, luaopen_pwm }
|
||||
|
||||
#endif
|
||||
|
1676
src/platform/lm3s/pwm.c
Normal file
1676
src/platform/lm3s/pwm.c
Normal file
File diff suppressed because it is too large
Load Diff
270
src/platform/lm3s/pwm.h
Normal file
270
src/platform/lm3s/pwm.h
Normal file
@ -0,0 +1,270 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
|
||||
//
|
||||
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. You may not combine
|
||||
// this software with "viral" open-source software in order to form a larger
|
||||
// program. Any use in violation of the foregoing restrictions may subject
|
||||
// the user to criminal sanctions under applicable laws, as well as to civil
|
||||
// liability for the breach of the terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 2752 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __PWM_H__
|
||||
#define __PWM_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following defines are passed to PWMGenConfigure() as the ulConfig
|
||||
// parameter and specify the configuration of the PWM generator.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
|
||||
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
|
||||
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
|
||||
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
|
||||
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
|
||||
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
|
||||
#define PWM_GEN_MODE_FAULT_LATCHED \
|
||||
0x00040000 // Fault is latched
|
||||
#define PWM_GEN_MODE_FAULT_UNLATCHED \
|
||||
0x00000000 // Fault is not latched
|
||||
#define PWM_GEN_MODE_FAULT_MINPER \
|
||||
0x00020000 // Enable min fault period
|
||||
#define PWM_GEN_MODE_FAULT_NO_MINPER \
|
||||
0x00000000 // Disable min fault period
|
||||
#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
|
||||
#define PWM_GEN_MODE_FAULT_LEGACY \
|
||||
0x00000000 // Disable extended fault support
|
||||
#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
|
||||
// immediately
|
||||
#define PWM_GEN_MODE_DB_SYNC_LOCAL \
|
||||
0x0000A800 // Deadband updates locally
|
||||
// synchronized
|
||||
#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
|
||||
0x0000FC00 // Deadband updates globally
|
||||
// synchronized
|
||||
#define PWM_GEN_MODE_GEN_NO_SYNC \
|
||||
0x00000000 // Generator mode updates occur
|
||||
// immediately
|
||||
#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
|
||||
0x00000280 // Generator mode updates locally
|
||||
// synchronized
|
||||
#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
|
||||
0x000003C0 // Generator mode updates globally
|
||||
// synchronized
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for enabling, disabling, and clearing PWM generator interrupts and
|
||||
// triggers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
|
||||
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
|
||||
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
|
||||
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
|
||||
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
|
||||
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
|
||||
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
|
||||
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
|
||||
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
|
||||
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
|
||||
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
|
||||
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for enabling, disabling, and clearing PWM interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
|
||||
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
|
||||
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
|
||||
#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
|
||||
#ifndef DEPRECATED
|
||||
#define PWM_INT_FAULT 0x00010000 // Fault interrupt
|
||||
#endif
|
||||
#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
|
||||
#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
|
||||
#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
|
||||
#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
|
||||
#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify the generators within a module.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
|
||||
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
|
||||
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
|
||||
#define PWM_GEN_3 0x00000100 // Offset address of Gen3
|
||||
|
||||
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
|
||||
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
|
||||
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
|
||||
#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
|
||||
|
||||
#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
|
||||
#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
|
||||
#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
|
||||
#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify the outputs within a module.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
|
||||
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
|
||||
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
|
||||
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
|
||||
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
|
||||
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
|
||||
#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
|
||||
#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
|
||||
|
||||
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
|
||||
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
|
||||
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
|
||||
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
|
||||
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
|
||||
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
|
||||
#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
|
||||
#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify each of the possible fault trigger conditions in
|
||||
// PWM_FAULT_GROUP_0
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULT_GROUP_0 0
|
||||
|
||||
#define PWM_FAULT_FAULT0 0x00000001
|
||||
#define PWM_FAULT_FAULT1 0x00000002
|
||||
#define PWM_FAULT_FAULT2 0x00000004
|
||||
#define PWM_FAULT_FAULT3 0x00000008
|
||||
#define PWM_FAULT_ACMP0 0x00010000
|
||||
#define PWM_FAULT_ACMP1 0x00020000
|
||||
#define PWM_FAULT_ACMP2 0x00040000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify the sense of each of the external FAULTn signals
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULT0_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT0_SENSE_LOW 0x00000001
|
||||
#define PWM_FAULT1_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT1_SENSE_LOW 0x00000002
|
||||
#define PWM_FAULT2_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT2_SENSE_LOW 0x00000004
|
||||
#define PWM_FAULT3_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT3_SENSE_LOW 0x00000008
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulConfig);
|
||||
extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulPeriod);
|
||||
extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
|
||||
unsigned long ulGen);
|
||||
extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
|
||||
extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
|
||||
extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
|
||||
unsigned long ulWidth);
|
||||
extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
|
||||
unsigned long ulPWMOut);
|
||||
extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned short usRise, unsigned short usFall);
|
||||
extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
|
||||
extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
|
||||
extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
|
||||
extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
|
||||
tBoolean bEnable);
|
||||
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
|
||||
tBoolean bInvert);
|
||||
extern void PWMOutputFaultLevel(unsigned long ulBase,
|
||||
unsigned long ulPWMOutBits,
|
||||
tBoolean bDriveHigh);
|
||||
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
|
||||
tBoolean bFaultSuppress);
|
||||
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
|
||||
void (*pfnIntHandler)(void));
|
||||
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
|
||||
extern void PWMFaultIntRegister(unsigned long ulBase,
|
||||
void (*pfnIntHandler)(void));
|
||||
extern void PWMFaultIntUnregister(unsigned long ulBase);
|
||||
extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulIntTrig);
|
||||
extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulIntTrig);
|
||||
extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
|
||||
tBoolean bMasked);
|
||||
extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulInts);
|
||||
extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
|
||||
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
|
||||
extern void PWMFaultIntClear(unsigned long ulBase);
|
||||
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void PWMFaultIntClearExt(unsigned long ulBase,
|
||||
unsigned long ulFaultInts);
|
||||
extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulMinFaultPeriod,
|
||||
unsigned long ulFaultSenses);
|
||||
extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulGroup,
|
||||
unsigned long ulFaultTriggers);
|
||||
extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,
|
||||
unsigned long ulGen,
|
||||
unsigned long ulGroup);
|
||||
extern unsigned long PWMGenFaultStatus(unsigned long ulBase,
|
||||
unsigned long ulGen,
|
||||
unsigned long ulGroup);
|
||||
extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulGroup,
|
||||
unsigned long ulFaultTriggers);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __PWM_H__
|
Loading…
x
Reference in New Issue
Block a user