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Remove tab characters and trailing spaces from avr32 platform code

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and regularize indentation/spacing in new uip/ethernet code.
This commit is contained in:
Martin Guy 2011-06-17 19:00:05 +02:00
parent dca244112b
commit 6d9cc5eb8c
10 changed files with 101 additions and 98 deletions
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6
src/platform/avr32/MIZAR32/mizar32_conf.h
View File

@ -81,7 +81,7 @@
#define NETLINE
#endif
#if defined( BUILD_RPC )
#if defined( BUILD_RPC )
#define RPCLINE _ROM( AUXLIB_RPC, luaopen_rpc, rpc_map )
#else
#define RPCLINE
@ -128,8 +128,8 @@
#else
#define NUM_TIMER 3
#endif
#define NUM_PWM 7 // PWM7 is on GPIO50
#define NUM_ADC 8 // Though ADC3 pin is the Ethernet IRQ
#define NUM_PWM 7 // PWM7 is on GPIO50
#define NUM_ADC 8 // Though ADC3 pin is the Ethernet IRQ
#define NUM_CAN 0
// As flow control seems not to work, we use a large buffer so that people

2
src/platform/avr32/ethernet.c
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@ -789,7 +789,7 @@ __attribute__((__interrupt__)) void vMACB_ISR(void)
// Variable definitions can be made now.
volatile unsigned long ulIntStatus, ulEventStatus;
// Find the cause of the interrupt.
// Find the cause of the interrupt.
ulIntStatus = AVR32_MACB.isr;
ulEventStatus = AVR32_MACB.rsr;

111
src/platform/avr32/platform.c
View File

@ -44,8 +44,8 @@
// UIP sys tick data
// NOTE: when using virtual timers, SYSTICKHZ and VTMR_FREQ_HZ should have the
// same value, as they're served by the same timer (the systick)
#define SYSTICKHZ 4
#define SYSTICKMS (1000 / SYSTICKHZ)
#define SYSTICKHZ 4
#define SYSTICKMS (1000 / SYSTICKHZ)
#ifdef BUILD_UIP
static int eth_timer_fired;
@ -54,7 +54,7 @@ static int eth_timer_fired;
// ****************************************************************************
// Platform initialization
#ifdef BUILD_UIP
u32 platform_ethernet_setup(void);
u32 platform_ethernet_setup( void );
#endif
extern int pm_configure_clocks( pm_freq_param_t *param );
@ -88,7 +88,7 @@ __attribute__((__interrupt__)) static void tmr_int_handler()
// of incrementing the timers and taking the appropriate actions.
platform_eth_force_interrupt();
#endif
}
}
#endif
const u32 uart_base_addr[ ] = {
@ -870,8 +870,8 @@ static const gpio_map_t pwm_pins =
{ AVR32_PWM_1_PIN, AVR32_PWM_1_FUNCTION },
{ AVR32_PWM_2_PIN, AVR32_PWM_2_FUNCTION },
{ AVR32_PWM_3_PIN, AVR32_PWM_3_FUNCTION },
{ AVR32_PWM_4_1_PIN, AVR32_PWM_4_1_FUNCTION }, // PB27
{ AVR32_PWM_5_1_PIN, AVR32_PWM_5_1_FUNCTION }, // PB28
{ AVR32_PWM_4_1_PIN, AVR32_PWM_4_1_FUNCTION }, // PB27
{ AVR32_PWM_5_1_PIN, AVR32_PWM_5_1_FUNCTION }, // PB28
{ AVR32_PWM_6_PIN, AVR32_PWM_6_FUNCTION },
};
@ -1012,80 +1012,81 @@ u32 platform_pwm_op( unsigned id, int op, u32 data)
#ifdef BUILD_UIP
static const gpio_map_t MACB_GPIO_MAP =
{
{AVR32_MACB_MDC_0_PIN, AVR32_MACB_MDC_0_FUNCTION },
{AVR32_MACB_MDIO_0_PIN, AVR32_MACB_MDIO_0_FUNCTION },
{AVR32_MACB_RXD_0_PIN, AVR32_MACB_RXD_0_FUNCTION },
{AVR32_MACB_TXD_0_PIN, AVR32_MACB_TXD_0_FUNCTION },
{AVR32_MACB_RXD_1_PIN, AVR32_MACB_RXD_1_FUNCTION },
{AVR32_MACB_TXD_1_PIN, AVR32_MACB_TXD_1_FUNCTION },
{AVR32_MACB_TX_EN_0_PIN, AVR32_MACB_TX_EN_0_FUNCTION },
{AVR32_MACB_RX_ER_0_PIN, AVR32_MACB_RX_ER_0_FUNCTION },
{AVR32_MACB_RX_DV_0_PIN, AVR32_MACB_RX_DV_0_FUNCTION },
{AVR32_MACB_TX_CLK_0_PIN, AVR32_MACB_TX_CLK_0_FUNCTION}
{ AVR32_MACB_MDC_0_PIN, AVR32_MACB_MDC_0_FUNCTION },
{ AVR32_MACB_MDIO_0_PIN, AVR32_MACB_MDIO_0_FUNCTION },
{ AVR32_MACB_RXD_0_PIN, AVR32_MACB_RXD_0_FUNCTION },
{ AVR32_MACB_TXD_0_PIN, AVR32_MACB_TXD_0_FUNCTION },
{ AVR32_MACB_RXD_1_PIN, AVR32_MACB_RXD_1_FUNCTION },
{ AVR32_MACB_TXD_1_PIN, AVR32_MACB_TXD_1_FUNCTION },
{ AVR32_MACB_TX_EN_0_PIN, AVR32_MACB_TX_EN_0_FUNCTION },
{ AVR32_MACB_RX_ER_0_PIN, AVR32_MACB_RX_ER_0_FUNCTION },
{ AVR32_MACB_RX_DV_0_PIN, AVR32_MACB_RX_DV_0_FUNCTION },
{ AVR32_MACB_TX_CLK_0_PIN, AVR32_MACB_TX_CLK_0_FUNCTION },
};
u32 platform_ethernet_setup()
u32 platform_ethernet_setup()
{
static struct uip_eth_addr sTempAddr;
// Assign GPIO to MACB
gpio_enable_module(MACB_GPIO_MAP, sizeof(MACB_GPIO_MAP) / sizeof(MACB_GPIO_MAP[0]));
static struct uip_eth_addr sTempAddr = {
.addr[0] = ETHERNET_CONF_ETHADDR0;
.addr[1] = ETHERNET_CONF_ETHADDR1;
.addr[2] = ETHERNET_CONF_ETHADDR2;
.addr[3] = ETHERNET_CONF_ETHADDR3;
.addr[4] = ETHERNET_CONF_ETHADDR4;
.addr[5] = ETHERNET_CONF_ETHADDR5;
}
// initialize MACB & Phy Layers
if (xMACBInit(&AVR32_MACB) == FALSE ) {
return PLATFORM_ERR;
}
// Assign GPIO to MACB
gpio_enable_module( MACB_GPIO_MAP, sizeof(MACB_GPIO_MAP ) / sizeof( MACB_GPIO_MAP[0] ) );
sTempAddr.addr[0] = ETHERNET_CONF_ETHADDR0;
sTempAddr.addr[1] = ETHERNET_CONF_ETHADDR1;
sTempAddr.addr[2] = ETHERNET_CONF_ETHADDR2;
sTempAddr.addr[3] = ETHERNET_CONF_ETHADDR3;
sTempAddr.addr[4] = ETHERNET_CONF_ETHADDR4;
sTempAddr.addr[5] = ETHERNET_CONF_ETHADDR5;
// initialize MACB & Phy Layers
if ( xMACBInit( &AVR32_MACB ) == FALSE ) {
return PLATFORM_ERR;
}
// Initialize the eLua uIP layer
elua_uip_init( &sTempAddr );
return PLATFORM_OK;
}
// Initialize the eLua uIP layer
elua_uip_init( &sTempAddr );
return PLATFORM_OK;
}
void platform_eth_send_packet( const void* src, u32 size )
{
lMACBSend(&AVR32_MACB,src, size, TRUE);
lMACBSend( &AVR32_MACB,src, size, TRUE );
}
u32 platform_eth_get_packet_nb( void* buf, u32 maxlen )
{
u32 len;
u32 len;
/* Obtain the size of the packet. */
len = ulMACBInputLength();
/* Obtain the size of the packet. */
len = ulMACBInputLength();
if (len > maxlen) {
return 0;
}
if( len > maxlen ) {
return 0;
}
if( len ) {
/* Let the driver know we are going to read a new packet. */
vMACBRead( NULL, 0, len );
vMACBRead( buf, len, len );
}
if( len ) {
/* Let the driver know we are going to read a new packet. */
vMACBRead( NULL, 0, len );
vMACBRead( buf, len, len );
}
return len;
return len;
}
void platform_eth_force_interrupt()
{
elua_uip_mainloop();
elua_uip_mainloop();
}
u32 platform_eth_get_elapsed_time()
{
if( eth_timer_fired )
{
eth_timer_fired = 0;
return SYSTICKMS;
}
else
return 0;
if( eth_timer_fired )
{
eth_timer_fired = 0;
return SYSTICKMS;
}
else
return 0;
}
#endif

20
src/platform/avr32/pm_conf_clocks.c
View File

@ -259,16 +259,18 @@ void pm_configure_usb_clock(void)
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
#else
// Use 12MHz from OSC0 and generate 96 MHz
pm_pll_setup(&AVR32_PM, 1, // pll.
7, // mul.
1, // div.
0, // osc.
16); // lockcount.
pm_pll_setup(&AVR32_PM,
1, // pll.
7, // mul.
1, // div.
0, // osc.
16); // lockcount.
pm_pll_set_option(&AVR32_PM, 1, // pll.
1, // pll_freq: choose the range 80-180MHz.
1, // pll_div2.
0); // pll_wbwdisable.
pm_pll_set_option(&AVR32_PM,
1, // pll.
1, // pll_freq: choose the range 80-180MHz.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL1 and wait forl lock
pm_pll_enable(&AVR32_PM, 1);

14
src/platform/avr32/pwm.c
View File

@ -5,7 +5,7 @@
*/
#include "pwm.h"
#include "platform_conf.h" // for REQ_PBA_FREQ
#include "platform_conf.h" // for REQ_PBA_FREQ
/*
* The AVR32 has 7 PWM channels, each of which chooses its clock from
@ -91,7 +91,7 @@ void pwm_set_linear_divider( unsigned prea, unsigned diva )
mr.prea = prea;
mr.diva = diva;
mr.preb = 0; // Turn clock B off
mr.preb = 0; // Turn clock B off
mr.divb = 0;
AVR32_PWM.MR = mr;
}
@ -107,9 +107,9 @@ u32 pwm_get_clock_freq( void )
if (divisor == 0)
{
// This clock is turned off. A frequency of 0 should surprise them.
return 0;
return 0;
}
return REQ_PBA_FREQ / ( ( 1<<prescaler ) * divisor );
}
@ -130,7 +130,7 @@ u32 pwm_get_clock_freq( void )
* the old frequency at the new duty period or vice versa.
* Worse, you have to be careful in which order you change them, since
* duty_period > cycle_period is not allowed by the hardware.
*
*
* - To know when one value has been flushed to its register, you have to
* enable the per-channel PWM interrupt, clear its status flag and wait until
* that interrupt status flag goes high, which happens at the end of each
@ -236,8 +236,8 @@ static void pwm_channel_set_period( unsigned id, u32 period )
// Select updating of the period and write into the update register
AVR32_PWM.channel[id].CMR.cpd = AVR32_PWM_CMR_CPD_UPDATE_CPRD;
update_has_flushed &= ~(1 << id); // The update hasn't happened yet...
AVR32_PWM.channel[id].cupd = period; // Schedule the update to be performed
update_has_flushed &= ~(1 << id); // The update hasn't happened yet...
AVR32_PWM.channel[id].cupd = period; // Schedule the update to be performed
}
static void pwm_channel_set_duty_cycle( unsigned id, u32 duty )

2
src/platform/avr32/pwm.h
View File

@ -4,7 +4,7 @@
* Martin Guy <martinwguy@gmail.com>, March 2011
*/
#include "platform.h" // for u32
#include "platform.h" // for u32
// Initialize the PWM system, called at startup
void pwm_init( void );

8
src/platform/avr32/spi.c
View File

@ -117,7 +117,7 @@ int spi_initMaster(volatile avr32_spi_t *spi, const spi_master_options_t *opt, U
}
/*-----------------------------------------------------------*/
int spi_setupChipReg(volatile avr32_spi_t *spi,
unsigned char reg, const spi_options_t *options, U32 pba_hz)
unsigned char reg, const spi_options_t *options, U32 pba_hz)
{
u_avr32_spi_csr_t u_avr32_spi_csr;
@ -167,11 +167,11 @@ int spi_selectChip(volatile avr32_spi_t *spi, unsigned char chip)
spi->mr |= AVR32_SPI_MR_PCS_MASK;
if (spi->mr & AVR32_SPI_MR_PCSDEC_MASK) {
// The signal is decoded; allow up to 15 chips.
// The signal is decoded; allow up to 15 chips.
if (chip > 14) goto err;
spi->mr &= ~AVR32_SPI_MR_PCS_MASK | (chip << AVR32_SPI_MR_PCS_OFFSET);
}else {
if (chip > 3) goto err;
if (chip > 3) goto err;
spi->mr &= ~(1 << (AVR32_SPI_MR_PCS_OFFSET + chip));
}
@ -183,7 +183,7 @@ err:
int spi_unselectChip(volatile avr32_spi_t *spi, unsigned char chip)
{
while (!(spi->sr & AVR32_SPI_SR_TXEMPTY_MASK))
continue;
continue;
// Assert all lines; no peripheral is selected.
spi->mr |= AVR32_SPI_MR_PCS_MASK;

26
src/platform/avr32/spi.h
View File

@ -4,15 +4,15 @@
#include <avr32/io.h>
#ifndef AVR32_SPI0
#define AVR32_SPI0 AVR32_SPI
#define AVR32_SPI0_ADDRESS AVR32_SPI_ADDRESS
#define AVR32_SPI0 AVR32_SPI
#define AVR32_SPI0_ADDRESS AVR32_SPI_ADDRESS
#endif
typedef enum {
SPI_MODE_0 = 0,
SPI_MODE_1,
SPI_MODE_2,
SPI_MODE_3
SPI_MODE_0 = 0,
SPI_MODE_1,
SPI_MODE_2,
SPI_MODE_3
} spi_mode_t;
//! Option structure for SPI channels.
@ -37,12 +37,12 @@ typedef struct
typedef struct
{
//! Mode fault detection disable
Bool modfdis;
//! Chip select decoding
Bool pcs_decode;
//! delay before chip select (in microseconds)
unsigned int delay;
//! Mode fault detection disable
Bool modfdis;
//! Chip select decoding
Bool pcs_decode;
//! delay before chip select (in microseconds)
unsigned int delay;
} spi_master_options_t;

2
src/platform/avr32/uip-conf.h
View File

@ -34,7 +34,7 @@ typedef unsigned short uip_stats_t;
//
#define UIP_CONF_PINGADDRCONF 0
//
//
// TCP support on or off
//
#define UIP_CONF_TCP 1

8
src/platform/avr32/usart.c
View File

@ -124,14 +124,14 @@ static int usart_set_async_baudrate(volatile avr32_usart_t *usart, unsigned int
*/
unsigned int usart_get_async_baudrate(volatile avr32_usart_t *usart, unsigned long pba_hz)
{
unsigned int clock; // Master clock frequency
unsigned int clock; // Master clock frequency
unsigned int over; // divisor of 8 or 16
unsigned int cd; // clock divider (0-65535)
unsigned int fp; // fractional part of clock divider (0-7)
unsigned int divisor; // What the master clock is divided by to get
// the final baud rate
// Find
// Find
switch ((usart->mr & AVR32_USART_MR_USCLKS_MASK) >> AVR32_USART_MR_USCLKS_OFFSET)
{
case AVR32_USART_MR_USCLKS_MCK:
@ -145,7 +145,7 @@ unsigned int usart_get_async_baudrate(volatile avr32_usart_t *usart, unsigned lo
case AVR32_USART_MR_USCLKS_SCK:
// If we have an external clock, we don't know its frequency here.
default:
return 0;
return 0;
}
over = usart->mr & AVR32_USART_MR_OVER_MASK;
@ -154,7 +154,7 @@ unsigned int usart_get_async_baudrate(volatile avr32_usart_t *usart, unsigned lo
// if CD==0, no baud rate is generated.
// if CD==1, the clock divider and fractional part are bypassed.
if (cd == 0) return 0;
if (cd == 0) return 0;
if (cd == 1) fp = 0;
// Rewriting "divisor = 8 * (2 - over) * (cd + fp/8)" for integer math: