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modified AVR32 port to work with AVR32 toolchain 2.4.2, tested only under Windows, shouldn't have no issues in Linux either

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This commit is contained in:
Bogdan Marinescu 2010-02-24 19:45:50 +00:00
parent a38076bb91
commit 97160f1008
28 changed files with 10389 additions and 8992 deletions
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5
src/fatfs/ff.c
View File

@ -78,6 +78,9 @@
#include "ff.h" /* FatFs configurations and declarations */
#include "diskio.h" /* Declarations of low level disk I/O functions */
#include "platform_conf.h"
#ifdef BUILD_MMCFS
/*--------------------------------------------------------------------------
@ -3151,3 +3154,5 @@ int f_printf (
#endif /* !_FS_READONLY */
#endif /* _USE_STRFUNC */
#endif // #ifdef BUILD_MMCFS

4
src/newlib/stubs.c
View File

@ -228,11 +228,7 @@ int _link_r( struct _reent *r, const char *c1, const char *c2 )
}
#include <sys/time.h>
#ifdef FORAVR32
int _gettimeofday_r( struct _reent *r, struct timeval *tp, struct timezone *tzp )
#else
int _gettimeofday_r( struct _reent *r, struct timeval *tv, void *tz )
#endif
{
r->_errno = ENOSYS;
return -1;

148
src/platform/avr32/evk1100.h → src/platform/avr32/EVK1100/evk1100.h
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@ -1,4 +1,4 @@
/* This header file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
@ -6,7 +6,9 @@
* \brief AT32UC3A EVK1100 board header file.
*
* This file contains definitions and services related to the features of the
* EVK1100 board.
* EVK1100 board rev. B and C.
*
* To use this board, define BOARD=EVK1100.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 AT32UC3A devices can be used.
@ -17,37 +19,44 @@
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _EVK1100_H_
#define _EVK1100_H_
#ifdef EVK1100_REVA
# include "evk1100_revA.h"
#else
#include "compiler.h"
//#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
@ -83,7 +92,7 @@
//! @{
//! Part header file of used SDRAM(s).
#define SDRAM_PART_HDR "mt48lc16m16a2tg7e.h"
#define SDRAM_PART_HDR "MT48LC16M16A2TG7E/mt48lc16m16a2tg7e.h"
//! Data bus width to use the SDRAM(s) with (16 or 32 bits; always 16 bits on
//! UC3).
@ -104,35 +113,19 @@
//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x.
//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and
//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from <avr32/uc3axxxx.h>.
#ifdef EVK1100_REVA
# define USB_VBOF AVR32_USBB_USB_VBOF_0_0
#else
# define USB_VBOF AVR32_USBB_USB_VBOF_0_1
#endif
#define USB_VBOF AVR32_USBB_USB_VBOF_0_1
//! Active level of the USB_VBOF output pin.
#ifdef EVK1100_REVA
# define USB_VBOF_ACTIVE_LEVEL HIGH
#else
# define USB_VBOF_ACTIVE_LEVEL LOW
#endif
#define USB_VBOF_ACTIVE_LEVEL LOW
//! USB overcurrent detection pin.
#ifdef EVK1100_REVA
# define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PB18
#else
# define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PX33
#endif
#define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PX33
//! @}
//! GPIO connection of the MAC PHY PWR_DOWN/INT signal.
#ifdef EVK1100_REVA
# define MACB_INTERRUPT_PIN AVR32_PIN_PX12
#else
# define MACB_INTERRUPT_PIN AVR32_PIN_PA24
#endif
#define MACB_INTERRUPT_PIN AVR32_PIN_PA24
//! Number of LEDs.
@ -141,25 +134,14 @@
/*! \name GPIO Connections of LEDs
*/
//! @{
#ifdef EVK1100_REVA
# define LED0_GPIO AVR32_PIN_PX13
# define LED1_GPIO AVR32_PIN_PX14
# define LED2_GPIO AVR32_PIN_PX15
# define LED3_GPIO AVR32_PIN_PX16
# define LED4_GPIO AVR32_PIN_PB19
# define LED5_GPIO AVR32_PIN_PB20
# define LED6_GPIO AVR32_PIN_PB21
# define LED7_GPIO AVR32_PIN_PB22
#else
# define LED0_GPIO AVR32_PIN_PB27
# define LED1_GPIO AVR32_PIN_PB28
# define LED2_GPIO AVR32_PIN_PB29
# define LED3_GPIO AVR32_PIN_PB30
# define LED4_GPIO AVR32_PIN_PB19
# define LED5_GPIO AVR32_PIN_PB20
# define LED6_GPIO AVR32_PIN_PB21
# define LED7_GPIO AVR32_PIN_PB22
#endif
#define LED0_GPIO AVR32_PIN_PB27
#define LED1_GPIO AVR32_PIN_PB28
#define LED2_GPIO AVR32_PIN_PB29
#define LED3_GPIO AVR32_PIN_PB30
#define LED4_GPIO AVR32_PIN_PB19
#define LED5_GPIO AVR32_PIN_PB20
#define LED6_GPIO AVR32_PIN_PB21
#define LED7_GPIO AVR32_PIN_PB22
//! @}
/*! \name PWM Channels of LEDs
@ -191,51 +173,42 @@
/*! \name Color Identifiers of LEDs to Use with LED Functions
*/
//! @{
#ifdef EVK1100_REVA
# define LED_MONO0_GREEN LED4
# define LED_MONO1_GREEN LED5
# define LED_MONO2_GREEN LED6
# define LED_MONO3_GREEN LED7
# define LED_BI0_GREEN LED1
# define LED_BI0_RED LED0
# define LED_BI1_GREEN LED3
# define LED_BI1_RED LED2
#else
# define LED_MONO0_GREEN LED0
# define LED_MONO1_GREEN LED1
# define LED_MONO2_GREEN LED2
# define LED_MONO3_GREEN LED3
# define LED_BI0_GREEN LED5
# define LED_BI0_RED LED4
# define LED_BI1_GREEN LED7
# define LED_BI1_RED LED6
#endif
#define LED_MONO0_GREEN LED0
#define LED_MONO1_GREEN LED1
#define LED_MONO2_GREEN LED2
#define LED_MONO3_GREEN LED3
#define LED_BI0_GREEN LED5
#define LED_BI0_RED LED4
#define LED_BI1_GREEN LED7
#define LED_BI1_RED LED6
//! @}
/*! \name GPIO Connections of Push Buttons
*/
//! @{
#ifdef EVK1100_REVA
# define GPIO_PUSH_BUTTON_0 AVR32_PIN_PB28
# define GPIO_PUSH_BUTTON_1 AVR32_PIN_PB29
# define GPIO_PUSH_BUTTON_2 AVR32_PIN_PB27
#else
# define GPIO_PUSH_BUTTON_0 AVR32_PIN_PX16
# define GPIO_PUSH_BUTTON_1 AVR32_PIN_PX19
# define GPIO_PUSH_BUTTON_2 AVR32_PIN_PX22
#endif
#define GPIO_PUSH_BUTTON_0 AVR32_PIN_PX16
#define GPIO_PUSH_BUTTON_0_PRESSED 0
#define GPIO_PUSH_BUTTON_1 AVR32_PIN_PX19
#define GPIO_PUSH_BUTTON_1_PRESSED 0
#define GPIO_PUSH_BUTTON_2 AVR32_PIN_PX22
#define GPIO_PUSH_BUTTON_2_PRESSED 0
//! @}
/*! \name GPIO Connections of the Joystick
*/
//! @{
#define GPIO_JOYSTICK_PUSH AVR32_PIN_PA20
#define GPIO_JOYSTICK_LEFT AVR32_PIN_PA25
#define GPIO_JOYSTICK_RIGHT AVR32_PIN_PA28
#define GPIO_JOYSTICK_UP AVR32_PIN_PA26
#define GPIO_JOYSTICK_DOWN AVR32_PIN_PA27
#define GPIO_JOYSTICK_PUSH AVR32_PIN_PA20
#define GPIO_JOYSTICK_PUSH_PRESSED 0
#define GPIO_JOYSTICK_LEFT AVR32_PIN_PA25
#define GPIO_JOYSTICK_LEFT_PRESSED 0
#define GPIO_JOYSTICK_RIGHT AVR32_PIN_PA28
#define GPIO_JOYSTICK_RIGHT_PRESSED 0
#define GPIO_JOYSTICK_UP AVR32_PIN_PA26
#define GPIO_JOYSTICK_UP_PRESSED 0
#define GPIO_JOYSTICK_DOWN AVR32_PIN_PA27
#define GPIO_JOYSTICK_DOWN_PRESSED 0
//! @}
@ -295,6 +268,7 @@
*/
//! @{
#define AT45DBX_SPI (&AVR32_SPI1)
#define AT45DBX_SPI_NPCS 0
#define AT45DBX_SPI_SCK_PIN AVR32_SPI1_SCK_0_0_PIN
#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_0_FUNCTION
#define AT45DBX_SPI_MISO_PIN AVR32_SPI1_MISO_0_0_PIN
@ -351,4 +325,6 @@
//! @}
#endif // !EVK1100_REVA
#endif // _EVK1100_H_

324
src/platform/avr32/EVK1100/evk1100_revA.h Normal file
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@ -0,0 +1,324 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief AT32UC3A EVK1100 board header file.
*
* This file contains definitions and services related to the features of the
* EVK1100 board rev. A.
*
* To use this board, define BOARD=EVK1100 and EVK1100_REVA.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 AT32UC3A devices can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _EVK1100_REVA_H_
#define _EVK1100_REVA_H_
#include "compiler.h"
//#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
//# include "led.h"
//#endif // __AVR32_ABI_COMPILER__
/*! \name Oscillator Definitions
*/
//! @{
// RCOsc has no custom calibration by default. Set the following definition to
// the appropriate value if a custom RCOsc calibration has been applied to your
// part.
//#define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< RCOsc frequency: Hz.
#define FOSC32 32768 //!< Osc32 frequency: Hz.
#define OSC32_STARTUP AVR32_PM_OSCCTRL32_STARTUP_8192_RCOSC //!< Osc32 startup time: RCOsc periods.
#define FOSC0 12000000 //!< Osc0 frequency: Hz.
#define OSC0_STARTUP AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC //!< Osc0 startup time: RCOsc periods.
// Osc1 crystal is not mounted by default. Set the following definitions to the
// appropriate values if a custom Osc1 crystal is mounted on your board.
//#define FOSC1 12000000 //!< Osc1 frequency: Hz.
//#define OSC1_STARTUP AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC //!< Osc1 startup time: RCOsc periods.
//! @}
/*! \name SDRAM Definitions
*/
//! @{
//! Part header file of used SDRAM(s).
#define SDRAM_PART_HDR "MT48LC16M16A2TG7E/mt48lc16m16a2tg7e.h"
//! Data bus width to use the SDRAM(s) with (16 or 32 bits; always 16 bits on
//! UC3).
#define SDRAM_DBW 16
//! @}
/*! \name USB Definitions
*/
//! @{
//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x.
//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and
//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from <avr32/uc3axxxx.h>.
#define USB_ID AVR32_USBB_USB_ID_0_0
//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x.
//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and
//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from <avr32/uc3axxxx.h>.
#define USB_VBOF AVR32_USBB_USB_VBOF_0_0
//! Active level of the USB_VBOF output pin.
#define USB_VBOF_ACTIVE_LEVEL HIGH
//! USB overcurrent detection pin.
#define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PB18
//! @}
//! GPIO connection of the MAC PHY PWR_DOWN/INT signal.
#define MACB_INTERRUPT_PIN AVR32_PIN_PX12
//! Number of LEDs.
#define LED_COUNT 8
/*! \name GPIO Connections of LEDs
*/
//! @{
#define LED0_GPIO AVR32_PIN_PX13
#define LED1_GPIO AVR32_PIN_PX14
#define LED2_GPIO AVR32_PIN_PX15
#define LED3_GPIO AVR32_PIN_PX16
#define LED4_GPIO AVR32_PIN_PB19
#define LED5_GPIO AVR32_PIN_PB20
#define LED6_GPIO AVR32_PIN_PB21
#define LED7_GPIO AVR32_PIN_PB22
//! @}
/*! \name PWM Channels of LEDs
*/
//! @{
#define LED0_PWM (-1)
#define LED1_PWM (-1)
#define LED2_PWM (-1)
#define LED3_PWM (-1)
#define LED4_PWM 0
#define LED5_PWM 1
#define LED6_PWM 2
#define LED7_PWM 3
//! @}
/*! \name PWM Functions of LEDs
*/
//! @{
#define LED0_PWM_FUNCTION (-1)
#define LED1_PWM_FUNCTION (-1)
#define LED2_PWM_FUNCTION (-1)
#define LED3_PWM_FUNCTION (-1)
#define LED4_PWM_FUNCTION AVR32_PWM_0_FUNCTION
#define LED5_PWM_FUNCTION AVR32_PWM_1_FUNCTION
#define LED6_PWM_FUNCTION AVR32_PWM_2_FUNCTION
#define LED7_PWM_FUNCTION AVR32_PWM_3_FUNCTION
//! @}
/*! \name Color Identifiers of LEDs to Use with LED Functions
*/
//! @{
#define LED_MONO0_GREEN LED4
#define LED_MONO1_GREEN LED5
#define LED_MONO2_GREEN LED6
#define LED_MONO3_GREEN LED7
#define LED_BI0_GREEN LED1
#define LED_BI0_RED LED0
#define LED_BI1_GREEN LED3
#define LED_BI1_RED LED2
//! @}
/*! \name GPIO Connections of Push Buttons
*/
//! @{
#define GPIO_PUSH_BUTTON_0 AVR32_PIN_PB28
#define GPIO_PUSH_BUTTON_0_PRESSED 0
#define GPIO_PUSH_BUTTON_1 AVR32_PIN_PB29
#define GPIO_PUSH_BUTTON_1_PRESSED 0
#define GPIO_PUSH_BUTTON_2 AVR32_PIN_PB27
#define GPIO_PUSH_BUTTON_2_PRESSED 0
//! @}
/*! \name GPIO Connections of the Joystick
*/
//! @{
#define GPIO_JOYSTICK_PUSH AVR32_PIN_PA20
#define GPIO_JOYSTICK_PUSH_PRESSED 0
#define GPIO_JOYSTICK_LEFT AVR32_PIN_PA25
#define GPIO_JOYSTICK_LEFT_PRESSED 0
#define GPIO_JOYSTICK_RIGHT AVR32_PIN_PA28
#define GPIO_JOYSTICK_RIGHT_PRESSED 0
#define GPIO_JOYSTICK_UP AVR32_PIN_PA26
#define GPIO_JOYSTICK_UP_PRESSED 0
#define GPIO_JOYSTICK_DOWN AVR32_PIN_PA27
#define GPIO_JOYSTICK_DOWN_PRESSED 0
//! @}
/*! \name ADC Connection of the Potentiometer
*/
//! @{
#define ADC_POTENTIOMETER_CHANNEL 1
#define ADC_POTENTIOMETER_PIN AVR32_ADC_AD_1_PIN
#define ADC_POTENTIOMETER_FUNCTION AVR32_ADC_AD_1_FUNCTION
//! @}
/*! \name ADC Connection of the Temperature Sensor
*/
//! @{
#define ADC_TEMPERATURE_CHANNEL 0
#define ADC_TEMPERATURE_PIN AVR32_ADC_AD_0_PIN
#define ADC_TEMPERATURE_FUNCTION AVR32_ADC_AD_0_FUNCTION
//! @}
/*! \name ADC Connection of the Light Sensor
*/
//! @{
#define ADC_LIGHT_CHANNEL 2
#define ADC_LIGHT_PIN AVR32_ADC_AD_2_PIN
#define ADC_LIGHT_FUNCTION AVR32_ADC_AD_2_FUNCTION
//! @}
/*! \name SPI Connections of the DIP204 LCD
*/
//! @{
#define DIP204_SPI (&AVR32_SPI1)
#define DIP204_SPI_NPCS 2
#define DIP204_SPI_SCK_PIN AVR32_SPI1_SCK_0_0_PIN
#define DIP204_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_0_FUNCTION
#define DIP204_SPI_MISO_PIN AVR32_SPI1_MISO_0_0_PIN
#define DIP204_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_0_FUNCTION
#define DIP204_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_0_PIN
#define DIP204_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_0_FUNCTION
#define DIP204_SPI_NPCS_PIN AVR32_SPI1_NPCS_2_0_PIN
#define DIP204_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_2_0_FUNCTION
//! @}
/*! \name GPIO and PWM Connections of the DIP204 LCD Backlight
*/
//! @{
#define DIP204_BACKLIGHT_PIN AVR32_PIN_PB18
#define DIP204_PWM_CHANNEL 6
#define DIP204_PWM_PIN AVR32_PWM_6_PIN
#define DIP204_PWM_FUNCTION AVR32_PWM_6_FUNCTION
//! @}
/*! \name SPI Connections of the AT45DBX Data Flash Memory
*/
//! @{
#define AT45DBX_SPI (&AVR32_SPI1)
#define AT45DBX_SPI_NPCS 0
#define AT45DBX_SPI_SCK_PIN AVR32_SPI1_SCK_0_0_PIN
#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_0_FUNCTION
#define AT45DBX_SPI_MISO_PIN AVR32_SPI1_MISO_0_0_PIN
#define AT45DBX_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_0_FUNCTION
#define AT45DBX_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_0_PIN
#define AT45DBX_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_0_FUNCTION
#define AT45DBX_SPI_NPCS0_PIN AVR32_SPI1_NPCS_0_0_PIN
#define AT45DBX_SPI_NPCS0_FUNCTION AVR32_SPI1_NPCS_0_0_FUNCTION
//! @}
/*! \name GPIO and SPI Connections of the SD/MMC Connector
*/
//! @{
#define SD_MMC_CARD_DETECT_PIN AVR32_PIN_PA02
#define SD_MMC_WRITE_PROTECT_PIN AVR32_PIN_PA07
#define SD_MMC_SPI (&AVR32_SPI1)
#define SD_MMC_SPI_NPCS 1
#define SD_MMC_SPI_SCK_PIN AVR32_SPI1_SCK_0_0_PIN
#define SD_MMC_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_0_FUNCTION
#define SD_MMC_SPI_MISO_PIN AVR32_SPI1_MISO_0_0_PIN
#define SD_MMC_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_0_FUNCTION
#define SD_MMC_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_0_PIN
#define SD_MMC_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_0_FUNCTION
#define SD_MMC_SPI_NPCS_PIN AVR32_SPI1_NPCS_1_0_PIN
#define SD_MMC_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_1_0_FUNCTION
//! @}
/*! \name TWI Connections of the Spare TWI Connector
*/
//! @{
#define SPARE_TWI (&AVR32_TWI)
#define SPARE_TWI_SCL_PIN AVR32_TWI_SCL_0_0_PIN
#define SPARE_TWI_SCL_FUNCTION AVR32_TWI_SCL_0_0_FUNCTION
#define SPARE_TWI_SDA_PIN AVR32_TWI_SDA_0_0_PIN
#define SPARE_TWI_SDA_FUNCTION AVR32_TWI_SDA_0_0_FUNCTION
//! @}
/*! \name SPI Connections of the Spare SPI Connector
*/
//! @{
#define SPARE_SPI (&AVR32_SPI0)
#define SPARE_SPI_NPCS 0
#define SPARE_SPI_SCK_PIN AVR32_SPI0_SCK_0_0_PIN
#define SPARE_SPI_SCK_FUNCTION AVR32_SPI0_SCK_0_0_FUNCTION
#define SPARE_SPI_MISO_PIN AVR32_SPI0_MISO_0_0_PIN
#define SPARE_SPI_MISO_FUNCTION AVR32_SPI0_MISO_0_0_FUNCTION
#define SPARE_SPI_MOSI_PIN AVR32_SPI0_MOSI_0_0_PIN
#define SPARE_SPI_MOSI_FUNCTION AVR32_SPI0_MOSI_0_0_FUNCTION
#define SPARE_SPI_NPCS_PIN AVR32_SPI0_NPCS_0_0_PIN
#define SPARE_SPI_NPCS_FUNCTION AVR32_SPI0_NPCS_0_0_FUNCTION
//! @}
#endif // _EVK1100_REVA_H_

235
src/platform/avr32/mt48lc16m16a2tg7e.h → src/platform/avr32/MT48LC16M16A2TG7E/mt48lc16m16a2tg7e.h
View File

@ -1,117 +1,120 @@
/* This header file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief MT48LC16M16A2TG-7E SDRAM driver for AVR32 UC3 SDRAMC on EBI.
*
* \note The values defined in this file are device-specific. See the device
* datasheet for further information.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an SDRAMC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MT48LC16M16A2TG7E_H_
#define _MT48LC16M16A2TG7E_H_
//! The number of bank bits for this SDRAM (1 or 2).
#define SDRAM_BANK_BITS 2
//! The number of row bits for this SDRAM (11 to 13).
#define SDRAM_ROW_BITS 13
//! The number of column bits for this SDRAM (8 to 11).
#define SDRAM_COL_BITS 9
//! The minimal column address select (READ) latency for this SDRAM (1 to 3 SDRAM cycles).
//! Unit: tCK (SDRAM cycle period).
#define SDRAM_CAS 2
//! The minimal write recovery time for this SDRAM (0 to 15 SDRAM cycles).
//! Unit: ns.
#define SDRAM_TWR 14
//! The minimal row cycle time for this SDRAM (0 to 15 SDRAM cycles).
//! ACTIVE-to-ACTIVE command delay.
//! Unit: ns.
#define SDRAM_TRC 60
//! The minimal row precharge time for this SDRAM (0 to 15 SDRAM cycles).
//! PRECHARGE command period.
//! Unit: ns.
#define SDRAM_TRP 15
//! The minimal row to column delay time for this SDRAM (0 to 15 SDRAM cycles).
//! ACTIVE-to-READ/WRITE command delay.
//! Unit: ns.
#define SDRAM_TRCD 15
//! The minimal row address select time for this SDRAM (0 to 15 SDRAM cycles).
//! ACTIVE-to-PRECHARGE command delay.
//! Unit: ns.
#define SDRAM_TRAS 37
//! The minimal exit self refresh time for this SDRAM (0 to 15 SDRAM cycles).
//! Exit SELF REFRESH to ACTIVE command delay.
//! Unit: ns.
#define SDRAM_TXSR 67
//! The maximal refresh time for this SDRAM (0 to 4095 SDRAM cycles).
//! Refresh period.
//! Unit: ns.
#define SDRAM_TR 7812
//! The minimal refresh cycle time for this SDRAM.
//! AUTO REFRESH command period.
//! Unit: ns.
#define SDRAM_TRFC 66
//! The minimal mode register delay time for this SDRAM.
//! LOAD MODE REGISTER command to ACTIVE or REFRESH command delay.
//! Unit: tCK (SDRAM cycle period).
#define SDRAM_TMRD 2
//! The minimal stable-clock initialization delay for this SDRAM.
//! Unit: us.
#define SDRAM_STABLE_CLOCK_INIT_DELAY 100
//! The minimal number of AUTO REFRESH commands required during initialization for this SDRAM.
#define SDRAM_INIT_AUTO_REFRESH_COUNT 2
#endif // _MT48LC16M16A2TG7E_H_
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief MT48LC16M16A2TG-7E SDRAM driver for AVR32 UC3 SDRAMC on EBI.
*
* \note The values defined in this file are device-specific. See the device
* datasheet for further information.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an SDRAMC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _MT48LC16M16A2TG7E_H_
#define _MT48LC16M16A2TG7E_H_
//! The number of bank bits for this SDRAM (1 or 2).
#define SDRAM_BANK_BITS 2
//! The number of row bits for this SDRAM (11 to 13).
#define SDRAM_ROW_BITS 13
//! The number of column bits for this SDRAM (8 to 11).
#define SDRAM_COL_BITS 9
//! The minimal column address select (READ) latency for this SDRAM (1 to 3 SDRAM cycles).
//! Unit: tCK (SDRAM cycle period).
#define SDRAM_CAS 2
//! The minimal write recovery time for this SDRAM (0 to 15 SDRAM cycles).
//! Unit: ns.
#define SDRAM_TWR 14
//! The minimal row cycle time for this SDRAM (0 to 15 SDRAM cycles).
//! ACTIVE-to-ACTIVE command delay.
//! Unit: ns.
#define SDRAM_TRC 60
//! The minimal row precharge time for this SDRAM (0 to 15 SDRAM cycles).
//! PRECHARGE command period.
//! Unit: ns.
#define SDRAM_TRP 15
//! The minimal row to column delay time for this SDRAM (0 to 15 SDRAM cycles).
//! ACTIVE-to-READ/WRITE command delay.
//! Unit: ns.
#define SDRAM_TRCD 15
//! The minimal row address select time for this SDRAM (0 to 15 SDRAM cycles).
//! ACTIVE-to-PRECHARGE command delay.
//! Unit: ns.
#define SDRAM_TRAS 37
//! The minimal exit self refresh time for this SDRAM (0 to 15 SDRAM cycles).
//! Exit SELF REFRESH to ACTIVE command delay.
//! Unit: ns.
#define SDRAM_TXSR 67
//! The maximal refresh time for this SDRAM (0 to 4095 SDRAM cycles).
//! Refresh period.
//! Unit: ns.
#define SDRAM_TR 7812
//! The minimal refresh cycle time for this SDRAM.
//! AUTO REFRESH command period.
//! Unit: ns.
#define SDRAM_TRFC 66
//! The minimal mode register delay time for this SDRAM.
//! LOAD MODE REGISTER command to ACTIVE or REFRESH command delay.
//! Unit: tCK (SDRAM cycle period).
#define SDRAM_TMRD 2
//! The minimal stable-clock initialization delay for this SDRAM.
//! Unit: us.
#define SDRAM_STABLE_CLOCK_INIT_DELAY 100
//! The minimal number of AUTO REFRESH commands required during initialization for this SDRAM.
#define SDRAM_INIT_AUTO_REFRESH_COUNT 2
#endif // _MT48LC16M16A2TG7E_H_

189
src/platform/avr32/board.h
View File

@ -1,77 +1,120 @@
/* This header file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Standard board header file.
*
* This file includes the appropriate board header file according to the
* defined board.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#include <avr32/io.h>
/*! \name Base Boards
*/
//! @{
#define EVK1100 1 //!< AT32UC3A EVK1100 board.
#define EVK1101 2 //!< AT32UC3B EVK1101 board.
#define STK1000 3 //!< AT32AP7000 STK1000 board.
#define NGW100 4 //!< AT32AP7000 NGW100 board.
#define USER_BOARD 99 //!< User-reserved board (if any).
//! @}
/*! \name Extension Boards
*/
//! @{
#define EXT1102 1 //!< AT32UC3B EXT1102 board.
#define MC300 2 //!< AT32UC3 MC300 board.
#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).
//! @}
#include "evk1100.h"
#ifndef FRCOSC
#define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< Default RCOsc frequency.
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Standard board header file.
*
* This file includes the appropriate board header file according to the
* defined board.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#include <avr32/io.h>
/*! \name Base Boards
*/
//! @{
#define EVK1100 1 //!< AT32UC3A EVK1100 board.
#define EVK1101 2 //!< AT32UC3B EVK1101 board.
#define UC3C_EK 3 //!< AT32UC3C UC3C_EK board.
#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.
#define EVK1105 5 //!< AT32UC3A EVK1105 board.
#define STK1000 6 //!< AT32AP7000 STK1000 board.
#define NGW100 7 //!< AT32AP7000 NGW100 board.
#define STK600_RCUC3L0 8 //!< STK600 RCUC3L0 board.
#define UC3L_EK 9 //!< AT32UC3L-EK board.
#define USER_BOARD 99 //!< User-reserved board (if any).
//! @}
/*! \name Extension Boards
*/
//! @{
#define EXT1102 1 //!< AT32UC3B EXT1102 board.
#define MC300 2 //!< AT32UC3 MC300 board.
#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).
//! @}
#if BOARD == EVK1100
#include "EVK1100/evk1100.h"
#elif BOARD == EVK1101
#include "EVK1101/evk1101.h"
#elif BOARD == UC3C_EK
#include "UC3C_EK/uc3c_ek.h"
#elif BOARD == EVK1104
#include "EVK1104/evk1104.h"
#elif BOARD == EVK1105
#include "EVK1105/evk1105.h"
#elif BOARD == STK1000
#include "STK1000/stk1000.h"
#elif BOARD == NGW100
#include "NGW100/ngw100.h"
#elif BOARD == STK600_RCUC3L0
#include "STK600/RCUC3L0/stk600_rcuc3l0.h"
#elif BOARD == UC3L_EK
#include "UC3L_EK/uc3l_ek.h"
#elif BOARD == USER_BOARD
// User-reserved area: #include the header file of your board here (if any).
#include "user_board.h"
#else
#error No known AVR32 board defined
#endif
#if (defined EXT_BOARD)
#if EXT_BOARD == EXT1102
#include "EXT1102/ext1102.h"
#elif EXT_BOARD == MC300
#include "MC300/mc300.h"
#elif EXT_BOARD == USER_EXT_BOARD
// User-reserved area: #include the header file of your extension board here
// (if any).
#endif
#endif
#ifndef FRCOSC
#define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< Default RCOsc frequency.
#endif
#define REQ_CPU_FREQ 60000000

2255
src/platform/avr32/compiler.h
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File diff suppressed because it is too large Load Diff

243
src/platform/avr32/conf_isp.h
View File

@ -1,121 +1,124 @@
/* This header file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file ******************************************************************
*
* \brief ISP configuration file.
*
* This file contains the possible external configuration of the ISP.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a USB module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
***************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CONF_ISP_H_
#define _CONF_ISP_H_
#include <avr32/io.h>
#include "compiler.h"
//_____ D E F I N I T I O N S ______________________________________________
#define PRODUCT_MANUFACTURER_ID 0x58
#define PRODUCT_FAMILY_ID 0x20
#define ISP_VERSION 0x02
#define ISP_ID0 0x00
#define ISP_ID1 0x00
#define ISP_GPFB_FORCE 31
#define ISP_GPFB_FORCE_MASK 0x80000000
#define ISP_GPFB_FORCE_OFFSET 31
#define ISP_GPFB_FORCE_SIZE 1
#define ISP_GPFB_IO_COND_EN 30
#define ISP_GPFB_IO_COND_EN_MASK 0x40000000
#define ISP_GPFB_IO_COND_EN_OFFSET 30
#define ISP_GPFB_IO_COND_EN_SIZE 1
#define ISP_GPFB_BOD_EN 29
#define ISP_GPFB_BOD_EN_MASK 0x20000000
#define ISP_GPFB_BOD_EN_OFFSET 29
#define ISP_GPFB_BOD_EN_SIZE 1
#define ISP_CFG (*(volatile U32 *)ISP_CFG_ADDRESS)
#define ISP_CFG_ADDRESS (AVR32_FLASHC_USER_PAGE_ADDRESS + ISP_CFG_OFFSET)
#define ISP_CFG_OFFSET 0x000001FC
#define ISP_CFG_SIZE 4
#define ISP_CFG_BOOT_KEY 17
#define ISP_CFG_BOOT_KEY_MASK 0xFFFE0000
#define ISP_CFG_BOOT_KEY_OFFSET 17
#define ISP_CFG_BOOT_KEY_SIZE 15
#define ISP_CFG_BOOT_KEY_VALUE 0x494F
#define ISP_CFG_IO_COND_LEVEL 16
#define ISP_CFG_IO_COND_LEVEL_MASK 0x00010000
#define ISP_CFG_IO_COND_LEVEL_OFFSET 16
#define ISP_CFG_IO_COND_LEVEL_SIZE 1
#define ISP_CFG_IO_COND_PIN 8
#define ISP_CFG_IO_COND_PIN_MASK 0x0000FF00
#define ISP_CFG_IO_COND_PIN_OFFSET 8
#define ISP_CFG_IO_COND_PIN_SIZE 8
#define ISP_CFG_CRC8 0
#define ISP_CFG_CRC8_MASK 0x000000FF
#define ISP_CFG_CRC8_OFFSET 0
#define ISP_CFG_CRC8_SIZE 8
#define ISP_CFG_CRC8_POLYNOMIAL 0x107
#define ISP_KEY (*(volatile U32 *)ISP_KEY_ADDRESS)
#define ISP_KEY_ADDRESS (AVR32_SRAM_ADDRESS + ISP_KEY_OFFSET)
#define ISP_KEY_OFFSET 0x00000000
#define ISP_KEY_SIZE 4
#define ISP_KEY_VALUE ('I' << 24 | 'S' << 16 | 'P' << 8 | 'K')
#ifndef ISP_OSC
#define ISP_OSC 0
#endif
#define DFU_FRAME_LENGTH 2048
#define PROGRAM_START_ADDRESS (AVR32_FLASH_ADDRESS + PROGRAM_START_OFFSET)
#define PROGRAM_START_OFFSET 0x00002000
#endif // _CONF_ISP_H_
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file ******************************************************************
*
* \brief ISP configuration file.
*
* This file contains the possible external configuration of the ISP.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a USB module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
***************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _CONF_ISP_H_
#define _CONF_ISP_H_
#include <avr32/io.h>
#include "compiler.h"
//_____ D E F I N I T I O N S ______________________________________________
#define PRODUCT_MANUFACTURER_ID 0x58
#define PRODUCT_FAMILY_ID 0x20
#define ISP_VERSION 0x03
#define ISP_ID0 0x00
#define ISP_ID1 0x00
#define ISP_GPFB_FORCE 31
#define ISP_GPFB_FORCE_MASK 0x80000000
#define ISP_GPFB_FORCE_OFFSET 31
#define ISP_GPFB_FORCE_SIZE 1
#define ISP_GPFB_IO_COND_EN 30
#define ISP_GPFB_IO_COND_EN_MASK 0x40000000
#define ISP_GPFB_IO_COND_EN_OFFSET 30
#define ISP_GPFB_IO_COND_EN_SIZE 1
#define ISP_GPFB_BOD_EN 29
#define ISP_GPFB_BOD_EN_MASK 0x20000000
#define ISP_GPFB_BOD_EN_OFFSET 29
#define ISP_GPFB_BOD_EN_SIZE 1
#define ISP_CFG (*(volatile U32 *)ISP_CFG_ADDRESS)
#define ISP_CFG_ADDRESS (AVR32_FLASHC_USER_PAGE_ADDRESS + ISP_CFG_OFFSET)
#define ISP_CFG_OFFSET 0x000001FC
#define ISP_CFG_SIZE 4
#define ISP_CFG_BOOT_KEY 17
#define ISP_CFG_BOOT_KEY_MASK 0xFFFE0000
#define ISP_CFG_BOOT_KEY_OFFSET 17
#define ISP_CFG_BOOT_KEY_SIZE 15
#define ISP_CFG_BOOT_KEY_VALUE 0x494F
#define ISP_CFG_IO_COND_LEVEL 16
#define ISP_CFG_IO_COND_LEVEL_MASK 0x00010000
#define ISP_CFG_IO_COND_LEVEL_OFFSET 16
#define ISP_CFG_IO_COND_LEVEL_SIZE 1
#define ISP_CFG_IO_COND_PIN 8
#define ISP_CFG_IO_COND_PIN_MASK 0x0000FF00
#define ISP_CFG_IO_COND_PIN_OFFSET 8
#define ISP_CFG_IO_COND_PIN_SIZE 8
#define ISP_CFG_CRC8 0
#define ISP_CFG_CRC8_MASK 0x000000FF
#define ISP_CFG_CRC8_OFFSET 0
#define ISP_CFG_CRC8_SIZE 8
#define ISP_CFG_CRC8_POLYNOMIAL 0x107
#define ISP_KEY (*(volatile U32 *)ISP_KEY_ADDRESS)
#define ISP_KEY_ADDRESS (AVR32_SRAM_ADDRESS + ISP_KEY_OFFSET)
#define ISP_KEY_OFFSET 0x00000000
#define ISP_KEY_SIZE 4
#define ISP_KEY_VALUE ('I' << 24 | 'S' << 16 | 'P' << 8 | 'K')
#ifndef ISP_OSC
#define ISP_OSC 0
#endif
#define DFU_FRAME_LENGTH 2048
#define PROGRAM_START_ADDRESS (AVR32_FLASH_ADDRESS + PROGRAM_START_OFFSET)
#define PROGRAM_START_OFFSET 0x00002000
#endif // _CONF_ISP_H_

107
src/platform/avr32/exception.s
View File

@ -1,14 +1,14 @@
/* This file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Exception and interrupt vectors.
*
* This file maps all events supported by an AVR32UC.
* This file maps all events supported by an AVR32.
*
* - Compiler: GNU GCC for AVR32
* - Supported devices: All AVR32UC devices with an INTC module can be used.
* - Supported devices: All AVR32 devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
@ -16,33 +16,41 @@
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#if !__AVR32_UC__ && !__AVR32_AP__
#error Implementation of the AVR32 architecture not supported by the INTC driver.
#endif
#include <avr32/io.h>
@ -71,7 +79,7 @@ _handle_Unrecoverable_Exception:
rjmp $
.org 0x004
// TLB Multiple Hit: UNUSED IN AVR32UC.
// TLB Multiple Hit.
_handle_TLB_Multiple_Hit:
rjmp $
@ -121,7 +129,7 @@ _handle_Privilege_Violation:
rjmp $
.org 0x02C
// Floating-Point: UNUSED IN AVR32UC.
// Floating-Point: UNUSED IN AVR32UC and AVR32AP.
_handle_Floating_Point:
rjmp $
@ -156,17 +164,17 @@ _handle_DTLB_Modified:
rjmp $
.org 0x050
// ITLB Miss: UNUSED IN AVR32UC.
// ITLB Miss.
_handle_ITLB_Miss:
rjmp $
.org 0x060
// DTLB Miss (Read): UNUSED IN AVR32UC.
// DTLB Miss (Read).
_handle_DTLB_Miss_Read:
rjmp $
.org 0x070
// DTLB Miss (Write): UNUSED IN AVR32UC.
// DTLB Miss (Write).
_handle_DTLB_Miss_Write:
rjmp $
@ -185,41 +193,30 @@ _handle_Supervisor_Call:
.balign 4
_int0:
.irp priority, 0, 1, 2, 3
_int\priority:
#if __AVR32_UC__
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry.
mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function.
// CPU upon interrupt entry. No other register is saved by hardware.
#elif __AVR32_AP__
// PC and SR are automatically saved in respectively RAR_INTx and RSR_INTx by
// the CPU upon interrupt entry. No other register is saved by hardware.
pushm r8-r12, lr
#endif
mov r12, \priority // Pass the int_level parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
_int1:
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry.
mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
_int2:
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry.
mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
_int3:
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry.
mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
#if __AVR32_UC__
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
#elif __AVR32_AP__
breq spint\priority // If this was a spurious interrupt (R12 == NULL), branch.
st.w --sp, r12 // Push the pointer to the interrupt handler onto the system stack since no register may be altered.
popm r8-r12, lr, pc // Restore registers and jump to the handler.
spint\priority:
popm r8-r12, lr
#endif
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
.endr
// Constant data area.
@ -232,10 +229,10 @@ _int3:
.global ipr_val
.type ipr_val, @object
ipr_val:
.word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEV_OFFSET) | (_int0 - _evba),\
(AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEV_OFFSET) | (_int1 - _evba),\
(AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEV_OFFSET) | (_int2 - _evba),\
(AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEV_OFFSET) | (_int3 - _evba)
.word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\
(AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\
(AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\
(AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba)
//! \endverbatim

2175
src/platform/avr32/flashc.c
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File diff suppressed because it is too large Load Diff

1994
src/platform/avr32/flashc.h
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File diff suppressed because it is too large Load Diff

731
src/platform/avr32/gpio.c
View File

@ -1,270 +1,461 @@
/* This source file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief GPIO driver for AVR32 UC3.
*
* This file defines a useful set of functions for the GPIO.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a GPIO module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gpio.h"
//! GPIO module instance.
#define GPIO AVR32_GPIO
/*! \name Peripheral Bus Interface
*/
//! @{
int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size)
{
int status = GPIO_SUCCESS;
unsigned int i;
for (i = 0; i < size; i++)
{
status |= gpio_enable_module_pin(gpiomap->pin, gpiomap->function);
gpiomap++;
}
return status;
}
int gpio_enable_module_pin(unsigned int pin, unsigned int function)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
// Enable the correct function.
switch (function)
{
case 0: // A function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
break;
case 1: // B function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
break;
case 2: // C function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
break;
default:
return GPIO_INVALID_ARGUMENT;
}
// Disable GPIO control.
gpio_port->gperc = 1 << (pin & 0x1F);
return GPIO_SUCCESS;
}
void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size)
{
unsigned int i;
for (i = 0; i < size; i++)
{
gpio_enable_gpio_pin(gpiomap->pin);
gpiomap++;
}
}
void gpio_enable_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->oderc = 1 << (pin & 0x1F);
gpio_port->gpers = 1 << (pin & 0x1F);
}
void gpio_enable_pin_open_drain(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->odmers = 1 << (pin & 0x1F);
}
void gpio_disable_pin_open_drain(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->odmerc = 1 << (pin & 0x1F);
}
void gpio_enable_pin_pull_up(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puers = 1 << (pin & 0x1F);
}
void gpio_disable_pin_pull_up(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
}
int gpio_get_pin_value(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return (gpio_port->pvr >> (pin & 0x1F)) & 1;
}
int gpio_get_gpio_pin_output_value(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return (gpio_port->ovr >> (pin & 0x1F)) & 1;
}
void gpio_set_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrs = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 1.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_clr_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_tgl_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrt = 1 << (pin & 0x1F); // Toggle the I/O line.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_enable_pin_glitch_filter(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->gfers = 1 << (pin & 0x1F);
}
void gpio_disable_pin_glitch_filter(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->gferc = 1 << (pin & 0x1F);
}
int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
// Enable the glitch filter.
gpio_port->gfers = 1 << (pin & 0x1F);
// Configure the edge detector.
switch (mode)
{
case GPIO_PIN_CHANGE:
gpio_port->imr0c = 1 << (pin & 0x1F);
gpio_port->imr1c = 1 << (pin & 0x1F);
break;
case GPIO_RISING_EDGE:
gpio_port->imr0s = 1 << (pin & 0x1F);
gpio_port->imr1c = 1 << (pin & 0x1F);
break;
case GPIO_FALLING_EDGE:
gpio_port->imr0c = 1 << (pin & 0x1F);
gpio_port->imr1s = 1 << (pin & 0x1F);
break;
default:
return GPIO_INVALID_ARGUMENT;
}
// Enable interrupt.
gpio_port->iers = 1 << (pin & 0x1F);
return GPIO_SUCCESS;
}
void gpio_disable_pin_interrupt(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ierc = 1 << (pin & 0x1F);
}
int gpio_get_pin_interrupt_flag(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return (gpio_port->ifr >> (pin & 0x1F)) & 1;
}
void gpio_clear_pin_interrupt_flag(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ifrc = 1 << (pin & 0x1F);
}
//! @}
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief GPIO driver for AVR32 UC3.
*
* This file defines a useful set of functions for the GPIO.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a GPIO module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#include "gpio.h"
//! GPIO module instance.
#define GPIO AVR32_GPIO
/*! \name Peripheral Bus Interface
*/
//! @{
int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size)
{
int status = GPIO_SUCCESS;
unsigned int i;
for (i = 0; i < size; i++)
{
status |= gpio_enable_module_pin(gpiomap->pin, gpiomap->function);
gpiomap++;
}
return status;
}
int gpio_enable_module_pin(unsigned int pin, unsigned int function)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
// Enable the correct function.
switch (function)
{
case 0: // A function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
case 1: // B function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
case 2: // C function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
case 3: // D function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
case 4: // E function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
case 5: // F function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
case 6: // G function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
case 7: // H function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
#endif
default:
return GPIO_INVALID_ARGUMENT;
}
// Disable GPIO control.
gpio_port->gperc = 1 << (pin & 0x1F);
return GPIO_SUCCESS;
}
void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size)
{
unsigned int i;
for (i = 0; i < size; i++)
{
gpio_enable_gpio_pin(gpiomap->pin);
gpiomap++;
}
}
void gpio_enable_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->oderc = 1 << (pin & 0x1F);
gpio_port->gpers = 1 << (pin & 0x1F);
}
// The open-drain mode is not synthesized on the current AVR32 products.
// If one day some AVR32 products have this feature, the corresponding part
// numbers should be listed in the #if below.
// Note that other functions are available in this driver to use pins with open
// drain in GPIO mode. The advantage of the open-drain mode functions over these
// other functions is that they can be used not only in GPIO mode but also in
// module mode.
#if 0
void gpio_enable_pin_open_drain(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->odmers = 1 << (pin & 0x1F);
}
void gpio_disable_pin_open_drain(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->odmerc = 1 << (pin & 0x1F);
}
#endif
void gpio_enable_pin_pull_up(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puers = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pderc = 1 << (pin & 0x1F);
#endif
}
void gpio_disable_pin_pull_up(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
}
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control.
/*! \brief Enables the pull-down resistor of a pin.
*
* \param pin The pin number.
*/
void gpio_enable_pin_pull_down(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
gpio_port->pders = 1 << (pin & 0x1F);
}
/*! \brief Disables the pull-down resistor of a pin.
*
* \param pin The pin number.
*/
void gpio_disable_pin_pull_down(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->pderc = 1 << (pin & 0x1F);
}
/*! \brief Enables the buskeeper functionality on a pin.
*
* \param pin The pin number.
*/
void gpio_enable_pin_buskeeper(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puers = 1 << (pin & 0x1F);
gpio_port->pders = 1 << (pin & 0x1F);
}
/*! \brief Disables the buskeeper functionality on a pin.
*
* \param pin The pin number.
*/
void gpio_disable_pin_buskeeper(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
gpio_port->pderc = 1 << (pin & 0x1F);
}
#endif
int gpio_get_pin_value(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return (gpio_port->pvr >> (pin & 0x1F)) & 1;
}
int gpio_get_gpio_pin_output_value(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return (gpio_port->ovr >> (pin & 0x1F)) & 1;
}
int gpio_get_gpio_open_drain_pin_output_value(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return ((gpio_port->oder >> (pin & 0x1F)) & 1) ^ 1;
}
void gpio_set_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrs = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 1.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_clr_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_tgl_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrt = 1 << (pin & 0x1F); // Toggle the I/O line.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_set_gpio_open_drain_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_clr_gpio_open_drain_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_tgl_gpio_open_drain_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line if the GPIO output driver is enabled: 0.
gpio_port->odert = 1 << (pin & 0x1F); // The GPIO output driver is toggled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_enable_pin_glitch_filter(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->gfers = 1 << (pin & 0x1F);
}
void gpio_disable_pin_glitch_filter(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->gferc = 1 << (pin & 0x1F);
}
/*! \brief Configure the edge detector of an input pin
*
* \param pin The pin number.
* \param mode The edge detection mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE
* or \ref GPIO_FALLING_EDGE).
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
static int gpio_configure_edge_detector(unsigned int pin, unsigned int mode)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
// Configure the edge detector.
switch (mode)
{
case GPIO_PIN_CHANGE:
gpio_port->imr0c = 1 << (pin & 0x1F);
gpio_port->imr1c = 1 << (pin & 0x1F);
break;
case GPIO_RISING_EDGE:
gpio_port->imr0s = 1 << (pin & 0x1F);
gpio_port->imr1c = 1 << (pin & 0x1F);
break;
case GPIO_FALLING_EDGE:
gpio_port->imr0c = 1 << (pin & 0x1F);
gpio_port->imr1s = 1 << (pin & 0x1F);
break;
default:
return GPIO_INVALID_ARGUMENT;
}
return GPIO_SUCCESS;
}
int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
// Enable the glitch filter.
gpio_port->gfers = 1 << (pin & 0x1F);
// Configure the edge detector.
if(GPIO_INVALID_ARGUMENT == gpio_configure_edge_detector(pin, mode))
return(GPIO_INVALID_ARGUMENT);
// Enable interrupt.
gpio_port->iers = 1 << (pin & 0x1F);
return GPIO_SUCCESS;
}
void gpio_disable_pin_interrupt(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ierc = 1 << (pin & 0x1F);
}
int gpio_get_pin_interrupt_flag(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return (gpio_port->ifr >> (pin & 0x1F)) & 1;
}
void gpio_clear_pin_interrupt_flag(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ifrc = 1 << (pin & 0x1F);
}
//#
//# Peripheral Event System Support.
//#
#if (((defined __GNUC__) && ((defined __AVR32_UC3L016__) || (defined __AVR32_UC3L032__) || (defined __AVR32_UC3L064__))) \
||((defined __ICCAVR32__) && ((defined __AT32UC3L016__) || (defined __AT32UC3L032__) || (defined __AT32UC3L064__) )))
int gpio_configure_pin_periph_event_mode(unsigned int pin, unsigned int mode, unsigned int use_igf)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
if(TRUE == use_igf)
{
// Enable the glitch filter.
gpio_port->gfers = 1 << (pin & 0x1F);
}
else
{
// Disable the glitch filter.
gpio_port->gferc = 1 << (pin & 0x1F);
}
// Configure the edge detector.
return(gpio_configure_edge_detector(pin, mode));
}
#endif
//! @}

966
src/platform/avr32/gpio.h
View File

@ -1,381 +1,587 @@
/* This header file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief GPIO header for AVR32 UC3.
*
* This file contains basic GPIO driver functions.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a GPIO module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GPIO_H_
#define _GPIO_H_
#include <avr32/io.h>
#include "compiler.h"
/*! \name Return Values of the GPIO API
*/
//! @{
#define GPIO_SUCCESS 0 //!< Function successfully completed.
#define GPIO_INVALID_ARGUMENT 1 //!< Input parameters are out of range.
//! @}
/*! \name Interrupt Trigger Modes
*/
//! @{
#define GPIO_PIN_CHANGE 0 //!< Interrupt triggered upon pin change.
#define GPIO_RISING_EDGE 1 //!< Interrupt triggered upon rising edge.
#define GPIO_FALLING_EDGE 2 //!< Interrupt triggered upon falling edge.
//! @}
//! A type definition of pins and modules connectivity.
typedef struct
{
unsigned char pin; //!< Module pin.
unsigned char function; //!< Module function.
} gpio_map_t[];
/*! \name Peripheral Bus Interface
*
* Low-speed interface with a non-deterministic number of clock cycles per
* access.
*
* This interface operates with lower clock frequencies (fPB <= fCPU), and its
* timing is not deterministic since it needs to access a shared bus which may
* be heavily loaded.
*
* \note This interface is immediately available without initialization.
*/
//! @{
/*! \brief Enables specific module modes for a set of pins.
*
* \param gpiomap The pin map.
* \param size The number of pins in \a gpiomap.
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
extern int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size);
/*! \brief Enables a specific module mode for a pin.
*
* \param pin The pin number.\n
* Refer to the product header file `uc3x.h' (where x is the part
* number; e.g. x = a0512) for module pins. E.g., to enable a PWM
* channel output, the pin number can be AVR32_PWM_3_PIN for PWM
* channel 3.
* \param function The pin function.\n
* Refer to the product header file `uc3x.h' (where x is the
* part number; e.g. x = a0512) for module pin functions. E.g.,
* to enable a PWM channel output, the pin function can be
* AVR32_PWM_3_FUNCTION for PWM channel 3.
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
extern int gpio_enable_module_pin(unsigned int pin, unsigned int function);
/*! \brief Enables the GPIO mode of a set of pins.
*
* \param gpiomap The pin map.
* \param size The number of pins in \a gpiomap.
*/
extern void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size);
/*! \brief Enables the GPIO mode of a pin.
*
* \param pin The pin number.\n
* Refer to the product header file `uc3x.h' (where x is the part
* number; e.g. x = a0512) for pin definitions. E.g., to enable the
* GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as
* AVR32_PWM_3_PIN for PWM channel 3 can also be used to release
* module pins for GPIO.
*/
extern void gpio_enable_gpio_pin(unsigned int pin);
/*! \brief Enables the open-drain mode of a pin.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_open_drain(unsigned int pin);
/*! \brief Disables the open-drain mode of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_open_drain(unsigned int pin);
/*! \brief Enables the pull-up resistor of a pin.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_pull_up(unsigned int pin);
/*! \brief Disables the pull-up resistor of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_pull_up(unsigned int pin);
/*! \brief Returns the value of a pin.
*
* \param pin The pin number.
*
* \return The pin value.
*/
extern int gpio_get_pin_value(unsigned int pin);
/*! \brief Returns the output value set for a GPIO pin.
*
* \param pin The pin number.
*
* \return The pin output value.
*/
extern int gpio_get_gpio_pin_output_value(unsigned int pin);
/*! \brief Drives a GPIO pin to 1.
*
* \param pin The pin number.
*/
extern void gpio_set_gpio_pin(unsigned int pin);
/*! \brief Drives a GPIO pin to 0.
*
* \param pin The pin number.
*/
extern void gpio_clr_gpio_pin(unsigned int pin);
/*! \brief Toggles a GPIO pin.
*
* \param pin The pin number.
*/
extern void gpio_tgl_gpio_pin(unsigned int pin);
/*! \brief Enables the glitch filter of a pin.
*
* When the glitch filter is enabled, a glitch with duration of less than 1
* clock cycle is automatically rejected, while a pulse with duration of 2 clock
* cycles or more is accepted. For pulse durations between 1 clock cycle and 2
* clock cycles, the pulse may or may not be taken into account, depending on
* the precise timing of its occurrence. Thus for a pulse to be guaranteed
* visible it must exceed 2 clock cycles, whereas for a glitch to be reliably
* filtered out, its duration must not exceed 1 clock cycle. The filter
* introduces 2 clock cycles latency.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_glitch_filter(unsigned int pin);
/*! \brief Disables the glitch filter of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_glitch_filter(unsigned int pin);
/*! \brief Enables the interrupt of a pin with the specified settings.
*
* \param pin The pin number.
* \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or
* \ref GPIO_FALLING_EDGE).
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
extern int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode);
/*! \brief Disables the interrupt of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_interrupt(unsigned int pin);
/*! \brief Gets the interrupt flag of a pin.
*
* \param pin The pin number.
*
* \return The pin interrupt flag.
*/
extern int gpio_get_pin_interrupt_flag(unsigned int pin);
/*! \brief Clears the interrupt flag of a pin.
*
* \param pin The pin number.
*/
extern void gpio_clear_pin_interrupt_flag(unsigned int pin);
//! @}
/*! \name Local Bus Interface
*
* High-speed interface with only one clock cycle per access.
*
* This interface operates with high clock frequency (fCPU), and its timing is
* deterministic since it does not need to access a shared bus which may be
* heavily loaded.
*
* \note This interface has to be initialized in order to be available.
*/
//! @{
/*! \brief Enables the local bus interface for GPIO.
*
* \note This function must have been called at least once before using other
* functions in this interface.
*/
#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_init(void)
{
Set_system_register(AVR32_CPUCR,
Get_system_register(AVR32_CPUCR) | AVR32_CPUCR_LOCEN_MASK);
}
/*! \brief Enables the output driver of a pin.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_enable_pin_output_driver(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);
}
/*! \brief Disables the output driver of a pin.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*/
#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_disable_pin_output_driver(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);
}
/*! \brief Returns the value of a pin.
*
* \param pin The pin number.
*
* \return The pin value.
*
* \note \ref gpio_local_init must have been called beforehand.
*/
#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ int gpio_local_get_pin_value(unsigned int pin)
{
return (AVR32_GPIO_LOCAL.port[pin >> 5].pvr >> (pin & 0x1F)) & 1;
}
/*! \brief Drives a GPIO pin to 1.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin nor its output
* driver. \ref gpio_enable_gpio_pin and
* \ref gpio_local_enable_pin_output_driver can be called for this
* purpose.
*/
#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_set_gpio_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrs = 1 << (pin & 0x1F);
}
/*! \brief Drives a GPIO pin to 0.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin nor its output
* driver. \ref gpio_enable_gpio_pin and
* \ref gpio_local_enable_pin_output_driver can be called for this
* purpose.
*/
#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_clr_gpio_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);
}
/*! \brief Toggles a GPIO pin.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin nor its output
* driver. \ref gpio_enable_gpio_pin and
* \ref gpio_local_enable_pin_output_driver can be called for this
* purpose.
*/
#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_tgl_gpio_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrt = 1 << (pin & 0x1F);
}
//! @}
#endif // _GPIO_H_
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief GPIO header for AVR32 UC3.
*
* This file contains basic GPIO driver functions.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a GPIO module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _GPIO_H_
#define _GPIO_H_
#include <avr32/io.h>
#include "compiler.h"
/*! \name Return Values of the GPIO API
*/
//! @{
#define GPIO_SUCCESS 0 //!< Function successfully completed.
#define GPIO_INVALID_ARGUMENT 1 //!< Input parameters are out of range.
//! @}
/*! \name Interrupt Trigger Modes
*/
//! @{
#define GPIO_PIN_CHANGE 0 //!< Interrupt triggered upon pin change.
#define GPIO_RISING_EDGE 1 //!< Interrupt triggered upon rising edge.
#define GPIO_FALLING_EDGE 2 //!< Interrupt triggered upon falling edge.
//! @}
//! A type definition of pins and modules connectivity.
typedef struct
{
unsigned char pin; //!< Module pin.
unsigned char function; //!< Module function.
} gpio_map_t[];
/*! \name Peripheral Bus Interface
*
* Low-speed interface with a non-deterministic number of clock cycles per
* access.
*
* This interface operates with lower clock frequencies (fPB <= fCPU), and its
* timing is not deterministic since it needs to access a shared bus which may
* be heavily loaded.
*
* \note This interface is immediately available without initialization.
*/
//! @{
/*! \brief Enables specific module modes for a set of pins.
*
* \param gpiomap The pin map.
* \param size The number of pins in \a gpiomap.
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
extern int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size);
/*! \brief Enables a specific module mode for a pin.
*
* \param pin The pin number.\n
* Refer to the product header file `uc3x.h' (where x is the part
* number; e.g. x = a0512) for module pins. E.g., to enable a PWM
* channel output, the pin number can be AVR32_PWM_3_PIN for PWM
* channel 3.
* \param function The pin function.\n
* Refer to the product header file `uc3x.h' (where x is the
* part number; e.g. x = a0512) for module pin functions. E.g.,
* to enable a PWM channel output, the pin function can be
* AVR32_PWM_3_FUNCTION for PWM channel 3.
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
extern int gpio_enable_module_pin(unsigned int pin, unsigned int function);
/*! \brief Enables the GPIO mode of a set of pins.
*
* \param gpiomap The pin map.
* \param size The number of pins in \a gpiomap.
*/
extern void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size);
/*! \brief Enables the GPIO mode of a pin.
*
* \param pin The pin number.\n
* Refer to the product header file `uc3x.h' (where x is the part
* number; e.g. x = a0512) for pin definitions. E.g., to enable the
* GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as
* AVR32_PWM_3_PIN for PWM channel 3 can also be used to release
* module pins for GPIO.
*/
extern void gpio_enable_gpio_pin(unsigned int pin);
// The open-drain mode is not synthesized on the current AVR32 products.
// If one day some AVR32 products have this feature, the corresponding part
// numbers should be listed in the #if below.
// Note that other functions are available in this driver to use pins with open
// drain in GPIO mode. The advantage of the open-drain mode functions over these
// other functions is that they can be used not only in GPIO mode but also in
// module mode.
#if 0
/*! \brief Enables the open-drain mode of a pin.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_open_drain(unsigned int pin);
/*! \brief Disables the open-drain mode of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_open_drain(unsigned int pin);
#endif
/*! \brief Enables the pull-up resistor of a pin.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_pull_up(unsigned int pin);
/*! \brief Disables the pull-up resistor of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_pull_up(unsigned int pin);
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control.
/*! \brief Enables the pull-down resistor of a pin.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_pull_down(unsigned int pin);
/*! \brief Disables the pull-down resistor of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_pull_down(unsigned int pin);
/*! \brief Enables the buskeeper functionality on a pin.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_buskeeper(unsigned int pin);
/*! \brief Disables the buskeeper functionality on a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_buskeeper(unsigned int pin);
#endif
/*! \brief Returns the value of a pin.
*
* \param pin The pin number.
*
* \return The pin value.
*/
extern int gpio_get_pin_value(unsigned int pin);
/*! \brief Returns the output value set for a GPIO pin.
*
* \param pin The pin number.
*
* \return The pin output value.
*
* \note This function must be used in conjunction with \ref gpio_set_gpio_pin,
* \ref gpio_clr_gpio_pin and \ref gpio_tgl_gpio_pin.
*/
extern int gpio_get_gpio_pin_output_value(unsigned int pin);
/*! \brief Returns the output value set for a GPIO pin using open drain.
*
* \param pin The pin number.
*
* \return The pin output value.
*
* \note This function must be used in conjunction with
* \ref gpio_set_gpio_open_drain_pin, \ref gpio_clr_gpio_open_drain_pin
* and \ref gpio_tgl_gpio_open_drain_pin.
*/
extern int gpio_get_gpio_open_drain_pin_output_value(unsigned int pin);
/*! \brief Drives a GPIO pin to 1.
*
* \param pin The pin number.
*/
extern void gpio_set_gpio_pin(unsigned int pin);
/*! \brief Drives a GPIO pin to 0.
*
* \param pin The pin number.
*/
extern void gpio_clr_gpio_pin(unsigned int pin);
/*! \brief Toggles a GPIO pin.
*
* \param pin The pin number.
*/
extern void gpio_tgl_gpio_pin(unsigned int pin);
/*! \brief Drives a GPIO pin to 1 using open drain.
*
* \param pin The pin number.
*/
extern void gpio_set_gpio_open_drain_pin(unsigned int pin);
/*! \brief Drives a GPIO pin to 0 using open drain.
*
* \param pin The pin number.
*/
extern void gpio_clr_gpio_open_drain_pin(unsigned int pin);
/*! \brief Toggles a GPIO pin using open drain.
*
* \param pin The pin number.
*/
extern void gpio_tgl_gpio_open_drain_pin(unsigned int pin);
/*! \brief Enables the glitch filter of a pin.
*
* When the glitch filter is enabled, a glitch with duration of less than 1
* clock cycle is automatically rejected, while a pulse with duration of 2 clock
* cycles or more is accepted. For pulse durations between 1 clock cycle and 2
* clock cycles, the pulse may or may not be taken into account, depending on
* the precise timing of its occurrence. Thus for a pulse to be guaranteed
* visible it must exceed 2 clock cycles, whereas for a glitch to be reliably
* filtered out, its duration must not exceed 1 clock cycle. The filter
* introduces 2 clock cycles latency.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_glitch_filter(unsigned int pin);
/*! \brief Disables the glitch filter of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_glitch_filter(unsigned int pin);
/*! \brief Enables the interrupt of a pin with the specified settings.
*
* \param pin The pin number.
* \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or
* \ref GPIO_FALLING_EDGE).
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
extern int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode);
/*! \brief Disables the interrupt of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_interrupt(unsigned int pin);
/*! \brief Gets the interrupt flag of a pin.
*
* \param pin The pin number.
*
* \return The pin interrupt flag.
*/
extern int gpio_get_pin_interrupt_flag(unsigned int pin);
/*! \brief Clears the interrupt flag of a pin.
*
* \param pin The pin number.
*/
extern void gpio_clear_pin_interrupt_flag(unsigned int pin);
//! @}
/*! \name Local Bus Interface
*
* High-speed interface with only one clock cycle per access.
*
* This interface operates with high clock frequency (fCPU), and its timing is
* deterministic since it does not need to access a shared bus which may be
* heavily loaded.
*
* \warning To use this interface, the clock frequency of the peripheral bus on
* which the GPIO peripheral is connected must be set to the CPU clock
* frequency (fPB = fCPU).
*
* \note This interface has to be initialized in order to be available.
*/
//! @{
/*! \brief Enables the local bus interface for GPIO.
*
* \note This function must have been called at least once before using other
* functions in this interface.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_init(void)
{
Set_system_register(AVR32_CPUCR,
Get_system_register(AVR32_CPUCR) | AVR32_CPUCR_LOCEN_MASK);
}
/*! \brief Enables the output driver of a pin.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_enable_pin_output_driver(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);
}
/*! \brief Disables the output driver of a pin.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_disable_pin_output_driver(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);
}
/*! \brief Returns the value of a pin.
*
* \param pin The pin number.
*
* \return The pin value.
*
* \note \ref gpio_local_init must have been called beforehand.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ int gpio_local_get_pin_value(unsigned int pin)
{
return (AVR32_GPIO_LOCAL.port[pin >> 5].pvr >> (pin & 0x1F)) & 1;
}
/*! \brief Drives a GPIO pin to 1.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin nor its output
* driver. \ref gpio_enable_gpio_pin and
* \ref gpio_local_enable_pin_output_driver can be called for this
* purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_set_gpio_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrs = 1 << (pin & 0x1F);
}
/*! \brief Drives a GPIO pin to 0.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin nor its output
* driver. \ref gpio_enable_gpio_pin and
* \ref gpio_local_enable_pin_output_driver can be called for this
* purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_clr_gpio_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);
}
/*! \brief Toggles a GPIO pin.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin nor its output
* driver. \ref gpio_enable_gpio_pin and
* \ref gpio_local_enable_pin_output_driver can be called for this
* purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_tgl_gpio_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrt = 1 << (pin & 0x1F);
}
/*! \brief Initializes the configuration of a GPIO pin so that it can be used
* with GPIO open-drain functions.
*
* \note This function must have been called at least once before using
* \ref gpio_local_set_gpio_open_drain_pin,
* \ref gpio_local_clr_gpio_open_drain_pin or
* \ref gpio_local_tgl_gpio_open_drain_pin.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_init_gpio_open_drain_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);
}
/*! \brief Drives a GPIO pin to 1 using open drain.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
* have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_set_gpio_open_drain_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);
}
/*! \brief Drives a GPIO pin to 0 using open drain.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
* have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_clr_gpio_open_drain_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);
}
/*! \brief Toggles a GPIO pin using open drain.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
* have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_tgl_gpio_open_drain_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].odert = 1 << (pin & 0x1F);
}
//! @}
#if (((defined __GNUC__) && ((defined __AVR32_UC3L016__) || \
(defined __AVR32_UC3L032__) || \
(defined __AVR32_UC3L064__)) \
||(defined __ICCAVR32__) && ((defined __AT32UC3L016__) || \
(defined __AT32UC3L032__) || \
(defined __AT32UC3L064__) )))
//! @{
/*! \name Peripheral Event System support
*
* The GPIO can be programmed to output peripheral events whenever an interrupt
* condition is detected, such as pin value change, or only when a rising or
* falling edge is detected.
*
*/
/*! \brief Enables the peripheral event generation of a pin.
*
* \param pin The pin number.
*
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_enable_pin_periph_event(unsigned int pin)
{
AVR32_GPIO.port[pin >> 5].oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin.
AVR32_GPIO.port[pin >> 5].evers = 1 << (pin & 0x1F);
}
/*! \brief Disables the peripheral event generation of a pin.
*
* \param pin The pin number.
*
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_disable_pin_periph_event(unsigned int pin)
{
AVR32_GPIO.port[pin >> 5].everc = 1 << (pin & 0x1F);
}
/*! \brief Configure the peripheral event trigger mode of a pin
*
* \param pin The pin number.
* \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or
* \ref GPIO_FALLING_EDGE).
* \param use_igf use the Input Glitch Filter (TRUE) or not (FALSE).
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
extern int gpio_configure_pin_periph_event_mode(unsigned int pin, unsigned int mode, unsigned int use_igf);
//! @}
#endif
#endif // _GPIO_H_

414
src/platform/avr32/intc.c
View File

@ -1,202 +1,214 @@
/* This source file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief INTC driver for AVR32 UC3.
*
* AVR32 Interrupt Controller driver module.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"
#include "intc.h"
//! Values to store in the interrupt priority registers for the various interrupt priority levels.
extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];
//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.
//! Each line handler table contains a set of pointers to interrupt handlers.
#if __GNUC__
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
#elif __ICCAVR32__
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
#endif
MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
#undef DECL_INT_LINE_HANDLER_TABLE
//! Table containing for each interrupt group the number of interrupt request
//! lines and a pointer to the table of interrupt line handlers.
static const struct
{
unsigned int num_irqs;
volatile __int_handler *_int_line_handler_table;
} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
{
#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
{AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
#undef INSERT_INT_LINE_HANDLER_TABLE
};
/*! \brief Default interrupt handler.
*
* \note Taken and adapted from Newlib.
*/
#if __GNUC__
__attribute__((__interrupt__))
#elif __ICCAVR32__
__interrupt
#endif
static void _unhandled_interrupt(void)
{
// Catch unregistered interrupts.
while (TRUE);
}
/*! \brief Gets the interrupt handler of the current event at the \a int_lev
* interrupt priority level (called from exception.S).
*
* \param int_lev Interrupt priority level to handle.
*
* \return Interrupt handler to execute.
*
* \note Taken and adapted from Newlib.
*/
__int_handler _get_interrupt_handler(unsigned int int_lev)
{
// ICR3 is mapped first, ICR0 last.
// Code in exception.S puts int_lev in R12 which is used by AVR32-GCC to pass
// a single argument to a function.
unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_lev];
unsigned int int_req = AVR32_INTC.irr[int_grp];
// As an interrupt may disappear while it is being fetched by the CPU
// (spurious interrupt caused by a delayed response from an MCU peripheral to
// an interrupt flag clear or interrupt disable instruction), check if there
// are remaining interrupt lines to process.
// If a spurious interrupt occurs, the status register (SR) contains an
// execution mode and interrupt level masks corresponding to a level 0
// interrupt, whatever the interrupt priority level causing the spurious
// event. This behavior has been chosen because a spurious interrupt has not
// to be a priority one and because it may not cause any trouble to other
// interrupts.
// However, these spurious interrupts place the hardware in an unstable state
// and could give problems in other/future versions of the CPU, so the
// software has to be written so that they never occur. The only safe way of
// achieving this is to always clear or disable peripheral interrupts with the
// following sequence:
// 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
// 2: Perform the bus access to the peripheral register that clears or
// disables the interrupt.
// 3: Wait until the interrupt has actually been cleared or disabled by the
// peripheral. This is usually performed by reading from a register in the
// same peripheral (it DOES NOT have to be the same register that was
// accessed in step 2, but it MUST be in the same peripheral), what takes
// bus system latencies into account, but peripheral internal latencies
// (generally 0 cycle) also have to be considered.
// 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
// Note that steps 1 and 4 are useless inside interrupt handlers as the
// corresponding interrupt level is automatically masked by IxM (unless IxM is
// explicitly cleared by the software).
//
// Get the right IRQ handler.
//
// If several interrupt lines are active in the group, the interrupt line with
// the highest number is selected. This is to be coherent with the
// prioritization of interrupt groups performed by the hardware interrupt
// controller.
//
// If no handler has been registered for the pending interrupt,
// _unhandled_interrupt will be selected thanks to the initialization of
// _int_line_handler_table_x by INTC_init_interrupts.
//
// exception.S will provide the interrupt handler with a clean interrupt stack
// frame, with nothing more pushed onto the stack. The interrupt handler must
// manage the `rete' instruction, what can be done thanks to pure assembly,
// inline assembly or the `__attribute__((__interrupt__))' C function
// attribute.
return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;
}
void INTC_init_interrupts(void)
{
unsigned int int_grp, int_req;
// For all interrupt groups,
for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
{
// For all interrupt request lines of each group,
for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)
{
// Assign _unhandled_interrupt as default interrupt handler.
_int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;
}
// Set the interrupt group priority register to its default value.
// By default, all interrupt groups are linked to the interrupt priority
// level 0 and to the interrupt vector _int0.
AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0];
}
}
void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev)
{
// Determine the group of the IRQ.
unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
// Store in _int_line_handler_table_x the pointer to the interrupt handler, so
// that _get_interrupt_handler can retrieve it when the interrupt is vectored.
_int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;
// Program the corresponding IPRX register to set the interrupt priority level
// and the interrupt vector offset that will be fetched by the core interrupt
// system.
// NOTE: The _intx functions are intermediate assembly functions between the
// core interrupt system and the user interrupt handler.
AVR32_INTC.ipr[int_grp] = ipr_val[int_lev & (AVR32_INTC_IPR_INTLEV_MASK >> AVR32_INTC_IPR_INTLEV_OFFSET)];
}
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief INTC driver for AVR32 UC3.
*
* AVR32 Interrupt Controller driver module.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"
#include "intc.h"
// define _evba from exception.S
extern void _evba;
//! Values to store in the interrupt priority registers for the various interrupt priority levels.
extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];
//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.
//! Each line handler table contains a set of pointers to interrupt handlers.
#if (defined __GNUC__)
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
#elif (defined __ICCAVR32__)
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
#endif
MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
#undef DECL_INT_LINE_HANDLER_TABLE
//! Table containing for each interrupt group the number of interrupt request
//! lines and a pointer to the table of interrupt line handlers.
static const struct
{
unsigned int num_irqs;
volatile __int_handler *_int_line_handler_table;
} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
{
#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
{AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
#undef INSERT_INT_LINE_HANDLER_TABLE
};
/*! \brief Default interrupt handler.
*
* \note Taken and adapted from Newlib.
*/
#if (defined __GNUC__)
__attribute__((__interrupt__))
#elif (defined __ICCAVR32__)
__interrupt
#endif
static void _unhandled_interrupt(void)
{
// Catch unregistered interrupts.
while (TRUE);
}
/*! \brief Gets the interrupt handler of the current event at the \a int_level
* interrupt priority level (called from exception.S).
*
* \param int_level Interrupt priority level to handle.
*
* \return Interrupt handler to execute.
*
* \note Taken and adapted from Newlib.
*/
__int_handler _get_interrupt_handler(unsigned int int_level)
{
// ICR3 is mapped first, ICR0 last.
// Code in exception.S puts int_level in R12 which is used by AVR32-GCC to
// pass a single argument to a function.
unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level];
unsigned int int_req = AVR32_INTC.irr[int_grp];
// As an interrupt may disappear while it is being fetched by the CPU
// (spurious interrupt caused by a delayed response from an MCU peripheral to
// an interrupt flag clear or interrupt disable instruction), check if there
// are remaining interrupt lines to process.
// If a spurious interrupt occurs, the status register (SR) contains an
// execution mode and interrupt level masks corresponding to a level 0
// interrupt, whatever the interrupt priority level causing the spurious
// event. This behavior has been chosen because a spurious interrupt has not
// to be a priority one and because it may not cause any trouble to other
// interrupts.
// However, these spurious interrupts place the hardware in an unstable state
// and could give problems in other/future versions of the CPU, so the
// software has to be written so that they never occur. The only safe way of
// achieving this is to always clear or disable peripheral interrupts with the
// following sequence:
// 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
// 2: Perform the bus access to the peripheral register that clears or
// disables the interrupt.
// 3: Wait until the interrupt has actually been cleared or disabled by the
// peripheral. This is usually performed by reading from a register in the
// same peripheral (it DOES NOT have to be the same register that was
// accessed in step 2, but it MUST be in the same peripheral), what takes
// bus system latencies into account, but peripheral internal latencies
// (generally 0 cycle) also have to be considered.
// 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
// Note that steps 1 and 4 are useless inside interrupt handlers as the
// corresponding interrupt level is automatically masked by IxM (unless IxM is
// explicitly cleared by the software).
//
// Get the right IRQ handler.
//
// If several interrupt lines are active in the group, the interrupt line with
// the highest number is selected. This is to be coherent with the
// prioritization of interrupt groups performed by the hardware interrupt
// controller.
//
// If no handler has been registered for the pending interrupt,
// _unhandled_interrupt will be selected thanks to the initialization of
// _int_line_handler_table_x by INTC_init_interrupts.
//
// exception.S will provide the interrupt handler with a clean interrupt stack
// frame, with nothing more pushed onto the stack. The interrupt handler must
// manage the `rete' instruction, what can be done thanks to pure assembly,
// inline assembly or the `__attribute__((__interrupt__))' C function
// attribute.
return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;
}
//! Init EVBA address. This sequence might also be done in the UTILS/STARTUP/GCC/crt0.S
static __inline__ void INTC_init_evba(void)
{
Set_system_register(AVR32_EVBA, (int)&_evba );
}
void INTC_init_interrupts(void)
{
unsigned int int_grp, int_req;
INTC_init_evba();
// For all interrupt groups,
for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
{
// For all interrupt request lines of each group,
for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)
{
// Assign _unhandled_interrupt as default interrupt handler.
_int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;
}
// Set the interrupt group priority register to its default value.
// By default, all interrupt groups are linked to the interrupt priority
// level 0 and to the interrupt vector _int0.
AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0];
}
}
void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level)
{
// Determine the group of the IRQ.
unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
// Store in _int_line_handler_table_x the pointer to the interrupt handler, so
// that _get_interrupt_handler can retrieve it when the interrupt is vectored.
_int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;
// Program the corresponding IPRX register to set the interrupt priority level
// and the interrupt vector offset that will be fetched by the core interrupt
// system.
// NOTE: The _intx functions are intermediate assembly functions between the
// core interrupt system and the user interrupt handler.
AVR32_INTC.ipr[int_grp] = ipr_val[int_level & (AVR32_INTC_IPR_INTLEVEL_MASK >> AVR32_INTC_IPR_INTLEVEL_OFFSET)];
}

195
src/platform/avr32/intc.h
View File

@ -1,97 +1,100 @@
/* This header file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief INTC driver for AVR32 UC3.
*
* AVR32 Interrupt Controller driver module.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _INTC_H_
#define _INTC_H_
#include "compiler.h"
//! Maximal number of interrupt request lines per group.
#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP 32
//! Number of interrupt priority levels.
#define AVR32_INTC_NUM_INT_LEVELS (1 << AVR32_INTC_IPR_INTLEV_SIZE)
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
//! Pointer to interrupt handler.
#if __GNUC__
typedef void (*__int_handler)(void);
#elif __ICCAVR32__
typedef void (__interrupt *__int_handler)(void);
#endif
/*! \brief Initializes the hardware interrupt controller driver.
*
* \note Taken and adapted from Newlib.
*/
extern void INTC_init_interrupts(void);
/*! \brief Registers an interrupt handler.
*
* \param handler Interrupt handler to register.
* \param irq IRQ of the interrupt handler to register.
* \param int_lev Interrupt priority level to assign to the group of this IRQ.
*
* \warning The interrupt handler must manage the `rete' instruction, what can
* be done thanks to pure assembly, inline assembly or the
* `__attribute__((__interrupt__))' C function attribute.
*
* \warning If several interrupt handlers of a same group are registered with
* different priority levels, only the latest priority level set will
* be effective.
*
* \note Taken and adapted from Newlib.
*/
extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev);
#endif // __AVR32_ABI_COMPILER__
#endif // _INTC_H_
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief INTC driver for AVR32 UC3.
*
* AVR32 Interrupt Controller driver module.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _INTC_H_
#define _INTC_H_
#include "compiler.h"
//! Maximal number of interrupt request lines per group.
#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP 32
//! Number of interrupt priority levels.
#define AVR32_INTC_NUM_INT_LEVELS (1 << AVR32_INTC_IPR_INTLEVEL_SIZE)
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
//! Pointer to interrupt handler.
#if (defined __GNUC__)
typedef void (*__int_handler)(void);
#elif (defined __ICCAVR32__)
typedef void (__interrupt *__int_handler)(void);
#endif
/*! \brief Initializes the hardware interrupt controller driver.
*
* \note Taken and adapted from Newlib.
*/
extern void INTC_init_interrupts(void);
/*! \brief Registers an interrupt handler.
*
* \param handler Interrupt handler to register.
* \param irq IRQ of the interrupt handler to register.
* \param int_level Interrupt priority level to assign to the group of this IRQ.
*
* \warning The interrupt handler must manage the `rete' instruction, what can
* be done thanks to pure assembly, inline assembly or the
* `__attribute__((__interrupt__))' C function attribute.
*
* \warning If several interrupt handlers of a same group are registered with
* different priority levels, only the latest priority level set will
* be effective.
*
* \note Taken and adapted from Newlib.
*/
extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level);
#endif // __AVR32_ABI_COMPILER__
#endif // _INTC_H_

651
src/platform/avr32/mrepeat.h
View File

@ -1,325 +1,328 @@
/* This header file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor macro repeating utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MREPEAT_H_
#define _MREPEAT_H_
#include "preprocessor.h"
//! Maximal number of repetitions supported by MREPEAT.
#define MREPEAT_LIMIT 256
/*! \brief Macro repeat.
*
* This macro represents a horizontal repetition construct.
*
* \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.
* \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with
* the current repetition number and the auxiliary data argument.
* \param data Auxiliary data passed to macro.
*
* \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>
*/
#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data)
#define MREPEAT0( macro, data)
#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)
#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)
#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)
#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)
#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)
#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)
#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)
#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)
#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)
#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)
#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)
#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)
#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)
#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)
#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)
#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)
#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)
#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)
#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)
#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)
#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)
#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)
#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)
#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)
#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)
#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)
#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)
#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)
#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)
#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)
#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)
#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)
#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)
#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)
#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)
#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)
#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)
#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)
#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)
#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)
#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)
#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)
#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)
#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)
#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)
#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)
#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)
#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)
#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)
#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)
#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)
#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)
#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)
#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)
#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)
#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)
#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)
#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)
#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)
#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)
#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)
#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)
#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)
#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)
#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)
#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)
#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)
#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)
#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)
#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)
#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)
#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)
#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)
#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)
#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)
#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)
#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)
#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)
#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)
#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)
#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)
#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)
#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)
#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)
#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)
#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)
#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)
#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)
#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)
#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)
#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)
#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)
#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)
#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)
#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)
#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)
#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)
#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)
#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)
#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)
#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)
#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)
#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)
#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)
#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)
#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)
#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)
#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)
#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)
#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)
#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)
#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)
#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)
#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)
#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)
#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)
#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)
#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)
#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)
#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)
#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)
#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)
#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)
#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)
#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)
#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)
#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)
#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)
#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)
#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)
#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)
#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)
#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)
#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)
#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)
#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)
#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)
#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)
#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)
#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)
#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)
#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)
#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)
#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)
#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)
#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)
#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)
#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)
#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)
#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)
#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)
#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)
#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)
#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)
#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)
#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)
#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)
#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)
#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)
#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)
#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)
#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)
#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)
#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)
#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)
#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)
#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)
#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)
#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)
#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)
#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)
#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)
#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)
#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)
#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)
#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)
#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)
#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)
#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)
#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)
#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)
#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)
#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)
#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)
#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)
#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)
#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)
#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)
#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)
#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)
#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)
#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)
#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)
#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)
#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)
#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)
#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)
#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)
#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)
#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)
#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)
#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)
#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)
#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)
#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)
#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)
#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)
#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)
#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)
#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)
#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)
#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)
#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)
#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)
#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)
#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)
#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)
#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)
#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)
#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)
#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)
#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)
#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)
#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)
#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)
#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)
#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)
#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)
#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)
#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)
#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)
#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)
#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)
#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)
#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)
#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)
#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)
#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)
#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)
#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)
#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)
#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)
#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)
#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)
#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)
#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)
#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)
#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)
#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)
#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)
#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)
#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)
#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)
#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)
#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)
#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)
#endif // _MREPEAT_H_
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor macro repeating utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _MREPEAT_H_
#define _MREPEAT_H_
#include "preprocessor.h"
//! Maximal number of repetitions supported by MREPEAT.
#define MREPEAT_LIMIT 256
/*! \brief Macro repeat.
*
* This macro represents a horizontal repetition construct.
*
* \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.
* \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with
* the current repetition number and the auxiliary data argument.
* \param data Auxiliary data passed to macro.
*
* \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>
*/
#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data)
#define MREPEAT0( macro, data)
#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)
#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)
#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)
#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)
#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)
#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)
#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)
#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)
#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)
#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)
#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)
#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)
#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)
#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)
#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)
#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)
#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)
#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)
#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)
#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)
#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)
#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)
#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)
#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)
#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)
#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)
#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)
#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)
#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)
#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)
#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)
#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)
#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)
#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)
#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)
#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)
#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)
#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)
#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)
#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)
#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)
#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)
#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)
#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)
#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)
#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)
#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)
#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)
#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)
#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)
#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)
#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)
#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)
#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)
#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)
#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)
#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)
#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)
#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)
#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)
#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)
#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)
#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)
#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)
#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)
#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)
#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)
#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)
#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)
#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)
#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)
#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)
#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)
#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)
#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)
#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)
#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)
#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)
#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)
#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)
#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)
#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)
#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)
#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)
#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)
#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)
#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)
#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)
#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)
#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)
#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)
#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)
#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)
#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)
#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)
#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)
#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)
#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)
#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)
#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)
#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)
#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)
#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)
#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)
#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)
#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)
#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)
#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)
#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)
#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)
#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)
#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)
#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)
#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)
#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)
#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)
#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)
#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)
#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)
#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)
#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)
#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)
#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)
#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)
#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)
#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)
#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)
#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)
#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)
#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)
#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)
#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)
#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)
#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)
#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)
#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)
#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)
#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)
#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)
#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)
#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)
#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)
#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)
#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)
#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)
#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)
#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)
#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)
#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)
#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)
#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)
#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)
#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)
#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)
#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)
#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)
#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)
#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)
#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)
#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)
#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)
#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)
#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)
#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)
#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)
#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)
#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)
#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)
#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)
#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)
#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)
#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)
#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)
#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)
#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)
#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)
#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)
#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)
#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)
#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)
#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)
#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)
#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)
#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)
#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)
#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)
#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)
#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)
#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)
#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)
#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)
#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)
#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)
#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)
#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)
#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)
#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)
#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)
#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)
#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)
#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)
#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)
#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)
#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)
#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)
#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)
#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)
#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)
#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)
#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)
#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)
#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)
#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)
#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)
#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)
#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)
#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)
#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)
#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)
#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)
#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)
#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)
#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)
#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)
#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)
#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)
#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)
#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)
#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)
#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)
#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)
#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)
#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)
#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)
#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)
#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)
#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)
#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)
#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)
#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)
#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)
#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)
#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)
#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)
#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)
#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)
#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)
#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)
#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)
#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)
#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)
#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)
#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)
#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)
#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)
#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)
#endif // _MREPEAT_H_

1062
src/platform/avr32/pm.c
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src/platform/avr32/pm.h
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/* This header file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Power Manager driver.
*
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _PM_H_
#define _PM_H_
#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"
/*! \brief Sets the MCU in the specified sleep mode.
*
* \param mode Sleep mode:
* \arg \c AVR32_PM_SMODE_IDLE: Idle;
* \arg \c AVR32_PM_SMODE_FROZEN: Frozen;
* \arg \c AVR32_PM_SMODE_STANDBY: Standby;
* \arg \c AVR32_PM_SMODE_STOP: Stop;
* \arg \c AVR32_PM_SMODE_SHUTDOWN: Shutdown (DeepStop);
* \arg \c AVR32_PM_SMODE_STATIC: Static.
*/
#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));}
//! Input and output parameters when initializing PM clocks using pm_configure_clocks().
typedef struct
{
//! CPU frequency (input/output argument).
unsigned long cpu_f;
//! PBA frequency (input/output argument).
unsigned long pba_f;
//! Oscillator 0 frequency (board dependant) (input argument).
unsigned long osc0_f;
//! Oscillator 0 startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument).
unsigned long osc0_startup;
} pm_freq_param_t;
#define PM_FREQ_STATUS_FAIL (-1)
#define PM_FREQ_STATUS_OK (0)
/*! \brief Gets the MCU reset cause.
*
* \param pm Base address of the Power Manager instance (i.e. &AVR32_PM).
*
* \return The MCU reset cause which can be masked with the
* \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.
*/
#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)
{
return pm->rcause;
}
/*!
* \brief This function will enable the external clock mode of the oscillator 0.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the crystal mode of the oscillator 0.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param fosc0 Oscillator 0 crystal frequency (Hz)
*/
extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0);
/*!
* \brief This function will enable the oscillator 0 to be used with a startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will disable the oscillator 0.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_disable_clk0(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the oscillator 0 to be used with no startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 0 startup time, for which the function does not wait. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will wait until the Osc0 clock is ready.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the external clock mode of the oscillator 1.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the crystal mode of the oscillator 1.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param fosc1 Oscillator 1 crystal frequency (Hz)
*/
extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1);
/*!
* \brief This function will enable the oscillator 1 to be used with a startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 1 startup time. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will disable the oscillator 1.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_disable_clk1(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the oscillator 1 to be used with no startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 1 startup time, for which the function does not wait. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will wait until the Osc1 clock is ready.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the external clock mode of the 32-kHz oscillator.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the crystal mode of the 32-kHz oscillator.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the oscillator 32 to be used with a startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 32 kHz startup time. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will disable the oscillator 32.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_disable_clk32(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the oscillator 32 to be used with no startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 32 kHz startup time, for which the function does not wait. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will wait until the osc32 clock is ready.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm);
/*!
* \brief This function will select all the power manager clocks.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pbadiv Peripheral Bus A clock divisor enable
* \param pbasel Peripheral Bus A select
* \param pbbdiv Peripheral Bus B clock divisor enable
* \param pbbsel Peripheral Bus B select
* \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock)
* \param hsbsel High Speed Bus select (CPU clock = HSB clock )
*/
extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel);
/*!
* \brief This function will setup a generic clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gc generic clock number (0 for gc0...)
* \param osc_or_pll Use OSC (=0) or PLL (=1)
* \param pll_osc Select Osc0/PLL0 or Osc1/PLL1
* \param diven Generic clock divisor enable
* \param div Generic clock divisor
*/
extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div);
/*!
* \brief This function will enable a generic clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gc generic clock number (0 for gc0...)
*/
extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc);
/*!
* \brief This function will disable a generic clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gc generic clock number (0 for gc0...)
*/
extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc);
/*!
* \brief This function will setup a PLL.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
* \param mul PLL MUL in the PLL formula
* \param div PLL DIV in the PLL formula
* \param osc OSC number (0 for osc0, 1 for osc1)
* \param lockcount PLL lockount
*/
extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount);
/*!
* \brief This function will set a PLL option.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
* \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
* \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
* \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
*/
extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable);
/*!
* \brief This function will get a PLL option.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
* \return Option
*/
extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll);
/*!
* \brief This function will enable a PLL.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
*/
extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll);
/*!
* \brief This function will disable a PLL.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
*/
extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll);
/*!
* \brief This function will wait for PLL0 locked
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm);
/*!
* \brief This function will wait for PLL1 locked
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm);
/*!
* \brief This function will switch the power manager main clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0.
*/
extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock);
/*!
* \brief Switch main clock to clock Osc0 (crystal mode)
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param fosc0 Oscillator 0 crystal frequency (Hz)
* \param startup Crystal 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
*/
extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup);
/*! \brief Enables the Brown-Out Detector interrupt.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*/
extern void pm_bod_enable_irq(volatile avr32_pm_t *pm);
/*! \brief Disables the Brown-Out Detector interrupt.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*/
extern void pm_bod_disable_irq(volatile avr32_pm_t *pm);
/*! \brief Clears the Brown-Out Detector interrupt flag.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*/
extern void pm_bod_clear_irq(volatile avr32_pm_t *pm);
/*! \brief Gets the Brown-Out Detector interrupt flag.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*
* \retval 0 No BOD interrupt.
* \retval 1 BOD interrupt pending.
*/
extern unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm);
/*! \brief Gets the Brown-Out Detector interrupt enable status.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*
* \retval 0 BOD interrupt disabled.
* \retval 1 BOD interrupt enabled.
*/
extern unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm);
/*! \brief Gets the triggering threshold of the Brown-Out Detector.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*
* \return Triggering threshold of the BOD. See the electrical characteristics
* in the part datasheet for actual voltage levels.
*/
extern unsigned long pm_bod_get_level(volatile avr32_pm_t *pm);
/*!
* \brief Read the content of the PM GPLP registers
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
*
* \return The content of the chosen GPLP register.
*/
extern unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp);
/*!
* \brief Write into the PM GPLP registers
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
* \param value Value to write
*/
extern void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value);
/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks
* according to the user wishes.
*
* This function needs some parameters stored in a pm_freq_param_t structure:
* - cpu_f and pba_f are the wanted frequencies,
* - osc0_f is the oscillator 0 on-board frequency (e.g. FOSC0),
* - osc0_startup is the oscillator 0 startup time (e.g. OSC0_STARTUP).
*
* The function will then configure the clocks using the following rules:
* - It first try to find a valid PLL frequency (the highest possible value to avoid jitter) in order
* to satisfy the CPU frequency,
* - It optimizes the configuration depending the various divide stages,
* - Then, the PBA frequency is configured from the CPU freq (PBA freq = CPU freq/(2 exp x)) so that
* PBA max frequencies is always below 30MHz.
* - Note that HSB and PBB are configured with the same frequency as CPU.
* - Note also that the number of wait states of the flash read accesses is automatically set-up depending
* the CPU frequency. As a consequence, the application needs the FLASHC driver to compile.
*
* The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.
*
* \param param pointer on the configuration structure.
*
* \retval PM_FREQ_STATUS_OK Mode successfully initialized.
* \retval PM_FREQ_STATUS_FAIL The configuration can not be done.
*/
extern int pm_configure_clocks(pm_freq_param_t *param);
/*! \brief Automatically configure the USB clock.
*
* USB clock is configured to 48MHz, using the PLL1 from the Oscillator0, assuming
* a 12 MHz crystal is connected to it.
*/
extern void pm_configure_usb_clock(void);
#endif // _PM_H_
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Power Manager driver.
*
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _PM_H_
#define _PM_H_
#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"
/*! \brief Sets the MCU in the specified sleep mode.
*
* \param mode Sleep mode:
* \arg \c AVR32_PM_SMODE_IDLE: Idle;
* \arg \c AVR32_PM_SMODE_FROZEN: Frozen;
* \arg \c AVR32_PM_SMODE_STANDBY: Standby;
* \arg \c AVR32_PM_SMODE_STOP: Stop;
* \arg \c AVR32_PM_SMODE_DEEP_STOP: DeepStop;
* \arg \c AVR32_PM_SMODE_STATIC: Static.
*/
#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));}
//! Input and output parameters when initializing PM clocks using pm_configure_clocks().
typedef struct
{
//! CPU frequency (input/output argument).
unsigned long cpu_f;
//! PBA frequency (input/output argument).
unsigned long pba_f;
//! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument).
unsigned long osc0_f;
//! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument).
unsigned long osc0_startup;
} pm_freq_param_t;
#define PM_FREQ_STATUS_FAIL (-1)
#define PM_FREQ_STATUS_OK (0)
/*! \brief Gets the MCU reset cause.
*
* \param pm Base address of the Power Manager instance (i.e. &AVR32_PM).
*
* \return The MCU reset cause which can be masked with the
* \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)
{
return pm->rcause;
}
/*!
* \brief This function will enable the external clock mode of the oscillator 0.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the crystal mode of the oscillator 0.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param fosc0 Oscillator 0 crystal frequency (Hz)
*/
extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0);
/*!
* \brief This function will enable the oscillator 0 to be used with a startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will disable the oscillator 0.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_disable_clk0(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the oscillator 0 to be used with no startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 0 startup time, for which the function does not wait. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will wait until the Osc0 clock is ready.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the external clock mode of the oscillator 1.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the crystal mode of the oscillator 1.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param fosc1 Oscillator 1 crystal frequency (Hz)
*/
extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1);
/*!
* \brief This function will enable the oscillator 1 to be used with a startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 1 startup time. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will disable the oscillator 1.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_disable_clk1(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the oscillator 1 to be used with no startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 1 startup time, for which the function does not wait. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will wait until the Osc1 clock is ready.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the external clock mode of the 32-kHz oscillator.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the crystal mode of the 32-kHz oscillator.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the oscillator 32 to be used with a startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 32 kHz startup time. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will disable the oscillator 32.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_disable_clk32(volatile avr32_pm_t *pm);
/*!
* \brief This function will enable the oscillator 32 to be used with no startup time.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param startup Clock 32 kHz startup time, for which the function does not wait. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
*/
extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
/*!
* \brief This function will wait until the osc32 clock is ready.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm);
/*!
* \brief This function will select all the power manager clocks.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pbadiv Peripheral Bus A clock divisor enable
* \param pbasel Peripheral Bus A select
* \param pbbdiv Peripheral Bus B clock divisor enable
* \param pbbsel Peripheral Bus B select
* \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock)
* \param hsbsel High Speed Bus select (CPU clock = HSB clock )
*/
extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel);
/*!
* \brief This function will setup a generic clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gc generic clock number (0 for gc0...)
* \param osc_or_pll Use OSC (=0) or PLL (=1)
* \param pll_osc Select Osc0/PLL0 or Osc1/PLL1
* \param diven Generic clock divisor enable
* \param div Generic clock divisor
*/
extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div);
/*!
* \brief This function will enable a generic clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gc generic clock number (0 for gc0...)
*/
extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc);
/*!
* \brief This function will disable a generic clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gc generic clock number (0 for gc0...)
*/
extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc);
/*!
* \brief This function will setup a PLL.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
* \param mul PLL MUL in the PLL formula
* \param div PLL DIV in the PLL formula
* \param osc OSC number (0 for osc0, 1 for osc1)
* \param lockcount PLL lockount
*/
extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount);
/*!
* \brief This function will set a PLL option.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
* \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
* \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
* \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
*/
extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable);
/*!
* \brief This function will get a PLL option.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
* \return Option
*/
extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll);
/*!
* \brief This function will enable a PLL.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
*/
extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll);
/*!
* \brief This function will disable a PLL.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pll PLL number(0 for PLL0, 1 for PLL1)
*/
extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll);
/*!
* \brief This function will wait for PLL0 locked
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm);
/*!
* \brief This function will wait for PLL1 locked
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
*/
extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm);
/*!
* \brief This function will switch the power manager main clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0.
*/
extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock);
/*!
* \brief Switch main clock to clock Osc0 (crystal mode)
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param fosc0 Oscillator 0 crystal frequency (Hz)
* \param startup Crystal 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
*/
extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup);
/*! \brief Enables the Brown-Out Detector interrupt.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*/
extern void pm_bod_enable_irq(volatile avr32_pm_t *pm);
/*! \brief Disables the Brown-Out Detector interrupt.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*/
extern void pm_bod_disable_irq(volatile avr32_pm_t *pm);
/*! \brief Clears the Brown-Out Detector interrupt flag.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*/
extern void pm_bod_clear_irq(volatile avr32_pm_t *pm);
/*! \brief Gets the Brown-Out Detector interrupt flag.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*
* \retval 0 No BOD interrupt.
* \retval 1 BOD interrupt pending.
*/
extern unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm);
/*! \brief Gets the Brown-Out Detector interrupt enable status.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*
* \retval 0 BOD interrupt disabled.
* \retval 1 BOD interrupt enabled.
*/
extern unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm);
/*! \brief Gets the triggering threshold of the Brown-Out Detector.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
*
* \return Triggering threshold of the BOD. See the electrical characteristics
* in the part datasheet for actual voltage levels.
*/
extern unsigned long pm_bod_get_level(volatile avr32_pm_t *pm);
/*!
* \brief Read the content of the PM GPLP registers
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
*
* \return The content of the chosen GPLP register.
*/
extern unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp);
/*!
* \brief Write into the PM GPLP registers
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
* \param value Value to write
*/
extern void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value);
/*! \brief Enable the clock of a module.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param module The module to clock (use one of the defines in the part-specific
* header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
* clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
*/
extern long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module);
/*! \brief Disable the clock of a module.
*
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param module The module to shut down (use one of the defines in the part-specific
* header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
* clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
*/
extern long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module);
/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks
* according to the user wishes.
*
* This function needs some parameters stored in a pm_freq_param_t structure:
* - cpu_f and pba_f are the wanted frequencies,
* - osc0_f is the oscillator 0 on-board frequency (e.g. FOSC0),
* - osc0_startup is the oscillator 0 startup time (e.g. OSC0_STARTUP).
*
* The function will then configure the clocks using the following rules:
* - It first try to find a valid PLL frequency (the highest possible value to avoid jitter) in order
* to satisfy the CPU frequency,
* - It optimizes the configuration depending the various divide stages,
* - Then, the PBA frequency is configured from the CPU freq.
* - Note that HSB and PBB are configured with the same frequency as CPU.
* - Note also that the number of wait states of the flash read accesses is automatically set-up depending
* the CPU frequency. As a consequence, the application needs the FLASHC driver to compile.
*
* The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.
*
* \param param pointer on the configuration structure.
*
* \retval PM_FREQ_STATUS_OK Mode successfully initialized.
* \retval PM_FREQ_STATUS_FAIL The configuration can not be done.
*/
extern int pm_configure_clocks(pm_freq_param_t *param);
/*! \brief Automatically configure the USB clock.
*
* USB clock is configured to 48MHz, using the PLL1 from the Oscillator0, assuming
* a 12 MHz crystal is connected to it.
*/
extern void pm_configure_usb_clock(void);
#endif // _PM_H_

517
src/platform/avr32/pm_conf_clocks.c
View File

@ -1,247 +1,272 @@
/* This source file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Power Manager clocks configuration helper.
*
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <string.h>
#if __GNUC__
# include <sys/cpu.h>
#endif
#include "compiler.h"
#include "pm.h"
extern void flashc_set_wait_state(unsigned int wait_state);
#define PM_MAX_MUL ((1 << AVR32_PM_PLL0_PLLMUL_SIZE) - 1)
int pm_configure_clocks(pm_freq_param_t *param)
{
// Supported frequencies:
// Fosc0 mul div PLL div2_en cpu_f pba_f Comment
// 12 15 1 192 1 12 12
// 12 9 3 40 1 20 20 PLL out of spec
// 12 15 1 192 1 24 12
// 12 9 1 120 1 30 15
// 12 9 3 40 0 40 20 PLL out of spec
// 12 15 1 192 1 48 12
// 12 15 1 192 1 48 24
// 12 8 1 108 1 54 27
// 12 9 1 120 1 60 15
// 12 9 1 120 1 60 30
// 12 10 1 132 1 66 16.5
//
unsigned long in_cpu_f = param->cpu_f;
unsigned long in_osc0_f = param->osc0_f;
unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
unsigned long pll_freq, rest;
Bool b_div2_pba, b_div2_cpu;
// Switch to external Oscillator 0
pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup);
// Start with CPU freq config
if (in_cpu_f == in_osc0_f)
{
param->cpu_f = in_osc0_f;
param->pba_f = in_osc0_f;
return PM_FREQ_STATUS_OK;
}
else if (in_cpu_f < in_osc0_f)
{
// TBD
}
rest = in_cpu_f % in_osc0_f;
for (div = 1; div < 32; div++)
{
if ((div * rest) % in_osc0_f == 0)
break;
}
if (div == 32)
return PM_FREQ_STATUS_FAIL;
mul = (in_cpu_f * div) / in_osc0_f;
if (mul > PM_MAX_MUL)
return PM_FREQ_STATUS_FAIL;
// export 2power from PLL div to div2_cpu
while (!(div % 2))
{
div /= 2;
div2_cpu++;
}
// Here we know the mul and div parameter of the PLL config.
// . Check out if the PLL has a valid in_cpu_f.
// . Try to have for the PLL frequency (VCO output) the highest possible value
// to reduce jitter.
while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
{
if (2 * mul > PM_MAX_MUL)
break;
mul *= 2;
div2_cpu++;
}
if (div2_cpu != 0)
{
div2_cpu--;
div2_en = 1;
}
pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
// Update real CPU Frequency
param->cpu_f = pll_freq / (1 << div2_cpu);
mul--;
pm_pll_setup(&AVR32_PM
, 0 // pll
, mul // mul
, div // div
, 0 // osc
, 16 // lockcount
);
pm_pll_set_option(&AVR32_PM
, 0 // pll
// PLL clock is lower than 160MHz: need to set pllopt.
, (pll_freq < 160000000) ? 1 : 0 // pll_freq
, div2_en // pll_div2
, 0 // pll_wbwdisable
);
rest = pll_freq;
while (rest > AVR32_PM_PBA_MAX_FREQ ||
rest != param->pba_f)
{
div2_pba++;
rest = pll_freq / (1 << div2_pba);
if (rest < param->pba_f)
break;
}
// Update real PBA Frequency
param->pba_f = pll_freq / (1 << div2_pba);
#if __GNUC__
set_cpu_hz(param->pba_f);
#endif
// Enable PLL0
pm_pll_enable(&AVR32_PM, 0);
// Wait for PLL0 locked
pm_wait_for_pll0_locked(&AVR32_PM);
if (div2_cpu)
{
b_div2_cpu = TRUE;
div2_cpu--;
}
else
b_div2_cpu = FALSE;
if (div2_pba)
{
b_div2_pba = TRUE;
div2_pba--;
}
else
b_div2_pba = FALSE;
pm_cksel(&AVR32_PM
, b_div2_pba, div2_pba // PBA
, b_div2_cpu, div2_cpu // PBB
, b_div2_cpu, div2_cpu // HSB
);
if (param->cpu_f > AVR32_FLASHC_FWS_0_MAX_FREQ)
flashc_set_wait_state(1);
else
flashc_set_wait_state(0);
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
return PM_FREQ_STATUS_OK;
}
void pm_configure_usb_clock(void)
{
volatile avr32_pm_t *pm = &AVR32_PM;
// Set PLL1 @ 96 MHz from Osc0: 12MHz*(7+1)/1 = 96MHz.
// In order to work, we need to go above 80MHz, then divide.
pm_pll_setup(pm, 1, // pll
7, // mul
1, // div
0, // osc
16); // lockcount
pm_pll_set_option(pm, 1, // pll1
1, // Choose the range 80-180MHz.
1, // div2
0); // wbwdisable
// Enable PLL1.
pm_pll_enable(pm, 1);
// Wait for PLL1 locked.
pm_wait_for_pll1_locked(pm);
// Setup USB GCLK.
pm_gc_setup(pm, AVR32_PM_GCLK_USBB, // gc
1, // osc_or_pll: use Osc (if 0) or PLL (if 1)
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
0, // diven
0); // div
// Enable USB GCLK.
pm_gc_enable(pm, AVR32_PM_GCLK_USBB);
}
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Power Manager clocks configuration helper.
*
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#include <string.h>
#include "compiler.h"
#include "pm.h"
extern void flashc_set_wait_state(unsigned int wait_state);
#if (defined AVR32_FLASHC_210_H_INCLUDED)
extern void flashc_issue_command(unsigned int command, int page_number);
#endif
#define PM_MAX_MUL ((1 << AVR32_PM_PLL0_PLLMUL_SIZE) - 1)
int pm_configure_clocks(pm_freq_param_t *param)
{
// Supported frequencies:
// Fosc0 mul div PLL div2_en cpu_f pba_f Comment
// 12 15 1 192 1 12 12
// 12 9 3 40 1 20 20 PLL out of spec
// 12 15 1 192 1 24 12
// 12 9 1 120 1 30 15
// 12 9 3 40 0 40 20 PLL out of spec
// 12 15 1 192 1 48 12
// 12 15 1 192 1 48 24
// 12 8 1 108 1 54 27
// 12 9 1 120 1 60 15
// 12 9 1 120 1 60 30
// 12 10 1 132 1 66 16.5
//
unsigned long in_cpu_f = param->cpu_f;
unsigned long in_osc0_f = param->osc0_f;
unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
unsigned long pll_freq, rest;
Bool b_div2_pba, b_div2_cpu;
// Switch to external Oscillator 0
pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup);
// Start with CPU freq config
if (in_cpu_f == in_osc0_f)
{
param->cpu_f = in_osc0_f;
param->pba_f = in_osc0_f;
return PM_FREQ_STATUS_OK;
}
else if (in_cpu_f < in_osc0_f)
{
// TBD
}
rest = in_cpu_f % in_osc0_f;
for (div = 1; div < 32; div++)
{
if ((div * rest) % in_osc0_f == 0)
break;
}
if (div == 32)
return PM_FREQ_STATUS_FAIL;
mul = (in_cpu_f * div) / in_osc0_f;
if (mul > PM_MAX_MUL)
return PM_FREQ_STATUS_FAIL;
// export 2power from PLL div to div2_cpu
while (!(div % 2))
{
div /= 2;
div2_cpu++;
}
// Here we know the mul and div parameter of the PLL config.
// . Check out if the PLL has a valid in_cpu_f.
// . Try to have for the PLL frequency (VCO output) the highest possible value
// to reduce jitter.
while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
{
if (2 * mul > PM_MAX_MUL)
break;
mul *= 2;
div2_cpu++;
}
if (div2_cpu != 0)
{
div2_cpu--;
div2_en = 1;
}
pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
// Update real CPU Frequency
param->cpu_f = pll_freq / (1 << div2_cpu);
mul--;
pm_pll_setup(&AVR32_PM
, 0 // pll
, mul // mul
, div // div
, 0 // osc
, 16 // lockcount
);
pm_pll_set_option(&AVR32_PM
, 0 // pll
// PLL clock is lower than 160MHz: need to set pllopt.
, (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0 // pll_freq
, div2_en // pll_div2
, 0 // pll_wbwdisable
);
rest = pll_freq;
while (rest > AVR32_PM_PBA_MAX_FREQ ||
rest != param->pba_f)
{
div2_pba++;
rest = pll_freq / (1 << div2_pba);
if (rest < param->pba_f)
break;
}
// Update real PBA Frequency
param->pba_f = pll_freq / (1 << div2_pba);
// Enable PLL0
pm_pll_enable(&AVR32_PM, 0);
// Wait for PLL0 locked
pm_wait_for_pll0_locked(&AVR32_PM);
if (div2_cpu)
{
b_div2_cpu = TRUE;
div2_cpu--;
}
else
b_div2_cpu = FALSE;
if (div2_pba)
{
b_div2_pba = TRUE;
div2_pba--;
}
else
b_div2_pba = FALSE;
pm_cksel(&AVR32_PM
, b_div2_pba, div2_pba // PBA
, b_div2_cpu, div2_cpu // PBB
, b_div2_cpu, div2_cpu // HSB
);
if (param->cpu_f > AVR32_FLASHC_FWS_0_MAX_FREQ)
{
flashc_set_wait_state(1);
#if (defined AVR32_FLASHC_210_H_INCLUDED)
if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ)
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
else
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
#endif
}
else
{
flashc_set_wait_state(0);
#if (defined AVR32_FLASHC_210_H_INCLUDED)
if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ)
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
else
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
#endif
}
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
return PM_FREQ_STATUS_OK;
}
void pm_configure_usb_clock(void)
{
#if (defined __AVR32_UC3A3256__) || (defined __AVR32_UC3A3128__) || (defined __AVR32_UC3A364__) || \
(defined __AVR32_UC3A3256S__) || (defined __AVR32_UC3A3128S__) || (defined __AVR32_UC3A364S__) || \
(defined __AT32UC3A3256__) || (defined __AT32UC3A3128__) || (defined __AT32UC3A364__) || \
(defined __AT32UC3A3256S__) || (defined __AT32UC3A3128S__) || (defined __AT32UC3A364S__)
// Setup USB GCLK.
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc
0, // osc_or_pll: use Osc (if 0) or PLL (if 1)
0, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
0, // diven
0); // div
// Enable USB GCLK.
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
#else
// Use 12MHz from OSC0 and generate 96 MHz
pm_pll_setup(&AVR32_PM, 1, // pll.
7, // mul.
1, // div.
0, // osc.
16); // lockcount.
pm_pll_set_option(&AVR32_PM, 1, // pll.
1, // pll_freq: choose the range 80-180MHz.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL1 and wait forl lock
pm_pll_enable(&AVR32_PM, 1);
// Wait for PLL1 locked.
pm_wait_for_pll1_locked(&AVR32_PM);
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc.
1, // osc_or_pll: use Osc (if 0) or PLL (if 1).
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
0, // diven.
0); // div.
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
#endif
}

105
src/platform/avr32/preprocessor.h
View File

@ -1,52 +1,55 @@
/* This header file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _PREPROCESSOR_H_
#define _PREPROCESSOR_H_
#include "tpaste.h"
#include "stringz.h"
#include "mrepeat.h"
#endif // _PREPROCESSOR_H_
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _PREPROCESSOR_H_
#define _PREPROCESSOR_H_
#include "tpaste.h"
#include "stringz.h"
#include "mrepeat.h"
#endif // _PREPROCESSOR_H_

579
src/platform/avr32/sdramc.c
View File

@ -1,262 +1,319 @@
/* This source file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief SDRAMC on EBI driver for AVR32 UC3.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an SDRAMC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "compiler.h"
#include "preprocessor.h"
#include "gpio.h"
#include "sdramc.h"
/*! \brief Waits during at least the specified delay before returning.
*
* \param ck Number of HSB clock cycles to wait.
*/
static void sdramc_ck_delay(unsigned long ck)
{
// Use the CPU cycle counter (CPU and HSB clocks are the same).
unsigned long delay_start_cycle = Get_system_register(AVR32_COUNT);
unsigned long delay_end_cycle = delay_start_cycle + ck;
// To be safer, the end of wait is based on an inequality test, so CPU cycle
// counter wrap around is checked.
if (delay_start_cycle <= delay_end_cycle)
{
while ((unsigned long)Get_system_register(AVR32_COUNT) < delay_end_cycle);
}
else
{
while ((unsigned long)Get_system_register(AVR32_COUNT) > delay_end_cycle);
}
}
/*! \brief Waits during at least the specified delay before returning.
*
* \param ns Number of nanoseconds to wait.
* \param hsb_mhz_up Rounded-up HSB frequency in MHz.
*/
#define sdramc_ns_delay(ns, hsb_mhz_up) sdramc_ck_delay(((ns) * (hsb_mhz_up) + 999) / 1000)
/*! \brief Waits during at least the specified delay before returning.
*
* \param us Number of microseconds to wait.
* \param hsb_mhz_up Rounded-up HSB frequency in MHz.
*/
#define sdramc_us_delay(us, hsb_mhz_up) sdramc_ck_delay((us) * (hsb_mhz_up))
/*! \brief Puts the multiplexed MCU pins used for the SDRAM under control of the
* SDRAMC.
*/
#if BOARD == EVK1100
static void sdramc_enable_muxed_pins(void)
{
static const gpio_map_t SDRAMC_EBI_GPIO_MAP =
{
// Enable data pins.
#define SDRAMC_ENABLE_DATA_PIN(DATA_BIT, unused) \
{AVR32_EBI_DATA_##DATA_BIT##_PIN, AVR32_EBI_DATA_##DATA_BIT##_FUNCTION},
MREPEAT(SDRAM_DBW, SDRAMC_ENABLE_DATA_PIN, ~)
#undef SDRAMC_ENABLE_DATA_PIN
// Enable row/column address pins.
{AVR32_EBI_ADDR_2_PIN, AVR32_EBI_ADDR_2_FUNCTION },
{AVR32_EBI_ADDR_3_PIN, AVR32_EBI_ADDR_3_FUNCTION },
{AVR32_EBI_ADDR_4_PIN, AVR32_EBI_ADDR_4_FUNCTION },
{AVR32_EBI_ADDR_5_PIN, AVR32_EBI_ADDR_5_FUNCTION },
{AVR32_EBI_ADDR_6_PIN, AVR32_EBI_ADDR_6_FUNCTION },
{AVR32_EBI_ADDR_7_PIN, AVR32_EBI_ADDR_7_FUNCTION },
{AVR32_EBI_ADDR_8_PIN, AVR32_EBI_ADDR_8_FUNCTION },
{AVR32_EBI_ADDR_9_PIN, AVR32_EBI_ADDR_9_FUNCTION },
{AVR32_EBI_ADDR_10_PIN, AVR32_EBI_ADDR_10_FUNCTION },
{AVR32_EBI_ADDR_11_PIN, AVR32_EBI_ADDR_11_FUNCTION },
{AVR32_EBI_SDA10_0_PIN, AVR32_EBI_SDA10_0_FUNCTION },
#if SDRAM_ROW_BITS >= 12
{AVR32_EBI_ADDR_13_PIN, AVR32_EBI_ADDR_13_FUNCTION },
#if SDRAM_ROW_BITS >= 13
{AVR32_EBI_ADDR_14_PIN, AVR32_EBI_ADDR_14_FUNCTION },
#endif
#endif
// Enable bank address pins.
{AVR32_EBI_ADDR_16_PIN, AVR32_EBI_ADDR_16_FUNCTION },
#if SDRAM_BANK_BITS >= 2
{AVR32_EBI_ADDR_17_PIN, AVR32_EBI_ADDR_17_FUNCTION },
#endif
// Enable data mask pins.
{AVR32_EBI_ADDR_0_PIN, AVR32_EBI_ADDR_0_FUNCTION },
{AVR32_EBI_NWE1_0_PIN, AVR32_EBI_NWE1_0_FUNCTION },
#if SDRAM_DBW >= 32
{AVR32_EBI_NWE2_0_PIN, AVR32_EBI_NWE2_0_FUNCTION },
{AVR32_EBI_NWE3_0_PIN, AVR32_EBI_NWE3_0_FUNCTION },
#endif
// Enable control pins.
{AVR32_EBI_SDWE_0_PIN, AVR32_EBI_SDWE_0_FUNCTION },
{AVR32_EBI_CAS_0_PIN, AVR32_EBI_CAS_0_FUNCTION },
{AVR32_EBI_RAS_0_PIN, AVR32_EBI_RAS_0_FUNCTION },
{AVR32_EBI_NCS_1_PIN, AVR32_EBI_NCS_1_FUNCTION },
// Enable clock-related pins.
{AVR32_EBI_SDCK_0_PIN, AVR32_EBI_SDCK_0_FUNCTION },
{AVR32_EBI_SDCKE_0_PIN, AVR32_EBI_SDCKE_0_FUNCTION }
};
gpio_enable_module(SDRAMC_EBI_GPIO_MAP, sizeof(SDRAMC_EBI_GPIO_MAP) / sizeof(SDRAMC_EBI_GPIO_MAP[0]));
}
#elif BOARD == STK1000
static void sdramc_enable_muxed_pins(void)
{
volatile avr32_hmatrix_t *hmatrix = &AVR32_HMATRIX;
// Enable SDRAM mode for CS1 in the BAMBI mux
hmatrix->sfr[4] |= 0x0002;
hmatrix->sfr[4] |= 0x0100;
static const gpio_map_t SDRAMC_EBI_GPIO_MAP =
{
// Enable DATA 16 through 31 pins, which is muxed with LCD
{AVR32_EBI_DATA_16_PIN, AVR32_EBI_DATA_16_FUNCTION },
{AVR32_EBI_DATA_17_PIN, AVR32_EBI_DATA_17_FUNCTION },
{AVR32_EBI_DATA_18_PIN, AVR32_EBI_DATA_18_FUNCTION },
{AVR32_EBI_DATA_19_PIN, AVR32_EBI_DATA_19_FUNCTION },
{AVR32_EBI_DATA_20_PIN, AVR32_EBI_DATA_20_FUNCTION },
{AVR32_EBI_DATA_21_PIN, AVR32_EBI_DATA_21_FUNCTION },
{AVR32_EBI_DATA_22_PIN, AVR32_EBI_DATA_22_FUNCTION },
{AVR32_EBI_DATA_23_PIN, AVR32_EBI_DATA_23_FUNCTION },
{AVR32_EBI_DATA_24_PIN, AVR32_EBI_DATA_24_FUNCTION },
{AVR32_EBI_DATA_25_PIN, AVR32_EBI_DATA_25_FUNCTION },
{AVR32_EBI_DATA_26_PIN, AVR32_EBI_DATA_26_FUNCTION },
{AVR32_EBI_DATA_27_PIN, AVR32_EBI_DATA_27_FUNCTION },
{AVR32_EBI_DATA_28_PIN, AVR32_EBI_DATA_28_FUNCTION },
{AVR32_EBI_DATA_29_PIN, AVR32_EBI_DATA_29_FUNCTION },
{AVR32_EBI_DATA_30_PIN, AVR32_EBI_DATA_30_FUNCTION },
{AVR32_EBI_DATA_31_PIN, AVR32_EBI_DATA_31_FUNCTION }
};
gpio_enable_module(SDRAMC_EBI_GPIO_MAP, sizeof(SDRAMC_EBI_GPIO_MAP) / sizeof(SDRAMC_EBI_GPIO_MAP[0]));
}
#endif
void sdramc_init(unsigned long hsb_hz)
{
unsigned long hsb_mhz_dn = hsb_hz / 1000000;
unsigned long hsb_mhz_up = (hsb_hz + 999999) / 1000000;
volatile ATPASTE2(U, SDRAM_DBW) *sdram = SDRAM;
unsigned int i;
// Put the multiplexed MCU pins used for the SDRAM under control of the SDRAMC.
sdramc_enable_muxed_pins();
// Enable SDRAM mode for CS1.
AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR] |= 1 << AVR32_EBI_SDRAM_CS;
AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR];
// Configure the SDRAM Controller with SDRAM setup and timing information.
// All timings below are rounded up because they are minimal values.
AVR32_SDRAMC.cr =
((( SDRAM_COL_BITS - 8) << AVR32_SDRAMC_CR_NC_OFFSET ) & AVR32_SDRAMC_CR_NC_MASK ) |
((( SDRAM_ROW_BITS - 11) << AVR32_SDRAMC_CR_NR_OFFSET ) & AVR32_SDRAMC_CR_NR_MASK ) |
((( SDRAM_BANK_BITS - 1) << AVR32_SDRAMC_CR_NB_OFFSET ) & AVR32_SDRAMC_CR_NB_MASK ) |
(( SDRAM_CAS << AVR32_SDRAMC_CR_CAS_OFFSET ) & AVR32_SDRAMC_CR_CAS_MASK ) |
((( SDRAM_DBW >> 4) << AVR32_SDRAMC_CR_DBW_OFFSET ) & AVR32_SDRAMC_CR_DBW_MASK ) |
((((SDRAM_TWR * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TWR_OFFSET ) & AVR32_SDRAMC_CR_TWR_MASK ) |
((((SDRAM_TRC * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRC_OFFSET ) & AVR32_SDRAMC_CR_TRC_MASK ) |
((((SDRAM_TRP * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRP_OFFSET ) & AVR32_SDRAMC_CR_TRP_MASK ) |
((((SDRAM_TRCD * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRCD_OFFSET) & AVR32_SDRAMC_CR_TRCD_MASK) |
((((SDRAM_TRAS * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRAS_OFFSET) & AVR32_SDRAMC_CR_TRAS_MASK) |
((((SDRAM_TXSR * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TXSR_OFFSET) & AVR32_SDRAMC_CR_TXSR_MASK);
AVR32_SDRAMC.cr;
// Issue a NOP command to the SDRAM in order to start the generation of SDRAMC signals.
AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_NOP;
AVR32_SDRAMC.mr;
sdram[0];
// Wait during the SDRAM stable-clock initialization delay.
sdramc_us_delay(SDRAM_STABLE_CLOCK_INIT_DELAY, hsb_mhz_up);
// Issue a PRECHARGE ALL command to the SDRAM.
AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_BANKS_PRECHARGE;
AVR32_SDRAMC.mr;
sdram[0];
sdramc_ns_delay(SDRAM_TRP, hsb_mhz_up);
// Issue initialization AUTO REFRESH commands to the SDRAM.
AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_AUTO_REFRESH;
AVR32_SDRAMC.mr;
for (i = 0; i < SDRAM_INIT_AUTO_REFRESH_COUNT; i++)
{
sdram[0];
sdramc_ns_delay(SDRAM_TRFC, hsb_mhz_up);
}
// Issue a LOAD MODE REGISTER command to the SDRAM.
// This configures the SDRAM with the following parameters in the mode register:
// - bits 0 to 2: burst length: 1 (000b);
// - bit 3: burst type: sequential (0b);
// - bits 4 to 6: CAS latency: AVR32_SDRAMC.CR.cas;
// - bits 7 to 8: operating mode: standard operation (00b);
// - bit 9: write burst mode: programmed burst length (0b);
// - all other bits: reserved: 0b.
AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_LOAD_MODE;
AVR32_SDRAMC.mr;
sdram[0];
sdramc_ns_delay(SDRAM_TMRD, hsb_mhz_up);
// Switch the SDRAM Controller to normal mode.
AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_NORMAL;
AVR32_SDRAMC.mr;
sdram[0];
// Write the refresh period into the SDRAMC Refresh Timer Register.
// tR is rounded down because it is a maximal value.
AVR32_SDRAMC.tr = (SDRAM_TR * hsb_mhz_dn) / 1000;
AVR32_SDRAMC.tr;
}
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief SDRAMC on EBI driver for AVR32 UC3.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an SDRAMC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#include "compiler.h"
#include "preprocessor.h"
#include "gpio.h"
#include "sdramc.h"
/*! \brief Waits during at least the specified delay before returning.
*
* \param ck Number of HSB clock cycles to wait.
*/
static void sdramc_ck_delay(unsigned long ck)
{
// Use the CPU cycle counter (CPU and HSB clocks are the same).
unsigned long delay_start_cycle = Get_system_register(AVR32_COUNT);
unsigned long delay_end_cycle = delay_start_cycle + ck;
// To be safer, the end of wait is based on an inequality test, so CPU cycle
// counter wrap around is checked.
if (delay_start_cycle > delay_end_cycle)
{
while ((unsigned long)Get_system_register(AVR32_COUNT) > delay_end_cycle);
}
while ((unsigned long)Get_system_register(AVR32_COUNT) < delay_end_cycle);
}
/*! \brief Waits during at least the specified delay before returning.
*
* \param ns Number of nanoseconds to wait.
* \param hsb_mhz_up Rounded-up HSB frequency in MHz.
*/
#define sdramc_ns_delay(ns, hsb_mhz_up) sdramc_ck_delay(((ns) * (hsb_mhz_up) + 999) / 1000)
/*! \brief Waits during at least the specified delay before returning.
*
* \param us Number of microseconds to wait.
* \param hsb_mhz_up Rounded-up HSB frequency in MHz.
*/
#define sdramc_us_delay(us, hsb_mhz_up) sdramc_ck_delay((us) * (hsb_mhz_up))
/*! \brief Puts the multiplexed MCU pins used for the SDRAM under control of the
* SDRAMC.
*/
#if BOARD == EVK1100 || BOARD == EVK1104 || BOARD == EVK1105
static void sdramc_enable_muxed_pins(void)
{
static const gpio_map_t SDRAMC_EBI_GPIO_MAP =
{
// Enable data pins.
#define SDRAMC_ENABLE_DATA_PIN(DATA_BIT, unused) \
{AVR32_EBI_DATA_##DATA_BIT##_PIN, AVR32_EBI_DATA_##DATA_BIT##_FUNCTION},
MREPEAT(SDRAM_DBW, SDRAMC_ENABLE_DATA_PIN, ~)
#undef SDRAMC_ENABLE_DATA_PIN
// Enable row/column address pins.
{AVR32_EBI_ADDR_2_PIN, AVR32_EBI_ADDR_2_FUNCTION },
{AVR32_EBI_ADDR_3_PIN, AVR32_EBI_ADDR_3_FUNCTION },
{AVR32_EBI_ADDR_4_PIN, AVR32_EBI_ADDR_4_FUNCTION },
{AVR32_EBI_ADDR_5_PIN, AVR32_EBI_ADDR_5_FUNCTION },
{AVR32_EBI_ADDR_6_PIN, AVR32_EBI_ADDR_6_FUNCTION },
{AVR32_EBI_ADDR_7_PIN, AVR32_EBI_ADDR_7_FUNCTION },
{AVR32_EBI_ADDR_8_PIN, AVR32_EBI_ADDR_8_FUNCTION },
{AVR32_EBI_ADDR_9_PIN, AVR32_EBI_ADDR_9_FUNCTION },
{AVR32_EBI_ADDR_10_PIN, AVR32_EBI_ADDR_10_FUNCTION },
{AVR32_EBI_ADDR_11_PIN, AVR32_EBI_ADDR_11_FUNCTION },
{AVR32_EBI_SDA10_0_PIN, AVR32_EBI_SDA10_0_FUNCTION },
#if SDRAM_ROW_BITS >= 12
{AVR32_EBI_ADDR_13_PIN, AVR32_EBI_ADDR_13_FUNCTION },
#if SDRAM_ROW_BITS >= 13
{AVR32_EBI_ADDR_14_PIN, AVR32_EBI_ADDR_14_FUNCTION },
#endif
#endif
// Enable bank address pins.
{AVR32_EBI_ADDR_16_PIN, AVR32_EBI_ADDR_16_FUNCTION },
#if SDRAM_BANK_BITS >= 2
{AVR32_EBI_ADDR_17_PIN, AVR32_EBI_ADDR_17_FUNCTION },
#endif
// Enable data mask pins.
{AVR32_EBI_ADDR_0_PIN, AVR32_EBI_ADDR_0_FUNCTION },
{AVR32_EBI_NWE1_0_PIN, AVR32_EBI_NWE1_0_FUNCTION },
#if SDRAM_DBW >= 32
{AVR32_EBI_ADDR_1_PIN, AVR32_EBI_ADDR_1_FUNCTION },
{AVR32_EBI_NWE3_0_PIN, AVR32_EBI_NWE3_0_FUNCTION },
#endif
// Enable control pins.
{AVR32_EBI_SDWE_0_PIN, AVR32_EBI_SDWE_0_FUNCTION },
{AVR32_EBI_CAS_0_PIN, AVR32_EBI_CAS_0_FUNCTION },
{AVR32_EBI_RAS_0_PIN, AVR32_EBI_RAS_0_FUNCTION },
{AVR32_EBI_NCS_1_PIN, AVR32_EBI_NCS_1_FUNCTION },
// Enable clock-related pins.
{AVR32_EBI_SDCK_0_PIN, AVR32_EBI_SDCK_0_FUNCTION },
{AVR32_EBI_SDCKE_0_PIN, AVR32_EBI_SDCKE_0_FUNCTION }
};
gpio_enable_module(SDRAMC_EBI_GPIO_MAP, sizeof(SDRAMC_EBI_GPIO_MAP) / sizeof(SDRAMC_EBI_GPIO_MAP[0]));
}
#elif BOARD == UC3C_EK
static void sdramc_enable_muxed_pins(void)
{
static const gpio_map_t SDRAMC_EBI_GPIO_MAP =
{
// Enable data pins.
#define SDRAMC_ENABLE_DATA_PIN(DATA_BIT, unused) \
{AVR32_EBI_DATA_##DATA_BIT##_PIN, AVR32_EBI_DATA_##DATA_BIT##_FUNCTION},
MREPEAT(SDRAM_DBW, SDRAMC_ENABLE_DATA_PIN, ~)
#undef SDRAMC_ENABLE_DATA_PIN
// Enable row/column address pins.
{AVR32_EBI_ADDR_2_PIN, AVR32_EBI_ADDR_2_FUNCTION },
{AVR32_EBI_ADDR_3_PIN, AVR32_EBI_ADDR_3_FUNCTION },
{AVR32_EBI_ADDR_4_PIN, AVR32_EBI_ADDR_4_FUNCTION },
{AVR32_EBI_ADDR_5_PIN, AVR32_EBI_ADDR_5_FUNCTION },
{AVR32_EBI_ADDR_6_PIN, AVR32_EBI_ADDR_6_FUNCTION },
{AVR32_EBI_ADDR_7_PIN, AVR32_EBI_ADDR_7_FUNCTION },
{AVR32_EBI_ADDR_8_PIN, AVR32_EBI_ADDR_8_FUNCTION },
{AVR32_EBI_ADDR_9_PIN, AVR32_EBI_ADDR_9_FUNCTION },
{AVR32_EBI_ADDR_10_PIN, AVR32_EBI_ADDR_10_FUNCTION },
{AVR32_EBI_ADDR_11_PIN, AVR32_EBI_ADDR_11_FUNCTION },
{AVR32_EBI_SDA10_PIN, AVR32_EBI_SDA10_FUNCTION },
#if SDRAM_ROW_BITS >= 12
{AVR32_EBI_ADDR_13_PIN, AVR32_EBI_ADDR_13_FUNCTION },
#if SDRAM_ROW_BITS >= 13
{AVR32_EBI_ADDR_14_PIN, AVR32_EBI_ADDR_14_FUNCTION },
#endif
#endif
// Enable bank address pins.
{AVR32_EBI_ADDR_16_PIN, AVR32_EBI_ADDR_16_FUNCTION },
#if SDRAM_BANK_BITS >= 2
{AVR32_EBI_ADDR_17_PIN, AVR32_EBI_ADDR_17_FUNCTION },
#endif
// Enable data mask pins.
{AVR32_EBI_ADDR_0_PIN, AVR32_EBI_ADDR_0_FUNCTION },
{AVR32_EBI_NWE1_PIN, AVR32_EBI_NWE1_FUNCTION },
#if SDRAM_DBW >= 32
{AVR32_EBI_ADDR_1_PIN, AVR32_EBI_ADDR_1_FUNCTION },
{AVR32_EBI_NWE3_PIN, AVR32_EBI_NWE3_FUNCTION },
#endif
// Enable control pins.
{AVR32_EBI_SDWE_PIN, AVR32_EBI_SDWE_FUNCTION },
{AVR32_EBI_CAS_PIN, AVR32_EBI_CAS_FUNCTION },
{AVR32_EBI_RAS_PIN, AVR32_EBI_RAS_FUNCTION },
{AVR32_EBI_NCS_1_PIN, AVR32_EBI_NCS_1_FUNCTION },
// Enable clock-related pins.
{AVR32_EBI_SDCK_PIN, AVR32_EBI_SDCK_FUNCTION },
{AVR32_EBI_SDCKE_PIN, AVR32_EBI_SDCKE_FUNCTION }
};
gpio_enable_module(SDRAMC_EBI_GPIO_MAP, sizeof(SDRAMC_EBI_GPIO_MAP) / sizeof(SDRAMC_EBI_GPIO_MAP[0]));
}
#elif BOARD == STK1000
static void sdramc_enable_muxed_pins(void)
{
volatile avr32_hmatrix_t *hmatrix = &AVR32_HMATRIX;
// Enable SDRAM mode for CS1 in the BAMBI mux
hmatrix->sfr[4] |= 0x0002;
hmatrix->sfr[4] |= 0x0100;
static const gpio_map_t SDRAMC_EBI_GPIO_MAP =
{
// Enable DATA 16 through 31 pins, which is muxed with LCD
{AVR32_EBI_DATA_16_PIN, AVR32_EBI_DATA_16_FUNCTION },
{AVR32_EBI_DATA_17_PIN, AVR32_EBI_DATA_17_FUNCTION },
{AVR32_EBI_DATA_18_PIN, AVR32_EBI_DATA_18_FUNCTION },
{AVR32_EBI_DATA_19_PIN, AVR32_EBI_DATA_19_FUNCTION },
{AVR32_EBI_DATA_20_PIN, AVR32_EBI_DATA_20_FUNCTION },
{AVR32_EBI_DATA_21_PIN, AVR32_EBI_DATA_21_FUNCTION },
{AVR32_EBI_DATA_22_PIN, AVR32_EBI_DATA_22_FUNCTION },
{AVR32_EBI_DATA_23_PIN, AVR32_EBI_DATA_23_FUNCTION },
{AVR32_EBI_DATA_24_PIN, AVR32_EBI_DATA_24_FUNCTION },
{AVR32_EBI_DATA_25_PIN, AVR32_EBI_DATA_25_FUNCTION },
{AVR32_EBI_DATA_26_PIN, AVR32_EBI_DATA_26_FUNCTION },
{AVR32_EBI_DATA_27_PIN, AVR32_EBI_DATA_27_FUNCTION },
{AVR32_EBI_DATA_28_PIN, AVR32_EBI_DATA_28_FUNCTION },
{AVR32_EBI_DATA_29_PIN, AVR32_EBI_DATA_29_FUNCTION },
{AVR32_EBI_DATA_30_PIN, AVR32_EBI_DATA_30_FUNCTION },
{AVR32_EBI_DATA_31_PIN, AVR32_EBI_DATA_31_FUNCTION }
};
gpio_enable_module(SDRAMC_EBI_GPIO_MAP, sizeof(SDRAMC_EBI_GPIO_MAP) / sizeof(SDRAMC_EBI_GPIO_MAP[0]));
}
#endif
void sdramc_init(unsigned long hsb_hz)
{
unsigned long hsb_mhz_dn = hsb_hz / 1000000;
unsigned long hsb_mhz_up = (hsb_hz + 999999) / 1000000;
volatile ATPASTE2(U, SDRAM_DBW) *sdram = SDRAM;
unsigned int i;
// Put the multiplexed MCU pins used for the SDRAM under control of the SDRAMC.
sdramc_enable_muxed_pins();
// Enable SDRAM mode for CS1.
AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR] |= 1 << AVR32_EBI_SDRAM_CS;
AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR];
// Configure the SDRAM Controller with SDRAM setup and timing information.
// All timings below are rounded up because they are minimal values.
AVR32_SDRAMC.cr =
((( SDRAM_COL_BITS - 8) << AVR32_SDRAMC_CR_NC_OFFSET ) & AVR32_SDRAMC_CR_NC_MASK ) |
((( SDRAM_ROW_BITS - 11) << AVR32_SDRAMC_CR_NR_OFFSET ) & AVR32_SDRAMC_CR_NR_MASK ) |
((( SDRAM_BANK_BITS - 1) << AVR32_SDRAMC_CR_NB_OFFSET ) & AVR32_SDRAMC_CR_NB_MASK ) |
(( SDRAM_CAS << AVR32_SDRAMC_CR_CAS_OFFSET ) & AVR32_SDRAMC_CR_CAS_MASK ) |
((( SDRAM_DBW >> 4) << AVR32_SDRAMC_CR_DBW_OFFSET ) & AVR32_SDRAMC_CR_DBW_MASK ) |
((((SDRAM_TWR * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TWR_OFFSET ) & AVR32_SDRAMC_CR_TWR_MASK ) |
((((SDRAM_TRC * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRC_OFFSET ) & AVR32_SDRAMC_CR_TRC_MASK ) |
((((SDRAM_TRP * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRP_OFFSET ) & AVR32_SDRAMC_CR_TRP_MASK ) |
((((SDRAM_TRCD * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRCD_OFFSET) & AVR32_SDRAMC_CR_TRCD_MASK) |
((((SDRAM_TRAS * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRAS_OFFSET) & AVR32_SDRAMC_CR_TRAS_MASK) |
((((SDRAM_TXSR * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TXSR_OFFSET) & AVR32_SDRAMC_CR_TXSR_MASK);
AVR32_SDRAMC.cr;
// Issue a NOP command to the SDRAM in order to start the generation of SDRAMC signals.
AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_NOP;
AVR32_SDRAMC.mr;
sdram[0];
// Wait during the SDRAM stable-clock initialization delay.
sdramc_us_delay(SDRAM_STABLE_CLOCK_INIT_DELAY, hsb_mhz_up);
// Issue a PRECHARGE ALL command to the SDRAM.
AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_BANKS_PRECHARGE;
AVR32_SDRAMC.mr;
sdram[0];
sdramc_ns_delay(SDRAM_TRP, hsb_mhz_up);
// Issue initialization AUTO REFRESH commands to the SDRAM.
AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_AUTO_REFRESH;
AVR32_SDRAMC.mr;
for (i = 0; i < SDRAM_INIT_AUTO_REFRESH_COUNT; i++)
{
sdram[0];
sdramc_ns_delay(SDRAM_TRFC, hsb_mhz_up);
}
// Issue a LOAD MODE REGISTER command to the SDRAM.
// This configures the SDRAM with the following parameters in the mode register:
// - bits 0 to 2: burst length: 1 (000b);
// - bit 3: burst type: sequential (0b);
// - bits 4 to 6: CAS latency: AVR32_SDRAMC.CR.cas;
// - bits 7 to 8: operating mode: standard operation (00b);
// - bit 9: write burst mode: programmed burst length (0b);
// - all other bits: reserved: 0b.
AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_LOAD_MODE;
AVR32_SDRAMC.mr;
sdram[0];
sdramc_ns_delay(SDRAM_TMRD, hsb_mhz_up);
// Switch the SDRAM Controller to normal mode.
AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_NORMAL;
AVR32_SDRAMC.mr;
sdram[0];
// Write the refresh period into the SDRAMC Refresh Timer Register.
// tR is rounded down because it is a maximal value.
AVR32_SDRAMC.tr = (SDRAM_TR * hsb_mhz_dn) / 1000;
AVR32_SDRAMC.tr;
}

172
src/platform/avr32/sdramc.h
View File

@ -1,84 +1,90 @@
/* This header file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief SDRAMC on EBI driver for AVR32 UC3.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an SDRAMC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _SDRAMC_H_
#define _SDRAMC_H_
#include <avr32/io.h>
#include "board.h"
#ifdef SDRAM_PART_HDR
#include SDRAM_PART_HDR
#else
#error No SDRAM header file defined
#endif
//! Pointer to SDRAM.
#define SDRAM ((void *)AVR32_EBI_CS1_ADDRESS)
//! SDRAM size.
#define SDRAM_SIZE (1 << (SDRAM_BANK_BITS + \
SDRAM_ROW_BITS + \
SDRAM_COL_BITS + \
(SDRAM_DBW >> 4)))
/*! \brief Initializes the AVR32 SDRAM Controller and the connected SDRAM(s).
*
* \param hsb_hz HSB frequency in Hz (the HSB frequency is applied to the SDRAMC
* and to the SDRAM).
*
* \note HMATRIX and SDRAMC registers are always read with a dummy load
* operation after having been written to, in order to force write-back
* before executing the following accesses, which depend on the values set
* in these registers.
*
* \note Each access to the SDRAM address space validates the mode of the SDRAMC
* and generates an operation corresponding to this mode.
*/
extern void sdramc_init(unsigned long hsb_hz);
#endif // _SDRAMC_H_
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief SDRAMC on EBI driver for AVR32 UC3.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an SDRAMC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _SDRAMC_H_
#define _SDRAMC_H_
#include <avr32/io.h>
#include "board.h"
#ifdef SDRAM_PART_HDR
#include SDRAM_PART_HDR
#else
#error No SDRAM header file defined
#endif
//! Pointer to SDRAM.
#if BOARD == UC3C_EK
#define SDRAM ((void *)AVR32_EBI_CS1_0_ADDRESS)
#else
#define SDRAM ((void *)AVR32_EBI_CS1_ADDRESS)
#endif
//! SDRAM size.
#define SDRAM_SIZE (1 << (SDRAM_BANK_BITS + \
SDRAM_ROW_BITS + \
SDRAM_COL_BITS + \
(SDRAM_DBW >> 4)))
/*! \brief Initializes the AVR32 SDRAM Controller and the connected SDRAM(s).
*
* \param hsb_hz HSB frequency in Hz (the HSB frequency is applied to the SDRAMC
* and to the SDRAM).
*
* \note HMATRIX and SDRAMC registers are always read with a dummy load
* operation after having been written to, in order to force write-back
* before executing the following accesses, which depend on the values set
* in these registers.
*
* \note Each access to the SDRAM address space validates the mode of the SDRAMC
* and generates an operation corresponding to this mode.
*/
extern void sdramc_init(unsigned long hsb_hz);
#endif // _SDRAMC_H_

145
src/platform/avr32/stringz.h
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@ -1,72 +1,75 @@
/* This header file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor stringizing utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _STRINGZ_H_
#define _STRINGZ_H_
/*! \brief Stringize.
*
* Stringize a preprocessing token, this token being allowed to be \#defined.
*
* May be used only within macros with the token passed as an argument if the token is \#defined.
*
* For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
* and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
* writing "A0".
*/
#define STRINGZ(x) #x
/*! \brief Absolute stringize.
*
* Stringize a preprocessing token, this token being allowed to be \#defined.
*
* No restriction of use if the token is \#defined.
*
* For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
* equivalent to writing "A0".
*/
#define ASTRINGZ(x) STRINGZ(x)
#endif // _STRINGZ_H_
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor stringizing utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _STRINGZ_H_
#define _STRINGZ_H_
/*! \brief Stringize.
*
* Stringize a preprocessing token, this token being allowed to be \#defined.
*
* May be used only within macros with the token passed as an argument if the token is \#defined.
*
* For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
* and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
* writing "A0".
*/
#define STRINGZ(x) #x
/*! \brief Absolute stringize.
*
* Stringize a preprocessing token, this token being allowed to be \#defined.
*
* No restriction of use if the token is \#defined.
*
* For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
* equivalent to writing "A0".
*/
#define ASTRINGZ(x) STRINGZ(x)
#endif // _STRINGZ_H_

613
src/platform/avr32/tc.c
View File

@ -1,299 +1,314 @@
/* This source file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief TC driver for AVR32 UC3.
*
* AVR32 Timer/Counter driver module.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a TC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <avr32/io.h>
#include "compiler.h"
#include "tc.h"
int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
return tc->channel[channel].imr;
}
int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield)
{
Bool global_interrupt_enabled = Is_global_interrupt_enabled();
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// Enable the appropriate interrupts.
tc->channel[channel].ier = bitfield->etrgs << AVR32_TC_ETRGS_OFFSET |
bitfield->ldrbs << AVR32_TC_LDRBS_OFFSET |
bitfield->ldras << AVR32_TC_LDRAS_OFFSET |
bitfield->cpcs << AVR32_TC_CPCS_OFFSET |
bitfield->cpbs << AVR32_TC_CPBS_OFFSET |
bitfield->cpas << AVR32_TC_CPAS_OFFSET |
bitfield->lovrs << AVR32_TC_LOVRS_OFFSET |
bitfield->covfs << AVR32_TC_COVFS_OFFSET;
// Disable the appropriate interrupts.
if (global_interrupt_enabled) Disable_global_interrupt();
tc->channel[channel].idr = (~bitfield->etrgs & 1) << AVR32_TC_ETRGS_OFFSET |
(~bitfield->ldrbs & 1) << AVR32_TC_LDRBS_OFFSET |
(~bitfield->ldras & 1) << AVR32_TC_LDRAS_OFFSET |
(~bitfield->cpcs & 1) << AVR32_TC_CPCS_OFFSET |
(~bitfield->cpbs & 1) << AVR32_TC_CPBS_OFFSET |
(~bitfield->cpas & 1) << AVR32_TC_CPAS_OFFSET |
(~bitfield->lovrs & 1) << AVR32_TC_LOVRS_OFFSET |
(~bitfield->covfs & 1) << AVR32_TC_COVFS_OFFSET;
tc->channel[channel].sr;
if (global_interrupt_enabled) Enable_global_interrupt();
return 0;
}
int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS || ext_clk_sig_src >= 1 << AVR32_TC_BMR_TC0XC0S_SIZE)
return TC_INVALID_ARGUMENT;
// Clear bit-field and set the correct behavior.
tc->bmr = (tc->bmr & ~(AVR32_TC_BMR_TC0XC0S_MASK << (channel * AVR32_TC_BMR_TC0XC0S_SIZE))) |
(ext_clk_sig_src << (channel * AVR32_TC_BMR_TC0XC0S_SIZE));
return 0;
}
int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt)
{
// Check for valid input.
if (opt->channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// MEASURE SIGNALS: Capture operating mode.
tc->channel[opt->channel].cmr = opt->ldrb << AVR32_TC_LDRB_OFFSET |
opt->ldra << AVR32_TC_LDRA_OFFSET |
0 << AVR32_TC_WAVE_OFFSET |
opt->cpctrg << AVR32_TC_CPCTRG_OFFSET |
opt->abetrg << AVR32_TC_ABETRG_OFFSET |
opt->etrgedg << AVR32_TC_ETRGEDG_OFFSET|
opt->ldbdis << AVR32_TC_LDBDIS_OFFSET |
opt->ldbstop << AVR32_TC_LDBSTOP_OFFSET |
opt->burst << AVR32_TC_BURST_OFFSET |
opt->clki << AVR32_TC_CLKI_OFFSET |
opt->tcclks << AVR32_TC_TCCLKS_OFFSET;
return 0;
}
int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt)
{
// Check for valid input.
if (opt->channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// GENERATE SIGNALS: Waveform operating mode.
tc->channel[opt->channel].cmr = opt->bswtrg << AVR32_TC_BSWTRG_OFFSET |
opt->beevt << AVR32_TC_BEEVT_OFFSET |
opt->bcpc << AVR32_TC_BCPC_OFFSET |
opt->bcpb << AVR32_TC_BCPB_OFFSET |
opt->aswtrg << AVR32_TC_ASWTRG_OFFSET |
opt->aeevt << AVR32_TC_AEEVT_OFFSET |
opt->acpc << AVR32_TC_ACPC_OFFSET |
opt->acpa << AVR32_TC_ACPA_OFFSET |
1 << AVR32_TC_WAVE_OFFSET |
opt->wavsel << AVR32_TC_WAVSEL_OFFSET |
opt->enetrg << AVR32_TC_ENETRG_OFFSET |
opt->eevt << AVR32_TC_EEVT_OFFSET |
opt->eevtedg << AVR32_TC_EEVTEDG_OFFSET |
opt->cpcdis << AVR32_TC_CPCDIS_OFFSET |
opt->cpcstop << AVR32_TC_CPCSTOP_OFFSET |
opt->burst << AVR32_TC_BURST_OFFSET |
opt->clki << AVR32_TC_CLKI_OFFSET |
opt->tcclks << AVR32_TC_TCCLKS_OFFSET;
return 0;
}
int tc_start(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// Enable, reset and start the selected timer/counter channel.
tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK | AVR32_TC_CLKEN_MASK;
return 0;
}
int tc_stop(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// Disable the selected timer/counter channel.
tc->channel[channel].ccr = AVR32_TC_CLKDIS_MASK;
return 0;
}
int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// Reset the selected timer/counter channel.
tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK;
return 0;
}
void tc_sync_trigger(volatile avr32_tc_t *tc)
{
// Reset all channels of the selected timer/counter.
tc->bcr = AVR32_TC_BCR_SYNC_MASK;
}
int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
return tc->channel[channel].sr;
}
int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
return Rd_bitfield(tc->channel[channel].cv, AVR32_TC_CV_MASK);
}
int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
return Rd_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK);
}
int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
return Rd_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK);
}
int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
return Rd_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK);
}
int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// This function is only available in WAVEFORM mode.
if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
Wr_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK, value);
return value;
}
int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// This function is only available in WAVEFORM mode.
if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
Wr_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK, value);
return value;
}
int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// This function is only available in WAVEFORM mode.
if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
Wr_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK, value);
return value;
}
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief TC driver for AVR32 UC3.
*
* AVR32 Timer/Counter driver module.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a TC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#include <avr32/io.h>
#include "compiler.h"
#include "tc.h"
int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
return tc->channel[channel].imr;
}
int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield)
{
Bool global_interrupt_enabled = Is_global_interrupt_enabled();
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// Enable the appropriate interrupts.
tc->channel[channel].ier = bitfield->etrgs << AVR32_TC_ETRGS_OFFSET |
bitfield->ldrbs << AVR32_TC_LDRBS_OFFSET |
bitfield->ldras << AVR32_TC_LDRAS_OFFSET |
bitfield->cpcs << AVR32_TC_CPCS_OFFSET |
bitfield->cpbs << AVR32_TC_CPBS_OFFSET |
bitfield->cpas << AVR32_TC_CPAS_OFFSET |
bitfield->lovrs << AVR32_TC_LOVRS_OFFSET |
bitfield->covfs << AVR32_TC_COVFS_OFFSET;
// Disable the appropriate interrupts.
if (global_interrupt_enabled) Disable_global_interrupt();
tc->channel[channel].idr = (~bitfield->etrgs & 1) << AVR32_TC_ETRGS_OFFSET |
(~bitfield->ldrbs & 1) << AVR32_TC_LDRBS_OFFSET |
(~bitfield->ldras & 1) << AVR32_TC_LDRAS_OFFSET |
(~bitfield->cpcs & 1) << AVR32_TC_CPCS_OFFSET |
(~bitfield->cpbs & 1) << AVR32_TC_CPBS_OFFSET |
(~bitfield->cpas & 1) << AVR32_TC_CPAS_OFFSET |
(~bitfield->lovrs & 1) << AVR32_TC_LOVRS_OFFSET |
(~bitfield->covfs & 1) << AVR32_TC_COVFS_OFFSET;
tc->channel[channel].sr;
if (global_interrupt_enabled) Enable_global_interrupt();
return 0;
}
int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS || ext_clk_sig_src >= 1 << AVR32_TC_BMR_TC0XC0S_SIZE)
return TC_INVALID_ARGUMENT;
// Clear bit-field and set the correct behavior.
tc->bmr = (tc->bmr & ~(AVR32_TC_BMR_TC0XC0S_MASK << (channel * AVR32_TC_BMR_TC0XC0S_SIZE))) |
(ext_clk_sig_src << (channel * AVR32_TC_BMR_TC0XC0S_SIZE));
return 0;
}
int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt)
{
// Check for valid input.
if (opt->channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// MEASURE SIGNALS: Capture operating mode.
tc->channel[opt->channel].cmr = opt->ldrb << AVR32_TC_LDRB_OFFSET |
opt->ldra << AVR32_TC_LDRA_OFFSET |
0 << AVR32_TC_WAVE_OFFSET |
opt->cpctrg << AVR32_TC_CPCTRG_OFFSET |
opt->abetrg << AVR32_TC_ABETRG_OFFSET |
opt->etrgedg << AVR32_TC_ETRGEDG_OFFSET|
opt->ldbdis << AVR32_TC_LDBDIS_OFFSET |
opt->ldbstop << AVR32_TC_LDBSTOP_OFFSET |
opt->burst << AVR32_TC_BURST_OFFSET |
opt->clki << AVR32_TC_CLKI_OFFSET |
opt->tcclks << AVR32_TC_TCCLKS_OFFSET;
return 0;
}
int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt)
{
// Check for valid input.
if (opt->channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// GENERATE SIGNALS: Waveform operating mode.
tc->channel[opt->channel].cmr = opt->bswtrg << AVR32_TC_BSWTRG_OFFSET |
opt->beevt << AVR32_TC_BEEVT_OFFSET |
opt->bcpc << AVR32_TC_BCPC_OFFSET |
opt->bcpb << AVR32_TC_BCPB_OFFSET |
opt->aswtrg << AVR32_TC_ASWTRG_OFFSET |
opt->aeevt << AVR32_TC_AEEVT_OFFSET |
opt->acpc << AVR32_TC_ACPC_OFFSET |
opt->acpa << AVR32_TC_ACPA_OFFSET |
1 << AVR32_TC_WAVE_OFFSET |
opt->wavsel << AVR32_TC_WAVSEL_OFFSET |
opt->enetrg << AVR32_TC_ENETRG_OFFSET |
opt->eevt << AVR32_TC_EEVT_OFFSET |
opt->eevtedg << AVR32_TC_EEVTEDG_OFFSET |
opt->cpcdis << AVR32_TC_CPCDIS_OFFSET |
opt->cpcstop << AVR32_TC_CPCSTOP_OFFSET |
opt->burst << AVR32_TC_BURST_OFFSET |
opt->clki << AVR32_TC_CLKI_OFFSET |
opt->tcclks << AVR32_TC_TCCLKS_OFFSET;
return 0;
}
int tc_start(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// Enable, reset and start the selected timer/counter channel.
tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK | AVR32_TC_CLKEN_MASK;
return 0;
}
int tc_stop(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// Disable the selected timer/counter channel.
tc->channel[channel].ccr = AVR32_TC_CLKDIS_MASK;
return 0;
}
int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// Reset the selected timer/counter channel.
tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK;
return 0;
}
void tc_sync_trigger(volatile avr32_tc_t *tc)
{
// Reset all channels of the selected timer/counter.
tc->bcr = AVR32_TC_BCR_SYNC_MASK;
}
void tc_sync_start(volatile avr32_tc_t *tc)
{
unsigned int i;
// Enable the clock for each channel.
for(i=0; i<TC_NUMBER_OF_CHANNELS;i++)
tc->channel[i].ccr = AVR32_TC_CLKEN_MASK;
// Reset all channels of the selected timer/counter.
tc->bcr = AVR32_TC_BCR_SYNC_MASK;
}
int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
return tc->channel[channel].sr;
}
int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
return Rd_bitfield(tc->channel[channel].cv, AVR32_TC_CV_MASK);
}
int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
return Rd_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK);
}
int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
return Rd_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK);
}
int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
return Rd_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK);
}
int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// This function is only available in WAVEFORM mode.
if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
Wr_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK, value);
return value;
}
int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// This function is only available in WAVEFORM mode.
if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
Wr_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK, value);
return value;
}
int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
{
// Check for valid input.
if (channel >= TC_NUMBER_OF_CHANNELS)
return TC_INVALID_ARGUMENT;
// This function is only available in WAVEFORM mode.
if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
Wr_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK, value);
return value;
}

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src/platform/avr32/tc.h
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185
src/platform/avr32/tpaste.h
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@ -1,92 +1,95 @@
/* This header file is part of the ATMEL AVR32-SoftwareFramework-1.3.0-AT32UC3A Release */
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.6.1 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor token pasting utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _TPASTE_H_
#define _TPASTE_H_
/*! \name Token Paste
*
* Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
*
* May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
*
* For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
* UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
* equivalent to writing U32.
*/
//! @{
#define TPASTE2( a, b) a##b
#define TPASTE3( a, b, c) a##b##c
#define TPASTE4( a, b, c, d) a##b##c##d
#define TPASTE5( a, b, c, d, e) a##b##c##d##e
#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f
#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g
#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h
#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i
#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j
//! @}
/*! \name Absolute Token Paste
*
* Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
*
* No restriction of use if the tokens are \#defined.
*
* For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
* as 32 is equivalent to writing U32.
*/
//! @{
#define ATPASTE2( a, b) TPASTE2( a, b)
#define ATPASTE3( a, b, c) TPASTE3( a, b, c)
#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)
#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)
#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)
#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)
#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)
#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)
#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)
//! @}
#endif // _TPASTE_H_
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor token pasting utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _TPASTE_H_
#define _TPASTE_H_
/*! \name Token Paste
*
* Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
*
* May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
*
* For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
* UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
* equivalent to writing U32.
*/
//! @{
#define TPASTE2( a, b) a##b
#define TPASTE3( a, b, c) a##b##c
#define TPASTE4( a, b, c, d) a##b##c##d
#define TPASTE5( a, b, c, d, e) a##b##c##d##e
#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f
#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g
#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h
#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i
#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j
//! @}
/*! \name Absolute Token Paste
*
* Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
*
* No restriction of use if the tokens are \#defined.
*
* For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
* as 32 is equivalent to writing U32.
*/
//! @{
#define ATPASTE2( a, b) TPASTE2( a, b)
#define ATPASTE3( a, b, c) TPASTE3( a, b, c)
#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)
#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)
#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)
#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)
#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)
#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)
#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)
//! @}
#endif // _TPASTE_H_

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src/platform/avr32/usart.c
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src/platform/avr32/usart.h
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