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Updated driver library (except for UART/USART).

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This commit is contained in:
James Snyder 2009-08-03 18:37:38 +00:00
parent 179042bc45
commit 9eddff8847
59 changed files with 64585 additions and 18790 deletions
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4
SConstruct
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@ -54,7 +54,7 @@ toolchain_list['devkitarm'] = toolchain_list['arm-eabi-gcc']
# (the one that will be used if none is specified)
platform_list = {
'at91sam7x' : { 'cpus' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
'lm3s' : { 'cpus' : [ 'LM3S8962', 'LM3S6965', 'LM3S6918', 'LM3S9B92' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
'str9' : { 'cpus' : [ 'STR912FAW44' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] },
'i386' : { 'cpus' : [ 'I386' ], 'toolchains' : [ 'i686-gcc' ] },
'sim' : { 'cpus' : [ 'LINUX' ], 'toolchains' : [ 'i686-gcc' ] },
@ -68,6 +68,7 @@ platform_list = {
board_list = { 'SAM7-EX256' : [ 'AT91SAM7X256', 'AT91SAM7X512' ],
'EK-LM3S8962' : [ 'LM3S8962' ],
'EK-LM3S6965' : [ 'LM3S6965' ],
'EK-LM3S9B92' : [ 'LM3S9B92' ],
'STR9-COMSTICK' : [ 'STR912FAW44' ],
'PC' : [ 'I386' ],
'SIM' : [ 'LINUX' ],
@ -104,6 +105,7 @@ romfs = { 'bisect' : [ 'bisect.lua' ],
file_list = { 'SAM7-EX256' : [ 'bisect', 'hangman' , 'led', 'piano', 'hello', 'info', 'morse' ],
'EK-LM3S8962' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope','adcpoll' ],
'EK-LM3S6965' : [ 'bisect', 'hangman', 'lhttpd', 'pong', 'led', 'piano', 'pwmled', 'tvbgone', 'hello', 'info', 'morse', 'adcscope','adcpoll' ],
'EK-LM3S9B92' : [ 'bisect', 'hangman', 'lhttpd', 'led', 'hello', 'info', 'adcscope','adcpoll' ],
'STR9-COMSTICK' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ],
'PC' : [ 'bisect', 'hello', 'info', 'life', 'hangman' ],
'SIM' : [ 'bisect', 'hello', 'info', 'life', 'hangman' ],

400
src/platform/lm3s/adc.c Normal file → Executable file
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@ -2,7 +2,7 @@
//
// adc.c - Driver for the ADC.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -52,6 +52,8 @@
#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)
#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
#define ADC_SSOP (ADC_O_SSOP0 - ADC_O_SSMUX0)
#define ADC_SSDC (ADC_O_SSDC0 - ADC_O_SSMUX0)
//*****************************************************************************
//
@ -91,7 +93,7 @@ ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -135,7 +137,7 @@ ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -172,7 +174,7 @@ ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -201,7 +203,7 @@ ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -235,10 +237,12 @@ unsigned long
ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
tBoolean bMasked)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -247,12 +251,27 @@ ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
//
if(bMasked)
{
return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum));
ulTemp = HWREG(ulBase + ADC_O_ISC) & (0x10001 << ulSequenceNum);
}
else
{
return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum));
ulTemp = HWREG(ulBase + ADC_O_RIS) & (0x10000 | (1 << ulSequenceNum));
//
// If the Digital Comparator status bit is set, reflect it to the
// appropriate sequence bit.
//
if(ulTemp & 0x10000)
{
ulTemp |= 0xF0000;
ulTemp &= ~(0x10000 << ulSequenceNum);
}
}
//
// Return the interrupt status
//
return(ulTemp);
}
//*****************************************************************************
@ -284,7 +303,7 @@ ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Check the arugments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -312,7 +331,7 @@ ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Check the arugments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -340,7 +359,7 @@ ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Check the arugments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -409,7 +428,7 @@ ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
//
// Check the arugments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) ||
(ulTrigger == ADC_TRIGGER_COMP0) ||
@ -452,18 +471,29 @@ ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
//! \param ulStep is the step to be configured.
//! \param ulConfig is the configuration of this step; must be a logical OR of
//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7).
//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH15). For parts
//! with the Digital Comparator feature, the follow values may also be OR'd
//! into the \e ulConfig value to enable the Digital Comparater feature:
//! \b ADC_CTL_CE and one of the comparater selects (\b ADC_CTL_CMP0 through
//! \b ADC_CTL_CMP7).
//!
//! This function will set the configuration of the ADC for one step of a
//! sample sequence. The ADC can be configured for single-ended or
//! differential operation (the \b ADC_CTL_D bit selects differential
//! operation when set), the channel to be sampled can be chosen (the
//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature
//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step
//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it
//! can be configured to cause an interrupt when the step is complete (the
//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the
//! appropriate time when the trigger for this sequence occurs.
//! \b ADC_CTL_CH0 through \b ADC_CTL_CH15 values), and the internal
//! temperature sensor can be selected (the \b ADC_CTL_TS bit). Additionally,
//! this step can be defined as the last in the sequence (the \b ADC_CTL_END
//! bit) and it can be configured to cause an interrupt when the step is
//! complete (the \b ADC_CTL_IE bit). If the Digital Comparators are present
//! on the device, this step may also be configured send the ADC sample to
//! the selected comparator (the \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7
//! values) by using the \b ADC_CTL_CE bit. The configuration is used by the
//! ADC at the appropriate time when the trigger for this sequence occurs.
//!
//! \note If the Digitial Comparator is present and enabled using the
//! \b ADC_CTL_CE bit, the ADC sample will NOT be written into the ADC
//! sequence data FIFO.
//!
//! The \e ulStep parameter determines the order in which the samples are
//! captured by the ADC when the trigger occurs. It can range from zero to
@ -488,10 +518,12 @@ void
ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
unsigned long ulStep, unsigned long ulConfig)
{
unsigned long ulTemp;
//
// Check the arugments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) ||
((ulSequenceNum == 1) && (ulStep < 4)) ||
@ -521,6 +553,37 @@ ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
~(0x0000000f << ulStep)) |
(((ulConfig & 0xf0) >> 4) << ulStep));
//
// Enable Digital Comparator if specified in the ulConfig bit-fields.
//
if(ulConfig & 0x000F0000)
{
//
// Program the comparator for the specified step.
//
ulTemp = HWREG(ulBase + ADC_SSDC);
ulTemp &= ~(0xF << ulStep);
ulTemp |= (((ulConfig & 0x00070000) >> 16) << ulStep);
HWREG(ulBase + ADC_SSDC) = ulTemp;
//
// Enable the comparator.
//
ulTemp = HWREG(ulBase + ADC_SSOP);
ulTemp |= (1 << ulStep);
HWREG(ulBase + ADC_SSOP) = ulTemp;
}
//
// Disable Digital Comparator if not specified.
//
else
{
ulTemp = HWREG(ulBase + ADC_SSOP);
ulTemp &= ~(1 << ulStep);
HWREG(ulBase + ADC_SSOP) = ulTemp;
}
}
//*****************************************************************************
@ -544,7 +607,7 @@ ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -573,7 +636,7 @@ ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -602,7 +665,7 @@ ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -631,7 +694,7 @@ ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -667,7 +730,7 @@ ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -717,7 +780,7 @@ ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
@ -759,7 +822,7 @@ ADCSoftwareOversampleConfigure(unsigned long ulBase,
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 3);
ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) &&
((ulSequenceNum == 0) || (ulFactor != 8)));
@ -803,7 +866,7 @@ ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 3);
ASSERT(((ulSequenceNum == 0) &&
(ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
@ -881,7 +944,7 @@ ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 3);
ASSERT(((ulSequenceNum == 0) &&
(ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
@ -953,7 +1016,7 @@ ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
//
// Check the arguments.
//
ASSERT(ulBase == ADC_BASE);
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) ||
(ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) ||
(ulFactor == 64)));
@ -971,6 +1034,281 @@ ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
HWREG(ulBase + ADC_O_SAC) = ulValue;
}
//*****************************************************************************
//
//! Configures an ADC Digital Comparator.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulComp is the index of the comparator to configure.
//! \param ulConfig is the configuration of the comparator.
//!
//! This function will configure a comparator. The \e ulConfig parameter is
//! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and
//! \b ADC_COMP_INT_xxx values.
//!
//! The \b ADC_COMP_TRIG_xxx term can take on the following values:
//!
//! - \b ADC_COMP_TRIG_NONE to never trigger PWM fault condition.
//! - \b ADC_COMP_TRIG_LOW_ALWAYS to always trigger PWM fault condition when
//! ADC output is in the low-band.
//! - \b ADC_COMP_TRIG_LOW_ONCE to trigger PWM fault condition once when ADC
//! output transitions into the low-band.
//! - \b ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when
//! ADC output is in the low-band only if ADC output has been in the high-band
//! since the last trigger output.
//! - \b ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC
//! output transitions into low-band only if ADC output has been in the
//! high-band since the last trigger output.
//! - \b ADC_COMP_TRIG_MID_ALWAYS to always trigger PWM fault condition when
//! ADC output is in the mid-band.
//! - \b ADC_COMP_TRIG_MID_ONCE to trigger PWM fault condition once when ADC
//! output transitions into the mid-band.
//! - \b ADC_COMP_TRIG_HIGH_ALWAYS to always trigger PWM fault condition when
//! ADC output is in the high-band.
//! - \b ADC_COMP_TRIG_HIGH_ONCE to trigger PWM fault condition once when ADC
//! output transitions into the high-band.
//! - \b ADC_COMP_TRIG_HIGH_HALWAYS to always trigger PWM fault condition when
//! ADC output is in the high-band only if ADC output has been in the low-band
//! since the last trigger output.
//! - \b ADC_COMP_TRIG_HIGH_HONCE to trigger PWM fault condition once when ADC
//! output transitions into high-band only if ADC output has been in the
//! low-band since the last trigger output.
//!
//! The \b ADC_COMP_INT_xxx term can take on the following values:
//!
//! - \b ADC_COMP_INT_NONE to never generate ADC interrupt.
//! - \b ADC_COMP_INT_LOW_ALWAYS to always generate ADC interrupt when ADC
//! output is in the low-band.
//! - \b ADC_COMP_INT_LOW_ONCE to generate ADC interrupt once when ADC output
//! transitions into the low-band.
//! - \b ADC_COMP__INT_LOW_HALWAYS to always generate ADC interrupt when ADC
//! output is in the low-band only if ADC output has been in the high-band
//! since the last trigger output.
//! - \b ADC_COMP_INT_LOW_HONCE to generate ADC interrupt once when ADC output
//! transitions into low-band only if ADC output has been in the high-band
//! since the last trigger output.
//! - \b ADC_COMP_INT_MID_ALWAYS to always generate ADC interrupt when ADC
//! output is in the mid-band.
//! - \b ADC_COMP_INT_MID_ONCE to generate ADC interrupt once when ADC output
//! transitions into the mid-band.
//! - \b ADC_COMP_INT_HIGH_ALWAYS to always generate ADC interrupt when ADC
//! output is in the high-band.
//! - \b ADC_COMP_INT_HIGH_ONCE to generate ADC interrupt once when ADC output
//! transitions into the high-band.
//! - \b ADC_COMP_INT_HIGH_HALWAYS to always generate ADC interrupt when ADC
//! output is in the high-band only if ADC output has been in the low-band
//! since the last trigger output.
//! - \b ADC_COMP_INT_HIGH_HONCE to generate ADC interrupt once when ADC output
//! transitions into high-band only if ADC output has been in the low-band
//! since the last trigger output.
//!
//! \return None.
//
//*****************************************************************************
void
ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulComp < 8);
//
// Save the new setting.
//
HWREG(ulBase + ADC_O_DCCTL0 + (ulComp * 4)) = ulConfig;
}
//*****************************************************************************
//
//! Define the ADC Digital Comparator Regions.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulComp is the index of the comparator to configure.
//! \param ulLowRef is the reference point for the low/mid band threshold.
//! \param ulHighRef is the reference point for the mid/high band threshold.
//!
//! The ADC Digital Comparator operation is based on three ADC value regions:
//! - \b low-band is defined as any ADC value less than or equal to the
//! \e ulLowRef value.
//! - \b mid-band is defined as any ADC value greater than the \e ulLowRef
//! value but less than or equal to the \e ulHighRef value.
//! - \b high-band is defined as any ADC value greater than the \e ulHighRef
//! value.
//!
//! \return None.
//
//*****************************************************************************
void
ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
unsigned long ulLowRef, unsigned long ulHighRef)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulComp < 8);
ASSERT((ulLowRef < 1024) && (ulLowRef <= ulHighRef));
ASSERT(ulHighRef < 1024);
//
// Save the new region settings.
//
HWREG(ulBase + ADC_O_DCCMP0 + (ulComp * 4)) = (ulHighRef << 16) | ulLowRef;
}
//*****************************************************************************
//
//! Resets the current ADC Digital Comparator conditions.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulComp is the index of the comparator.
//! \param bTrigger is the flag to indicate reset of Trigger conditions.
//! \param bInterrupt is the flag to indicate reset of Interrupt conditions.
//!
//! Because the Digital Comparator uses current and previous ADC values, this
//! function is provide to allow the comparator to be reset to its initial
//! value to prevent stale data from being used when a sequence is enabled.
//!
//! \return None.
//
//*****************************************************************************
void
ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
tBoolean bTrigger, tBoolean bInterrupt)
{
unsigned long ulTemp = 0;
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulComp < 8);
//
// Set the appropriate bits to reset the trigger and/or interrupt
// comparator conditions.
//
if(bTrigger)
{
ulTemp |= (1 << (16 + ulComp));
}
if(bInterrupt)
{
ulTemp |= (1 << ulComp);
}
HWREG(ulBase + ADC_O_DCRIC) = ulTemp;
}
//*****************************************************************************
//
//! Disables a sample sequence comparator interrupt.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This function disables the requested sample sequence comparator interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
ADCComparatorIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Disable this sample sequence comparator interrupt.
//
HWREG(ulBase + ADC_O_IM) &= ~(0x10000 << ulSequenceNum);
}
//*****************************************************************************
//
//! Enables a sample sequence comparator interrupt.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This function enables the requested sample sequence comparator interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
ADCComparatorIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT(ulSequenceNum < 4);
//
// Enable this sample sequence interrupt.
//
HWREG(ulBase + ADC_O_IM) |= 0x10000 << ulSequenceNum;
}
//*****************************************************************************
//
//! Gets the current comparator interrupt status.
//!
//! \param ulBase is the base address of the ADC module.
//!
//! This returns the Digitial Comparator interrupt status bits. This status
//! is sequence agnostic.
//!
//! \return The current comparator interrupt status.
//
//*****************************************************************************
unsigned long
ADCComparatorIntStatus(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
//
// Return the digitial comparator interrupt status.
//
return(HWREG(ulBase + ADC_O_DCISC));
}
//*****************************************************************************
//
//! Clears sample sequence comparator interrupt source.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulStatus is the bit-mapped interrupts status to clear.
//!
//! The specified interrupt status is cleared.
//!
//! \return None.
//
//*****************************************************************************
void
ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus)
{
//
// Check the arugments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
//
// Clear the interrupt.
//
HWREG(ulBase + ADC_O_DCISC) = ulStatus;
}
//*****************************************************************************
//
// Close the Doxygen group.

79
src/platform/lm3s/adc.h Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -74,6 +74,66 @@ extern "C"
#define ADC_CTL_CH5 0x00000005 // Input channel 5
#define ADC_CTL_CH6 0x00000006 // Input channel 6
#define ADC_CTL_CH7 0x00000007 // Input channel 7
#define ADC_CTL_CH8 0x00000008 // Input channel 8
#define ADC_CTL_CH9 0x00000009 // Input channel 9
#define ADC_CTL_CH10 0x0000000A // Input channel 10
#define ADC_CTL_CH11 0x0000000B // Input channel 11
#define ADC_CTL_CH12 0x0000000C // Input channel 12
#define ADC_CTL_CH13 0x0000000D // Input channel 13
#define ADC_CTL_CH14 0x0000000E // Input channel 14
#define ADC_CTL_CH15 0x0000000F // Input channel 15
#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3
#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4
#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5
#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6
#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7
//*****************************************************************************
//
// Values that can be passed to ADCComparatorConfigure as part of the
// ulConfig parameter.
//
//*****************************************************************************
#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled
#define ADC_COMP_TRIG_LOW_ALWAYS \
0x00001000 // Trigger Low Always
#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once
#define ADC_COMP_TRIG_LOW_HALWAYS \
0x00001200 // Trigger Low Always (Hysteresis)
#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis)
#define ADC_COMP_TRIG_MID_ALWAYS \
0x00001400 // Trigger Mid Always
#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once
#define ADC_COMP_TRIG_HIGH_ALWAYS \
0x00001C00 // Trigger High Always
#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once
#define ADC_COMP_TRIG_HIGH_HALWAYS \
0x00001E00 // Trigger High Always (Hysteresis)
#define ADC_COMP_TRIG_HIGH_HONCE \
0x00001F00 // Trigger High Once (Hysteresis)
#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled
#define ADC_COMP_INT_LOW_ALWAYS \
0x00000010 // Interrupt Low Always
#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once
#define ADC_COMP_INT_LOW_HALWAYS \
0x00000012 // Interrupt Low Always
// (Hysteresis)
#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis)
#define ADC_COMP_INT_MID_ALWAYS \
0x00000014 // Interrupt Mid Always
#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once
#define ADC_COMP_INT_HIGH_ALWAYS \
0x0000001C // Interrupt High Always
#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once
#define ADC_COMP_INT_HIGH_HALWAYS \
0x0000001E // Interrupt High Always
// (Hysteresis)
#define ADC_COMP_INT_HIGH_HONCE \
0x0000001F // Interrupt High Once (Hysteresis)
//*****************************************************************************
//
@ -128,6 +188,21 @@ extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
unsigned long ulCount);
extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
unsigned long ulFactor);
extern void ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig);
extern void ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
unsigned long ulLowRef,
unsigned long ulHighRef);
extern void ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
tBoolean bTrigger, tBoolean bInterrupt);
extern void ADCComparatorIntDisable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCComparatorIntEnable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern unsigned long ADCComparatorIntStatus(unsigned long ulBase);
extern void ADCComparatorIntClear(unsigned long ulBase,
unsigned long ulStatus);
//*****************************************************************************
//

2203
src/platform/lm3s/can.c Executable file
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458
src/platform/lm3s/can.h Executable file
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@ -0,0 +1,458 @@
//*****************************************************************************
//
// can.h - Defines and Macros for the CAN controller.
//
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __CAN_H__
#define __CAN_H__
//*****************************************************************************
//
//! \addtogroup can_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Miscellaneous defines for Message ID Types
//
//*****************************************************************************
//*****************************************************************************
//
//! These are the flags used by the tCANMsgObject variable when calling the
//! CANMessageSet() and CANMessageGet() functions.
//
//*****************************************************************************
typedef enum
{
//
//! This indicates that transmit interrupts should be enabled, or are
//! enabled.
//
MSG_OBJ_TX_INT_ENABLE = 0x00000001,
//
//! This indicates that receive interrupts should be enabled, or are
//! enabled.
//
MSG_OBJ_RX_INT_ENABLE = 0x00000002,
//
//! This indicates that a message object will use or is using an extended
//! identifier.
//
MSG_OBJ_EXTENDED_ID = 0x00000004,
//
//! This indicates that a message object will use or is using filtering
//! based on the object's message identifier.
//
MSG_OBJ_USE_ID_FILTER = 0x00000008,
//
//! This indicates that new data was available in the message object.
//
MSG_OBJ_NEW_DATA = 0x00000080,
//
//! This indicates that data was lost since this message object was last
//! read.
//
MSG_OBJ_DATA_LOST = 0x00000100,
//
//! This indicates that a message object will use or is using filtering
//! based on the direction of the transfer. If the direction filtering is
//! used, then ID filtering must also be enabled.
//
MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),
//
//! This indicates that a message object will use or is using message
//! identifier filtering based on the extended identifier. If the extended
//! identifier filtering is used, then ID filtering must also be enabled.
//
MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),
//
//! This indicates that a message object is a remote frame.
//
MSG_OBJ_REMOTE_FRAME = 0x00000040,
//
//! This indicates that a message object has no flags set.
//
MSG_OBJ_NO_FLAGS = 0x00000000
}
tCANObjFlags;
//*****************************************************************************
//
//! This define is used with the #tCANObjFlags enumerated values to allow
//! checking only status flags and not configuration flags.
//
//*****************************************************************************
#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
//*****************************************************************************
//
//! The structure used for encapsulating all the items associated with a CAN
//! message object in the CAN controller.
//
//*****************************************************************************
typedef struct
{
//
//! The CAN message identifier used for 11 or 29 bit identifiers.
//
unsigned long ulMsgID;
//
//! The message identifier mask used when identifier filtering is enabled.
//
unsigned long ulMsgIDMask;
//
//! This value holds various status flags and settings specified by
//! tCANObjFlags.
//
unsigned long ulFlags;
//
//! This value is the number of bytes of data in the message object.
//
unsigned long ulMsgLen;
//
//! This is a pointer to the message object's data.
//
unsigned char *pucMsgData;
}
tCANMsgObject;
//*****************************************************************************
//
//! This structure is used for encapsulating the values associated with setting
//! up the bit timing for a CAN controller. The structure is used when calling
//! the CANGetBitTiming and CANSetBitTiming functions.
//
//*****************************************************************************
typedef struct
{
//
//! This value holds the sum of the Synchronization, Propagation, and Phase
//! Buffer 1 segments, measured in time quanta. The valid values for this
//! setting range from 2 to 16.
//
unsigned int uSyncPropPhase1Seg;
//
//! This value holds the Phase Buffer 2 segment in time quanta. The valid
//! values for this setting range from 1 to 8.
//
unsigned int uPhase2Seg;
//
//! This value holds the Resynchronization Jump Width in time quanta. The
//! valid values for this setting range from 1 to 4.
//
unsigned int uSJW;
//
//! This value holds the CAN_CLK divider used to determine time quanta.
//! The valid values for this setting range from 1 to 1023.
//
unsigned int uQuantumPrescaler;
}
tCANBitClkParms;
//*****************************************************************************
//
//! This data type is used to identify the interrupt status register. This is
//! used when calling the CANIntStatus() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the CAN interrupt status information.
//
CAN_INT_STS_CAUSE,
//
//! Read a message object's interrupt status.
//
CAN_INT_STS_OBJECT
}
tCANIntStsReg;
//*****************************************************************************
//
//! This data type is used to identify which of several status registers to
//! read when calling the CANStatusGet() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the full CAN controller status.
//
CAN_STS_CONTROL,
//
//! Read the full 32-bit mask of message objects with a transmit request
//! set.
//
CAN_STS_TXREQUEST,
//
//! Read the full 32-bit mask of message objects with new data available.
//
CAN_STS_NEWDAT,
//
//! Read the full 32-bit mask of message objects that are enabled.
//
CAN_STS_MSGVAL
}
tCANStsReg;
//*****************************************************************************
//
//! These definitions are used to specify interrupt sources to CANIntEnable()
//! and CANIntDisable().
//
//*****************************************************************************
typedef enum
{
//
//! This flag is used to allow a CAN controller to generate error
//! interrupts.
//
CAN_INT_ERROR = 0x00000008,
//
//! This flag is used to allow a CAN controller to generate status
//! interrupts.
//
CAN_INT_STATUS = 0x00000004,
//
//! This flag is used to allow a CAN controller to generate any CAN
//! interrupts. If this is not set, then no interrupts will be generated
//! by the CAN controller.
//
CAN_INT_MASTER = 0x00000002
}
tCANIntFlags;
//*****************************************************************************
//
//! This definition is used to determine the type of message object that will
//! be set up via a call to the CANMessageSet() API.
//
//*****************************************************************************
typedef enum
{
//
//! Transmit message object.
//
MSG_OBJ_TYPE_TX,
//
//! Transmit remote request message object
//
MSG_OBJ_TYPE_TX_REMOTE,
//
//! Receive message object.
//
MSG_OBJ_TYPE_RX,
//
//! Receive remote request message object.
//
MSG_OBJ_TYPE_RX_REMOTE,
//
//! Remote frame receive remote, with auto-transmit message object.
//
MSG_OBJ_TYPE_RXTX_REMOTE
}
tMsgObjType;
//*****************************************************************************
//
//! The following enumeration contains all error or status indicators that can
//! be returned when calling the CANStatusGet() function.
//
//*****************************************************************************
typedef enum
{
//
//! CAN controller has entered a Bus Off state.
//
CAN_STATUS_BUS_OFF = 0x00000080,
//
//! CAN controller error level has reached warning level.
//
CAN_STATUS_EWARN = 0x00000040,
//
//! CAN controller error level has reached error passive level.
//
CAN_STATUS_EPASS = 0x00000020,
//
//! A message was received successfully since the last read of this status.
//
CAN_STATUS_RXOK = 0x00000010,
//
//! A message was transmitted successfully since the last read of this
//! status.
//
CAN_STATUS_TXOK = 0x00000008,
//
//! This is the mask for the last error code field.
//
CAN_STATUS_LEC_MSK = 0x00000007,
//
//! There was no error.
//
CAN_STATUS_LEC_NONE = 0x00000000,
//
//! A bit stuffing error has occurred.
//
CAN_STATUS_LEC_STUFF = 0x00000001,
//
//! A formatting error has occurred.
//
CAN_STATUS_LEC_FORM = 0x00000002,
//
//! An acknowledge error has occurred.
//
CAN_STATUS_LEC_ACK = 0x00000003,
//
//! The bus remained a bit level of 1 for longer than is allowed.
//
CAN_STATUS_LEC_BIT1 = 0x00000004,
//
//! The bus remained a bit level of 0 for longer than is allowed.
//
CAN_STATUS_LEC_BIT0 = 0x00000005,
//
//! A CRC error has occurred.
//
CAN_STATUS_LEC_CRC = 0x00000006,
//
//! This is the mask for the CAN Last Error Code (LEC).
//
CAN_STATUS_LEC_MASK = 0x00000007
}
tCANStatusCtrl;
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms);
extern void CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms);
extern unsigned long CANBitRateSet(unsigned long ulBase,
unsigned long ulSourceClock,
unsigned long ulBitRate);
extern void CANDisable(unsigned long ulBase);
extern void CANEnable(unsigned long ulBase);
extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
unsigned long *pulTxCount);
extern void CANInit(unsigned long ulBase);
extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);
extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern unsigned long CANIntStatus(unsigned long ulBase,
tCANIntStsReg eIntStsReg);
extern void CANIntUnregister(unsigned long ulBase);
extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);
extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);
extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
tCANMsgObject *pMsgObject, tMsgObjType eMsgType);
extern tBoolean CANRetryGet(unsigned long ulBase);
extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);
extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);
//*****************************************************************************
//
// Several CAN APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#define CANSetBitTiming(a, b) CANBitTimingSet(a, b)
#define CANGetBitTiming(a, b) CANBitTimingGet(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __CAN_H__

4
src/platform/lm3s/cpu.c Normal file → Executable file
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@ -3,7 +3,7 @@
// cpu.c - Instruction wrappers for special CPU instructions needed by the
// drivers.
//
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -22,7 +22,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

4
src/platform/lm3s/cpu.h Normal file → Executable file
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@ -2,7 +2,7 @@
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

4
src/platform/lm3s/debug.h Normal file → Executable file
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@ -2,7 +2,7 @@
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

9
src/platform/lm3s/ethernet.c Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// ethernet.c - Driver for the Integrated Ethernet Controller
//
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -32,14 +32,13 @@
//
//*****************************************************************************
#include "hw_ethernet.h"
#include "hw_ints.h"
#include "hw_memmap.h"
#include "hw_types.h"
#include "hw_ethernet.h"
#include "debug.h"
#include "interrupt.h"
#include "sysctl.h"
#include "ethernet.h"
#include "interrupt.h"
//*****************************************************************************
//

4
src/platform/lm3s/ethernet.h Normal file → Executable file
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@ -2,7 +2,7 @@
//
// ethernet.h - Defines and Macros for the ethernet module.
//
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

84
src/platform/lm3s/flash.c Normal file → Executable file
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@ -2,7 +2,7 @@
//
// flash.c - Driver for programming the on-chip flash.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -34,7 +34,6 @@
#include "hw_flash.h"
#include "hw_ints.h"
#include "hw_memmap.h"
#include "hw_sysctl.h"
#include "hw_types.h"
#include "debug.h"
@ -210,30 +209,75 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress,
HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
//
// Loop over the words to be programmed.
// See if this device has a write buffer.
//
while(ulCount)
if(HWREG(SYSCTL_NVMSTAT) & SYSCTL_NVMSTAT_FWB)
{
//
// Program the next word.
// Loop over the words to be programmed.
//
HWREG(FLASH_FMA) = ulAddress;
HWREG(FLASH_FMD) = *pulData;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
//
// Wait until the word has been programmed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE)
while(ulCount)
{
}
//
// Set the address of this block of words.
//
HWREG(FLASH_FMA) = ulAddress & ~(0x7f);
//
// Loop over the words in this 32-word block.
//
while(((ulAddress & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) &&
(ulCount != 0))
{
//
// Write this word into the write buffer.
//
HWREG(FLASH_FWBN + (ulAddress & 0x7c)) = *pulData++;
ulAddress += 4;
ulCount -= 4;
}
//
// Program the contents of the write buffer into flash.
//
HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF;
//
// Wait until the write buffer has been programmed.
//
while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF)
{
}
}
}
else
{
//
// Increment to the next word.
// Loop over the words to be programmed.
//
pulData++;
ulAddress += 4;
ulCount -= 4;
while(ulCount)
{
//
// Program the next word.
//
HWREG(FLASH_FMA) = ulAddress;
HWREG(FLASH_FMD) = *pulData;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
//
// Wait until the word has been programmed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE)
{
}
//
// Increment to the next word.
//
pulData++;
ulAddress += 4;
ulCount -= 4;
}
}
//
@ -313,7 +357,7 @@ FlashProtectGet(unsigned long ulAddress)
//
// This block is marked as execute only (that is, it can not be erased
// or programmed, and the only reads allowed are via the instruction
// fecth interface).
// fetch interface).
//
case 0:
case 1:

2
src/platform/lm3s/flash.h Normal file → Executable file
View File

@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

186
src/platform/lm3s/gpio.c Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// gpio.c - API for GPIO ports
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -35,11 +35,31 @@
#include "hw_gpio.h"
#include "hw_ints.h"
#include "hw_memmap.h"
#include "hw_sysctl.h"
#include "hw_types.h"
#include "debug.h"
#include "gpio.h"
#include "interrupt.h"
//*****************************************************************************
//
// The base addresses of all the GPIO modules. Both the APB and AHB apertures
// are provided.
//
//*****************************************************************************
static const unsigned long g_pulGPIOBaseAddrs[] =
{
GPIO_PORTA_BASE, GPIO_PORTA_AHB_BASE,
GPIO_PORTB_BASE, GPIO_PORTB_AHB_BASE,
GPIO_PORTC_BASE, GPIO_PORTC_AHB_BASE,
GPIO_PORTD_BASE, GPIO_PORTD_AHB_BASE,
GPIO_PORTE_BASE, GPIO_PORTE_AHB_BASE,
GPIO_PORTF_BASE, GPIO_PORTF_AHB_BASE,
GPIO_PORTG_BASE, GPIO_PORTG_AHB_BASE,
GPIO_PORTH_BASE, GPIO_PORTH_AHB_BASE,
GPIO_PORTJ_BASE, GPIO_PORTJ_AHB_BASE,
};
//*****************************************************************************
//
//! \internal
@ -64,7 +84,8 @@ GPIOBaseValid(unsigned long ulPort)
(ulPort == GPIO_PORTE_BASE) || (ulPort == GPIO_PORTE_AHB_BASE) ||
(ulPort == GPIO_PORTF_BASE) || (ulPort == GPIO_PORTF_AHB_BASE) ||
(ulPort == GPIO_PORTG_BASE) || (ulPort == GPIO_PORTG_AHB_BASE) ||
(ulPort == GPIO_PORTH_BASE) || (ulPort == GPIO_PORTH_AHB_BASE));
(ulPort == GPIO_PORTH_BASE) || (ulPort == GPIO_PORTH_AHB_BASE) ||
(ulPort == GPIO_PORTJ_BASE) || (ulPort == GPIO_PORTJ_AHB_BASE));
}
#endif
@ -146,6 +167,13 @@ GPIOGetIntNumber(unsigned long ulPort)
break;
}
case GPIO_PORTJ_BASE:
case GPIO_PORTJ_AHB_BASE:
{
ulInt = INT_GPIOJ;
break;
}
default:
{
return(-1);
@ -851,7 +879,6 @@ GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins)
// Set the pad(s) for analog operation.
//
GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
}
//*****************************************************************************
@ -1298,14 +1325,18 @@ GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins)
//
//! Configures pin(s) for use by the USB peripheral.
//!
//! \param ulPort is the base address of the USB port.
//! \param ulPort is the base address of the GPIO port.
//! \param ucPins is the bit-packed representation of the pin(s).
//!
//! Some USB pins must be properly configured for the USB peripheral to
//! Some USB digital pins must be properly configured for the USB peripheral to
//! function correctly. This function provides a typical configuration for
//! the digital USB pin(s); other configurations may work as well depending
//! upon the board setup (for example, using the on-chip pull-ups).
//!
//! This function should only be used with EPEN and PFAULT pins as all other
//! USB pins are analog in nature or are not used in devices without OTG
//! functionality.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
@ -1335,6 +1366,149 @@ GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins)
GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Configures pin(s) for use by the USB peripheral.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPins is the bit-packed representation of the pin(s).
//!
//! Some USB analog pins must be properly configured for the USB peripheral to
//! function correctly. This function provides the proper configuration for
//! any USB pin(s). This can also be used to configure the EPEN and PFAULT pins
//! so that they are no longer used by the USB controller.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \note This cannot be used to turn any pin into a USB pin; it only
//! configures a USB pin for proper operation.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Make the pin(s) be inputs.
//
GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
//
// Set the pad(s) for analog operation.
//
GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
}
//*****************************************************************************
//
//! Configures pin(s) for use by the I2S peripheral.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPins is the bit-packed representation of the pin(s).
//!
//! Some I2S pins must be properly configured for the I2S peripheral to
//! function correctly. This function provides a typical configuration for
//! the digital I2S pin(s); other configurations may work as well depending
//! upon the board setup (for example, using the on-chip pull-ups).
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \note This cannot be used to turn any pin into a I2S pin; it only
//! configures a I2S pin for proper operation.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Make the pin(s) be peripheral controlled.
//
GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
//
// Set the pad(s) for standard push-pull operation.
//
GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Configures the alternate function of a GPIO pin.
//!
//! \param ulPinConfig is the pin configuration value, specified as one of the
//! \b GPIO_P??_??? values.
//!
//! This function configures the pin mux that selects the peripheral function
//! associated with a particular GPIO pin. Only one peripheral function at a
//! time can be associated with a GPIO pin, and each peripheral function should
//! only be associated with a single GPIO pin at a time (despite the fact that
//! many of them can be associated with more than one GPIO pin).
//!
//! \note This function is only valid on Tempest-class devices.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOPinConfigure(unsigned long ulPinConfig)
{
unsigned long ulBase, ulShift;
//
// Check the argument.
//
ASSERT(((ulPinConfig >> 16) & 0xff) < 9);
ASSERT(((ulPinConfig >> 8) & 0xe3) == 0);
//
// Extract the base address index from the input value.
//
ulBase = (ulPinConfig >> 16) & 0xff;
//
// Get the base address of the GPIO module, selecting either the APB or the
// AHB aperture as appropriate.
//
if(HWREG(SYSCTL_GPIOHSCTL) & (1 << ulBase))
{
ulBase = g_pulGPIOBaseAddrs[(ulBase << 1) + 1];
}
else
{
ulBase = g_pulGPIOBaseAddrs[ulBase << 1];
}
//
// Extract the shift from the input value.
//
ulShift = (ulPinConfig >> 8) & 0xff;
//
// Write the requested pin muxing value for this GPIO pin.
//
HWREG(ulBase + GPIO_O_PCTL) = ((HWREG(ulBase + GPIO_O_PCTL) &
~(0xf << ulShift)) |
((ulPinConfig & 0xf) << ulShift));
}
//*****************************************************************************
//
// Close the Doxygen group.

617
src/platform/lm3s/gpio.h Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -101,6 +101,616 @@ extern "C"
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Values that can be passed to GPIOPinConfigure as the ulPinConfig parameter.
//
//*****************************************************************************
//
// GPIO pin A0
//
#define GPIO_PA0_U0RX 0x00000001
#define GPIO_PA0_I2C1SCL 0x00000008
#define GPIO_PA0_U1RX 0x00000009
//
// GPIO pin A1
//
#define GPIO_PA1_U0TX 0x00000401
#define GPIO_PA1_I2C1SDA 0x00000408
#define GPIO_PA1_U1TX 0x00000409
//
// GPIO pin A2
//
#define GPIO_PA2_SSI0CLK 0x00000801
#define GPIO_PA2_PWM4 0x00000804
#define GPIO_PA2_I2S0RXSD 0x00000809
//
// GPIO pin A3
//
#define GPIO_PA3_SSI0FSS 0x00000c01
#define GPIO_PA3_PWM5 0x00000c04
#define GPIO_PA3_I2S0RXMCLK 0x00000c09
//
// GPIO pin A4
//
#define GPIO_PA4_SSI0RX 0x00001001
#define GPIO_PA4_PWM6 0x00001004
#define GPIO_PA4_CAN0RX 0x00001005
#define GPIO_PA4_I2S0TXSCK 0x00001009
//
// GPIO pin A5
//
#define GPIO_PA5_SSI0TX 0x00001401
#define GPIO_PA5_PWM7 0x00001404
#define GPIO_PA5_CAN0TX 0x00001405
#define GPIO_PA5_I2S0TXWS 0x00001409
//
// GPIO pin A6
//
#define GPIO_PA6_I2C1SCL 0x00001801
#define GPIO_PA6_CCP1 0x00001802
#define GPIO_PA6_PWM0 0x00001804
#define GPIO_PA6_PWM4 0x00001805
#define GPIO_PA6_CAN0RX 0x00001806
#define GPIO_PA6_USB0EPEN 0x00001808
#define GPIO_PA6_U1CTS 0x00001809
//
// GPIO pin A7
//
#define GPIO_PA7_I2C1SDA 0x00001c01
#define GPIO_PA7_CCP4 0x00001c02
#define GPIO_PA7_PWM1 0x00001c04
#define GPIO_PA7_PWM5 0x00001c05
#define GPIO_PA7_CAN0TX 0x00001c06
#define GPIO_PA7_CCP3 0x00001c07
#define GPIO_PA7_USB0PFLT 0x00001c08
#define GPIO_PA7_U1DCD 0x00001c09
//
// GPIO pin B0
//
#define GPIO_PB0_CCP0 0x00010001
#define GPIO_PB0_PWM2 0x00010002
#define GPIO_PB0_U1RX 0x00010005
//
// GPIO pin B1
//
#define GPIO_PB1_CCP2 0x00010401
#define GPIO_PB1_PWM3 0x00010402
#define GPIO_PB1_CCP1 0x00010404
#define GPIO_PB1_U1TX 0x00010405
//
// GPIO pin B2
//
#define GPIO_PB2_I2C0SCL 0x00010801
#define GPIO_PB2_IDX0 0x00010802
#define GPIO_PB2_CCP3 0x00010804
#define GPIO_PB2_CCP0 0x00010805
#define GPIO_PB2_USB0EPEN 0x00010808
//
// GPIO pin B3
//
#define GPIO_PB3_I2C0SDA 0x00010c01
#define GPIO_PB3_FAULT0 0x00010c02
#define GPIO_PB3_FAULT3 0x00010c04
#define GPIO_PB3_USB0PFLT 0x00010c08
//
// GPIO pin B4
//
#define GPIO_PB4_U2RX 0x00011004
#define GPIO_PB4_CAN0RX 0x00011005
#define GPIO_PB4_IDX0 0x00011006
#define GPIO_PB4_U1RX 0x00011007
#define GPIO_PB4_EPI0S23 0x00011008
//
// GPIO pin B5
//
#define GPIO_PB5_C0O 0x00011401
#define GPIO_PB5_CCP5 0x00011402
#define GPIO_PB5_CCP6 0x00011403
#define GPIO_PB5_CCP0 0x00011404
#define GPIO_PB5_CAN0TX 0x00011405
#define GPIO_PB5_CCP2 0x00011406
#define GPIO_PB5_U1TX 0x00011407
#define GPIO_PB5_EPI0S22 0x00011408
//
// GPIO pin B6
//
#define GPIO_PB6_CCP1 0x00011801
#define GPIO_PB6_CCP7 0x00011802
#define GPIO_PB6_C0O 0x00011803
#define GPIO_PB6_FAULT1 0x00011804
#define GPIO_PB6_IDX0 0x00011805
#define GPIO_PB6_CCP5 0x00011806
#define GPIO_PB6_I2S0TXSCK 0x00011809
//
// GPIO pin B7
//
#define GPIO_PB7_NMI 0x00011c04
//
// GPIO pin C0
//
#define GPIO_PC0_TCK 0x00020003
//
// GPIO pin C1
//
#define GPIO_PC1_TMS 0x00020403
//
// GPIO pin C2
//
#define GPIO_PC2_TDI 0x00020803
//
// GPIO pin C3
//
#define GPIO_PC3_TDO 0x00020c03
//
// GPIO pin C4
//
#define GPIO_PC4_CCP5 0x00021001
#define GPIO_PC4_PHA0 0x00021002
#define GPIO_PC4_PWM6 0x00021004
#define GPIO_PC4_CCP2 0x00021005
#define GPIO_PC4_CCP4 0x00021006
#define GPIO_PC4_EPI0S2 0x00021008
#define GPIO_PC4_CCP1 0x00021009
//
// GPIO pin C5
//
#define GPIO_PC5_CCP1 0x00021401
#define GPIO_PC5_C1O 0x00021402
#define GPIO_PC5_C0O 0x00021403
#define GPIO_PC5_FAULT2 0x00021404
#define GPIO_PC5_CCP3 0x00021405
#define GPIO_PC5_USB0EPEN 0x00021406
#define GPIO_PC5_EPI0S3 0x00021408
//
// GPIO pin C6
//
#define GPIO_PC6_CCP3 0x00021801
#define GPIO_PC6_PHB0 0x00021802
#define GPIO_PC6_C2O 0x00021803
#define GPIO_PC6_PWM7 0x00021804
#define GPIO_PC6_U1RX 0x00021805
#define GPIO_PC6_CCP0 0x00021806
#define GPIO_PC6_USB0PFLT 0x00021807
#define GPIO_PC6_EPI0S4 0x00021808
//
// GPIO pin C7
//
#define GPIO_PC7_CCP4 0x00021c01
#define GPIO_PC7_PHB0 0x00021c02
#define GPIO_PC7_CCP0 0x00021c04
#define GPIO_PC7_U1TX 0x00021c05
#define GPIO_PC7_USB0PFLT 0x00021c06
#define GPIO_PC7_C1O 0x00021c07
#define GPIO_PC7_EPI0S5 0x00021c08
//
// GPIO pin D0
//
#define GPIO_PD0_PWM0 0x00030001
#define GPIO_PD0_CAN0RX 0x00030002
#define GPIO_PD0_IDX0 0x00030003
#define GPIO_PD0_U2RX 0x00030004
#define GPIO_PD0_U1RX 0x00030005
#define GPIO_PD0_CCP6 0x00030006
#define GPIO_PD0_I2S0RXSCK 0x00030008
#define GPIO_PD0_U1CTS 0x00030009
//
// GPIO pin D1
//
#define GPIO_PD1_PWM1 0x00030401
#define GPIO_PD1_CAN0TX 0x00030402
#define GPIO_PD1_PHA0 0x00030403
#define GPIO_PD1_U2TX 0x00030404
#define GPIO_PD1_U1TX 0x00030405
#define GPIO_PD1_CCP7 0x00030406
#define GPIO_PD1_I2S0RXWS 0x00030408
#define GPIO_PD1_U1DCD 0x00030409
#define GPIO_PD1_CCP2 0x0003040a
#define GPIO_PD1_PHB1 0x0003040b
//
// GPIO pin D2
//
#define GPIO_PD2_U1RX 0x00030801
#define GPIO_PD2_CCP6 0x00030802
#define GPIO_PD2_PWM2 0x00030803
#define GPIO_PD2_CCP5 0x00030804
#define GPIO_PD2_EPI0S20 0x00030808
//
// GPIO pin D3
//
#define GPIO_PD3_U1TX 0x00030c01
#define GPIO_PD3_CCP7 0x00030c02
#define GPIO_PD3_PWM3 0x00030c03
#define GPIO_PD3_CCP0 0x00030c04
#define GPIO_PD3_EPI0S21 0x00030c08
//
// GPIO pin D4
//
#define GPIO_PD4_CCP0 0x00031001
#define GPIO_PD4_CCP3 0x00031002
#define GPIO_PD4_I2S0RXSD 0x00031008
#define GPIO_PD4_U1RI 0x00031009
#define GPIO_PD4_EPI0S19 0x0003100a
//
// GPIO pin D5
//
#define GPIO_PD5_CCP2 0x00031401
#define GPIO_PD5_CCP4 0x00031402
#define GPIO_PD5_I2S0RXMCLK 0x00031408
#define GPIO_PD5_U2RX 0x00031409
#define GPIO_PD5_EPI0S28 0x0003140a
//
// GPIO pin D6
//
#define GPIO_PD6_FAULT0 0x00031801
#define GPIO_PD6_I2S0TXSCK 0x00031808
#define GPIO_PD6_U2TX 0x00031809
#define GPIO_PD6_EPI0S29 0x0003180a
//
// GPIO pin D7
//
#define GPIO_PD7_IDX0 0x00031c01
#define GPIO_PD7_C0O 0x00031c02
#define GPIO_PD7_CCP1 0x00031c03
#define GPIO_PD7_I2S0TXWS 0x00031c08
#define GPIO_PD7_U1DTR 0x00031c09
#define GPIO_PD7_EPI0S30 0x00031c0a
//
// GPIO pin E0
//
#define GPIO_PE0_PWM4 0x00040001
#define GPIO_PE0_SSI1CLK 0x00040002
#define GPIO_PE0_CCP3 0x00040003
#define GPIO_PE0_EPI0S8 0x00040008
#define GPIO_PE0_USB0PFLT 0x00040009
//
// GPIO pin E1
//
#define GPIO_PE1_PWM5 0x00040401
#define GPIO_PE1_SSI1FSS 0x00040402
#define GPIO_PE1_FAULT0 0x00040403
#define GPIO_PE1_CCP2 0x00040404
#define GPIO_PE1_CCP6 0x00040405
#define GPIO_PE1_EPI0S9 0x00040408
//
// GPIO pin E2
//
#define GPIO_PE2_CCP4 0x00040801
#define GPIO_PE2_SSI1RX 0x00040802
#define GPIO_PE2_PHB1 0x00040803
#define GPIO_PE2_PHA0 0x00040804
#define GPIO_PE2_CCP2 0x00040805
#define GPIO_PE2_EPI0S24 0x00040808
//
// GPIO pin E3
//
#define GPIO_PE3_CCP1 0x00040c01
#define GPIO_PE3_SSI1TX 0x00040c02
#define GPIO_PE3_PHA1 0x00040c03
#define GPIO_PE3_PHB0 0x00040c04
#define GPIO_PE3_CCP7 0x00040c05
#define GPIO_PE3_EPI0S25 0x00040c08
//
// GPIO pin E4
//
#define GPIO_PE4_CCP3 0x00041001
#define GPIO_PE4_FAULT0 0x00041004
#define GPIO_PE4_U2TX 0x00041005
#define GPIO_PE4_CCP2 0x00041006
#define GPIO_PE4_I2S0TXWS 0x00041009
//
// GPIO pin E5
//
#define GPIO_PE5_CCP5 0x00041401
#define GPIO_PE5_I2S0TXSD 0x00041409
//
// GPIO pin E6
//
#define GPIO_PE6_PWM4 0x00041801
#define GPIO_PE6_C1O 0x00041802
#define GPIO_PE6_U1CTS 0x00041809
//
// GPIO pin E7
//
#define GPIO_PE7_PWM5 0x00041c01
#define GPIO_PE7_C2O 0x00041c02
#define GPIO_PE7_U1DCD 0x00041c09
//
// GPIO pin F0
//
#define GPIO_PF0_CAN1RX 0x00050001
#define GPIO_PF0_PHB0 0x00050002
#define GPIO_PF0_PWM0 0x00050003
#define GPIO_PF0_I2S0TXSD 0x00050008
#define GPIO_PF0_U1DSR 0x00050009
//
// GPIO pin F1
//
#define GPIO_PF1_CAN1TX 0x00050401
#define GPIO_PF1_IDX1 0x00050402
#define GPIO_PF1_PWM1 0x00050403
#define GPIO_PF1_I2S0TXMCLK 0x00050408
#define GPIO_PF1_U1RTS 0x00050409
#define GPIO_PF1_CCP3 0x0005040a
//
// GPIO pin F2
//
#define GPIO_PF2_LED1 0x00050801
#define GPIO_PF2_PWM4 0x00050802
#define GPIO_PF2_PWM2 0x00050804
#define GPIO_PF2_SSI1CLK 0x00050809
//
// GPIO pin F3
//
#define GPIO_PF3_LED0 0x00050c01
#define GPIO_PF3_PWM5 0x00050c02
#define GPIO_PF3_PWM3 0x00050c04
#define GPIO_PF3_SSI1FSS 0x00050c09
//
// GPIO pin F4
//
#define GPIO_PF4_CCP0 0x00051001
#define GPIO_PF4_C0O 0x00051002
#define GPIO_PF4_FAULT0 0x00051004
#define GPIO_PF4_EPI0S12 0x00051008
#define GPIO_PF4_SSI1RX 0x00051009
//
// GPIO pin F5
//
#define GPIO_PF5_CCP2 0x00051401
#define GPIO_PF5_C1O 0x00051402
#define GPIO_PF5_EPI0S15 0x00051408
#define GPIO_PF5_SSI1TX 0x00051409
//
// GPIO pin F6
//
#define GPIO_PF6_CCP1 0x00051801
#define GPIO_PF6_C2O 0x00051802
#define GPIO_PF6_PHA0 0x00051804
#define GPIO_PF6_I2S0TXMCLK 0x00051809
#define GPIO_PF6_U1RTS 0x0005180a
//
// GPIO pin F7
//
#define GPIO_PF7_CCP4 0x00051c01
#define GPIO_PF7_PHB0 0x00051c04
#define GPIO_PF7_EPI0S12 0x00051c08
#define GPIO_PF7_FAULT1 0x00051c09
//
// GPIO pin G0
//
#define GPIO_PG0_U2RX 0x00060001
#define GPIO_PG0_PWM0 0x00060002
#define GPIO_PG0_I2C1SCL 0x00060003
#define GPIO_PG0_PWM4 0x00060004
#define GPIO_PG0_USB0EPEN 0x00060007
#define GPIO_PG0_EPI0S13 0x00060008
//
// GPIO pin G1
//
#define GPIO_PG1_U2TX 0x00060401
#define GPIO_PG1_PWM1 0x00060402
#define GPIO_PG1_I2C1SDA 0x00060403
#define GPIO_PG1_PWM5 0x00060404
#define GPIO_PG1_EPI0S14 0x00060408
//
// GPIO pin G2
//
#define GPIO_PG2_PWM0 0x00060801
#define GPIO_PG2_FAULT0 0x00060804
#define GPIO_PG2_IDX1 0x00060808
#define GPIO_PG2_I2S0RXSD 0x00060809
//
// GPIO pin G3
//
#define GPIO_PG3_PWM1 0x00060c01
#define GPIO_PG3_FAULT2 0x00060c04
#define GPIO_PG3_FAULT0 0x00060c08
#define GPIO_PG3_I2S0RXMCLK 0x00060c09
//
// GPIO pin G4
//
#define GPIO_PG4_CCP3 0x00061001
#define GPIO_PG4_FAULT1 0x00061004
#define GPIO_PG4_EPI0S15 0x00061008
#define GPIO_PG4_PWM6 0x00061009
#define GPIO_PG4_U1RI 0x0006100a
//
// GPIO pin G5
//
#define GPIO_PG5_CCP5 0x00061401
#define GPIO_PG5_IDX0 0x00061404
#define GPIO_PG5_FAULT1 0x00061405
#define GPIO_PG5_PWM7 0x00061408
#define GPIO_PG5_I2S0RXSCK 0x00061409
#define GPIO_PG5_U1DTR 0x0006140a
//
// GPIO pin G6
//
#define GPIO_PG6_PHA1 0x00061801
#define GPIO_PG6_PWM6 0x00061804
#define GPIO_PG6_FAULT1 0x00061808
#define GPIO_PG6_I2S0RXWS 0x00061809
#define GPIO_PG6_U1RI 0x0006180a
//
// GPIO pin G7
//
#define GPIO_PG7_PHB1 0x00061c01
#define GPIO_PG7_PWM7 0x00061c04
#define GPIO_PG7_CCP5 0x00061c08
#define GPIO_PG7_EPI0S31 0x00061c09
//
// GPIO pin H0
//
#define GPIO_PH0_CCP6 0x00070001
#define GPIO_PH0_PWM2 0x00070002
#define GPIO_PH0_EPI0S6 0x00070008
#define GPIO_PH0_PWM4 0x00070009
//
// GPIO pin H1
//
#define GPIO_PH1_CCP7 0x00070401
#define GPIO_PH1_PWM3 0x00070402
#define GPIO_PH1_EPI0S7 0x00070408
#define GPIO_PH1_PWM5 0x00070409
//
// GPIO pin H2
//
#define GPIO_PH2_IDX1 0x00070801
#define GPIO_PH2_C1O 0x00070802
#define GPIO_PH2_FAULT3 0x00070804
#define GPIO_PH2_EPI0S1 0x00070808
//
// GPIO pin H3
//
#define GPIO_PH3_PHB0 0x00070c01
#define GPIO_PH3_FAULT0 0x00070c02
#define GPIO_PH3_USB0EPEN 0x00070c04
#define GPIO_PH3_EPI0S0 0x00070c08
//
// GPIO pin H4
//
#define GPIO_PH4_USB0PFLT 0x00071004
#define GPIO_PH4_EPI0S10 0x00071008
#define GPIO_PH4_SSI1CLK 0x0007100b
//
// GPIO pin H5
//
#define GPIO_PH5_EPI0S11 0x00071408
#define GPIO_PH5_FAULT2 0x0007140a
#define GPIO_PH5_SSI1FSS 0x0007140b
//
// GPIO pin H6
//
#define GPIO_PH6_EPI0S26 0x00071808
#define GPIO_PH6_PWM4 0x0007180a
#define GPIO_PH6_SSI1RX 0x0007180b
//
// GPIO pin H7
//
#define GPIO_PH7_EPI0S27 0x00071c08
#define GPIO_PH7_PWM5 0x00071c0a
#define GPIO_PH7_SSI1TX 0x00071c0b
//
// GPIO pin J0
//
#define GPIO_PJ0_EPI0S16 0x00080008
#define GPIO_PJ0_PWM0 0x0008000a
#define GPIO_PJ0_I2C1SCL 0x0008000b
//
// GPIO pin J1
//
#define GPIO_PJ1_EPI0S17 0x00080408
#define GPIO_PJ1_USB0PFLT 0x00080409
#define GPIO_PJ1_PWM1 0x0008040a
#define GPIO_PJ1_I2C1SDA 0x0008040b
//
// GPIO pin J2
//
#define GPIO_PJ2_EPI0S18 0x00080808
#define GPIO_PJ2_CCP0 0x00080809
#define GPIO_PJ2_FAULT0 0x0008080a
//
// GPIO pin J3
//
#define GPIO_PJ3_EPI0S19 0x00080c08
#define GPIO_PJ3_U1CTS 0x00080c09
#define GPIO_PJ3_CCP6 0x00080c0a
//
// GPIO pin J4
//
#define GPIO_PJ4_EPI0S28 0x00081008
#define GPIO_PJ4_U1DCD 0x00081009
#define GPIO_PJ4_CCP4 0x0008100a
//
// GPIO pin J5
//
#define GPIO_PJ5_EPI0S29 0x00081408
#define GPIO_PJ5_U1DSR 0x00081409
#define GPIO_PJ5_CCP2 0x0008140a
//
// GPIO pin J6
//
#define GPIO_PJ6_EPI0S30 0x00081808
#define GPIO_PJ6_U1RTS 0x00081809
#define GPIO_PJ6_CCP1 0x0008180a
//
// GPIO pin J7
//
#define GPIO_PJ7_U1DTR 0x00081c09
#define GPIO_PJ7_CCP0 0x00081c0a
//*****************************************************************************
//
// Prototypes for the APIs.
@ -128,6 +738,7 @@ extern void GPIOPortIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern void GPIOPinConfigure(unsigned long ulPinConfig);
extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
@ -136,11 +747,13 @@ extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
//*****************************************************************************

563
src/platform/lm3s/hw_adc.h Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// hw_adc.h - Macros used when accessing the ADC hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -43,23 +43,56 @@
#define ADC_O_SSPRI 0x00000020 // Channel priority register
#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.
#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.
#define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt
// Status and Clear
#define ADC_O_CTL 0x00000038 // ADC Control
#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register
#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.
#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register
#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register
#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation
#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital
// Comparator Select
#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register
#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.
#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register
#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register
#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation
#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital
// Comparator Select
#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register
#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.
#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register
#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register
#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation
#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital
// Comparator Select
#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register
#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.
#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register
#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register
#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation
#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital
// Comparator Select
#define ADC_O_TMLB 0x00000100 // Test mode loopback register
#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset
// Initial Conditions
#define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0
#define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1
#define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2
#define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3
#define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4
#define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5
#define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6
#define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7
#define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0
#define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1
#define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2
#define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3
#define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4
#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5
#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6
#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7
//*****************************************************************************
//
@ -76,6 +109,8 @@
// The following are defines for the bit fields in the ADC_RIS register.
//
//*****************************************************************************
#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt
// Status.
#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt
#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt
#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt
@ -86,6 +121,14 @@
// The following are defines for the bit fields in the ADC_IM register.
//
//*****************************************************************************
#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on
// SS3.
#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on
// SS2.
#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on
// SS1.
#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on
// SS0.
#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask
#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask
#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask
@ -96,6 +139,14 @@
// The following are defines for the bit fields in the ADC_ISC register.
//
//*****************************************************************************
#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt
// Status on SS3.
#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt
// Status on SS2.
#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt
// Status on SS1.
#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt
// Status on SS0.
#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt
#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt
#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt
@ -126,6 +177,7 @@
#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event
#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event
#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event
#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM3
#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event
#define ADC_EMUX_EM2_M 0x00000F00 // Event mux 2 mask
#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event
@ -137,6 +189,7 @@
#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event
#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event
#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event
#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM3
#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event
#define ADC_EMUX_EM1_M 0x000000F0 // Event mux 1 mask
#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event
@ -148,6 +201,7 @@
#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event
#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event
#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event
#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM3
#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event
#define ADC_EMUX_EM0_M 0x0000000F // Event mux 0 mask
#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event
@ -159,6 +213,7 @@
#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event
#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event
#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event
#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM3
#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event
//*****************************************************************************
@ -202,6 +257,8 @@
// The following are defines for the bit fields in the ADC_PSSI register.
//
//*****************************************************************************
#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize.
#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait.
#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3
#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2
#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1
@ -247,14 +304,14 @@
// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
//
//*****************************************************************************
#define ADC_SSMUX0_MUX7_M 0x70000000 // 8th Sample Input Select.
#define ADC_SSMUX0_MUX6_M 0x07000000 // 7th Sample Input Select.
#define ADC_SSMUX0_MUX5_M 0x00700000 // 6th Sample Input Select.
#define ADC_SSMUX0_MUX4_M 0x00070000 // 5th Sample Input Select.
#define ADC_SSMUX0_MUX3_M 0x00007000 // 4th Sample Input Select.
#define ADC_SSMUX0_MUX2_M 0x00000700 // 3rd Sample Input Select.
#define ADC_SSMUX0_MUX1_M 0x00000070 // 2nd Sample Input Select.
#define ADC_SSMUX0_MUX0_M 0x00000007 // 1st Sample Input Select.
#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select.
#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select.
#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select.
#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select.
#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select.
#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select.
#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select.
#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select.
#define ADC_SSMUX0_MUX7_S 28
#define ADC_SSMUX0_MUX6_S 24
#define ADC_SSMUX0_MUX5_S 20
@ -327,10 +384,10 @@
// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
//
//*****************************************************************************
#define ADC_SSMUX1_MUX3_M 0x00007000 // 4th Sample Input Select.
#define ADC_SSMUX1_MUX2_M 0x00000700 // 3rd Sample Input Select.
#define ADC_SSMUX1_MUX1_M 0x00000070 // 2nd Sample Input Select.
#define ADC_SSMUX1_MUX0_M 0x00000007 // 1st Sample Input Select.
#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select.
#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select.
#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select.
#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select.
#define ADC_SSMUX1_MUX3_S 12
#define ADC_SSMUX1_MUX2_S 8
#define ADC_SSMUX1_MUX1_S 4
@ -383,10 +440,10 @@
// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
//
//*****************************************************************************
#define ADC_SSMUX2_MUX3_M 0x00007000 // 4th Sample Input Select.
#define ADC_SSMUX2_MUX2_M 0x00000700 // 3rd Sample Input Select.
#define ADC_SSMUX2_MUX1_M 0x00000070 // 2nd Sample Input Select.
#define ADC_SSMUX2_MUX0_M 0x00000007 // 1st Sample Input Select.
#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select.
#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select.
#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select.
#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select.
#define ADC_SSMUX2_MUX3_S 12
#define ADC_SSMUX2_MUX2_S 8
#define ADC_SSMUX2_MUX1_S 4
@ -439,7 +496,7 @@
// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
//
//*****************************************************************************
#define ADC_SSMUX3_MUX0_M 0x00000007 // 1st Sample Input Select.
#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select.
#define ADC_SSMUX3_MUX0_S 0
//*****************************************************************************
@ -472,6 +529,474 @@
#define ADC_SSFSTAT3_HPTR_S 4
#define ADC_SSFSTAT3_TPTR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSDC0 register.
//
//*****************************************************************************
#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator
// Select.
#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator
// Select.
#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator
// Select.
#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator
// Select.
#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
// Select.
#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
// Select.
#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
// Select.
#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
// Select.
#define ADC_SSDC0_S6DCSEL_S 24
#define ADC_SSDC0_S5DCSEL_S 20
#define ADC_SSDC0_S4DCSEL_S 16
#define ADC_SSDC0_S3DCSEL_S 12
#define ADC_SSDC0_S2DCSEL_S 8
#define ADC_SSDC0_S1DCSEL_S 4
#define ADC_SSDC0_S0DCSEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSDC1 register.
//
//*****************************************************************************
#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
// Select.
#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
// Select.
#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
// Select.
#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
// Select.
#define ADC_SSDC1_S2DCSEL_S 8
#define ADC_SSDC1_S1DCSEL_S 4
#define ADC_SSDC1_S0DCSEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSDC2 register.
//
//*****************************************************************************
#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
// Select.
#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
// Select.
#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
// Select.
#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
// Select.
#define ADC_SSDC2_S2DCSEL_S 8
#define ADC_SSDC2_S1DCSEL_S 4
#define ADC_SSDC2_S0DCSEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSDC3 register.
//
//*****************************************************************************
#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
// Select.
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCISC register.
//
//*****************************************************************************
#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt
// Status and Clear.
#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt
// Status and Clear.
#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt
// Status and Clear.
#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt
// Status and Clear.
#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt
// Status and Clear.
#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt
// Status and Clear.
#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt
// Status and Clear.
#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt
// Status and Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSOP0 register.
//
//*****************************************************************************
#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator
// Operation.
#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator
// Operation.
#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator
// Operation.
#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator
// Operation.
#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator
// Operation.
#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator
// Operation.
#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator
// Operation.
#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator
// Operation.
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSOP1 register.
//
//*****************************************************************************
#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 7 Digital Comparator
// Operation.
#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator
// Operation.
#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator
// Operation.
#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator
// Operation.
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSOP2 register.
//
//*****************************************************************************
#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 7 Digital Comparator
// Operation.
#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator
// Operation.
#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator
// Operation.
#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator
// Operation.
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSOP3 register.
//
//*****************************************************************************
#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 7 Digital Comparator
// Operation.
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCRIC register.
//
//*****************************************************************************
#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7.
#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6.
#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5.
#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4.
#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3.
#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2.
#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1.
#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0.
#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7.
#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6.
#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5.
#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4.
#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3.
#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2.
#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1.
#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0.
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
//
//*****************************************************************************
#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable.
#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition.
#define ADC_DCCTL0_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL0_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode.
#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once
#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis always
#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis once
#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable.
#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition.
#define ADC_DCCTL0_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL0_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
#define ADC_DCCTL0_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode.
#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once
#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis always
#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis once
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
//
//*****************************************************************************
#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable.
#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition.
#define ADC_DCCTL1_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL1_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode.
#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once
#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis always
#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis once
#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable.
#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition.
#define ADC_DCCTL1_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL1_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
#define ADC_DCCTL1_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode.
#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once
#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis always
#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis once
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
//
//*****************************************************************************
#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable.
#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition.
#define ADC_DCCTL2_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL2_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode.
#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once
#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis always
#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis once
#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable.
#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition.
#define ADC_DCCTL2_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL2_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
#define ADC_DCCTL2_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode.
#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once
#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis always
#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis once
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
//
//*****************************************************************************
#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable.
#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition.
#define ADC_DCCTL3_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL3_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode.
#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once
#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis always
#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis once
#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable.
#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition.
#define ADC_DCCTL3_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL3_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
#define ADC_DCCTL3_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode.
#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once
#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis always
#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis once
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
//
//*****************************************************************************
#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable.
#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition.
#define ADC_DCCTL4_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL4_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode.
#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once
#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis always
#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis once
#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable.
#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition.
#define ADC_DCCTL4_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL4_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
#define ADC_DCCTL4_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode.
#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once
#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis always
#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis once
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
//
//*****************************************************************************
#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable.
#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition.
#define ADC_DCCTL5_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL5_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode.
#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once
#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis always
#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis once
#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable.
#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition.
#define ADC_DCCTL5_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL5_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
#define ADC_DCCTL5_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode.
#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once
#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis always
#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis once
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
//
//*****************************************************************************
#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable.
#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition.
#define ADC_DCCTL6_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL6_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode.
#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once
#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis always
#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis once
#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable.
#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition.
#define ADC_DCCTL6_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL6_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
#define ADC_DCCTL6_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode.
#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once
#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis always
#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis once
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
//
//*****************************************************************************
#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable.
#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition.
#define ADC_DCCTL7_CTC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL7_CTC_MID 0x00000400 // COMP0 >= CV < COMP1
#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // CV <= COMP0 and <= COMP1
#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode.
#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once
#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis always
#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis once
#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable.
#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition.
#define ADC_DCCTL7_CIC_LOW 0x00000000 // CV < COMP0 and < COMP1
#define ADC_DCCTL7_CIC_MID 0x00000004 // COMP0 >= CV < COMP1
#define ADC_DCCTL7_CIC_HIGH 0x0000000C // CV <= COMP0 and <= COMP1
#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode.
#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always
#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once
#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis always
#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis once
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
//
//*****************************************************************************
#define ADC_DCCMP0_COMP1_M 0x03FF0000 // Compare 1.
#define ADC_DCCMP0_COMP0_M 0x000003FF // Compare 0.
#define ADC_DCCMP0_COMP1_S 16
#define ADC_DCCMP0_COMP0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
//
//*****************************************************************************
#define ADC_DCCMP1_COMP1_M 0x03FF0000 // Compare 1.
#define ADC_DCCMP1_COMP0_M 0x000003FF // Compare 0.
#define ADC_DCCMP1_COMP1_S 16
#define ADC_DCCMP1_COMP0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
//
//*****************************************************************************
#define ADC_DCCMP2_COMP1_M 0x03FF0000 // Compare 1.
#define ADC_DCCMP2_COMP0_M 0x000003FF // Compare 0.
#define ADC_DCCMP2_COMP1_S 16
#define ADC_DCCMP2_COMP0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
//
//*****************************************************************************
#define ADC_DCCMP3_COMP1_M 0x03FF0000 // Compare 1.
#define ADC_DCCMP3_COMP0_M 0x000003FF // Compare 0.
#define ADC_DCCMP3_COMP1_S 16
#define ADC_DCCMP3_COMP0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
//
//*****************************************************************************
#define ADC_DCCMP4_COMP1_M 0x03FF0000 // Compare 1.
#define ADC_DCCMP4_COMP0_M 0x000003FF // Compare 0.
#define ADC_DCCMP4_COMP1_S 16
#define ADC_DCCMP4_COMP0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
//
//*****************************************************************************
#define ADC_DCCMP5_COMP1_M 0x03FF0000 // Compare 1.
#define ADC_DCCMP5_COMP0_M 0x000003FF // Compare 0.
#define ADC_DCCMP5_COMP1_S 16
#define ADC_DCCMP5_COMP0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
//
//*****************************************************************************
#define ADC_DCCMP6_COMP1_M 0x03FF0000 // Compare 1.
#define ADC_DCCMP6_COMP0_M 0x000003FF // Compare 0.
#define ADC_DCCMP6_COMP1_S 16
#define ADC_DCCMP6_COMP0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
//
//*****************************************************************************
#define ADC_DCCMP7_COMP1_M 0x03FF0000 // Compare 1.
#define ADC_DCCMP7_COMP0_M 0x000003FF // Compare 0.
#define ADC_DCCMP7_COMP1_S 16
#define ADC_DCCMP7_COMP0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_CTL register.
//
//*****************************************************************************
#define ADC_CTL_VREF 0x00000001 // Voltage Reference Select.
//*****************************************************************************
//
// The following definitions are deprecated.

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//*****************************************************************************
//
// hw_can.h - Defines and macros used when accessing the can.
//
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_CAN_H__
#define __HW_CAN_H__
//*****************************************************************************
//
// The following are defines for the CAN register offsets.
//
//*****************************************************************************
#define CAN_O_CTL 0x00000000 // Control register
#define CAN_O_STS 0x00000004 // Status register
#define CAN_O_ERR 0x00000008 // Error register
#define CAN_O_BIT 0x0000000C // Bit Timing register
#define CAN_O_INT 0x00000010 // Interrupt register
#define CAN_O_TST 0x00000014 // Test register
#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register
#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.
#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.
#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register
#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register
#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.
#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.
#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.
#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register
#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register
#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register
#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register
#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.
#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.
#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register
#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register
#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.
#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.
#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.
#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register
#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register
#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register
#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register
#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register
#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register
#define CAN_O_NWDA1 0x00000120 // New Data 1 register
#define CAN_O_NWDA2 0x00000124 // New Data 2 register
#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_CTL register.
//
//*****************************************************************************
#define CAN_CTL_TEST 0x00000080 // Test mode enable
#define CAN_CTL_CCE 0x00000040 // Configuration change enable
#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission
#define CAN_CTL_EIE 0x00000008 // Error interrupt enable
#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable
#define CAN_CTL_IE 0x00000002 // Module interrupt enable
#define CAN_CTL_INIT 0x00000001 // Initialization
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_STS register.
//
//*****************************************************************************
#define CAN_STS_BOFF 0x00000080 // Bus Off status
#define CAN_STS_EWARN 0x00000040 // Error Warning status
#define CAN_STS_EPASS 0x00000020 // Error Passive status
#define CAN_STS_RXOK 0x00000010 // Received Message Successful
#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful
#define CAN_STS_LEC_M 0x00000007 // Last Error Code
#define CAN_STS_LEC_NONE 0x00000000 // No error
#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error
#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error
#define CAN_STS_LEC_ACK 0x00000003 // Ack error
#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error
#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error
#define CAN_STS_LEC_CRC 0x00000006 // CRC error
#define CAN_STS_LEC_NOEVENT 0x00000007 // Unused
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_ERR register.
//
//*****************************************************************************
#define CAN_ERR_RP 0x00008000 // Receive error passive status
#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter.
#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter.
#define CAN_ERR_REC_S 8 // Receive error counter bit pos
#define CAN_ERR_TEC_S 0 // Transmit error counter bit pos
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_BIT register.
//
//*****************************************************************************
#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point.
#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample
// Point.
#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width.
#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescalar.
#define CAN_BIT_TSEG2_S 12
#define CAN_BIT_TSEG1_S 8
#define CAN_BIT_SJW_S 6
#define CAN_BIT_BRP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_INT register.
//
//*****************************************************************************
#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier.
#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending
#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_TST register.
//
//*****************************************************************************
#define CAN_TST_RX 0x00000080 // CAN_RX pin status
#define CAN_TST_TX_M 0x00000060 // Overide control of CAN_TX pin
#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX
#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX
#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX
#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX
#define CAN_TST_LBACK 0x00000010 // Loop back mode
#define CAN_TST_SILENT 0x00000008 // Silent mode
#define CAN_TST_BASIC 0x00000004 // Basic mode
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_BRPE register.
//
//*****************************************************************************
#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescalar Extension.
#define CAN_BRPE_BRPE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_TXRQ1 register.
//
//*****************************************************************************
#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits.
#define CAN_TXRQ1_TXRQST_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_TXRQ2 register.
//
//*****************************************************************************
#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits.
#define CAN_TXRQ2_TXRQST_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_NWDA1 register.
//
//*****************************************************************************
#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits.
#define CAN_NWDA1_NEWDAT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_NWDA2 register.
//
//*****************************************************************************
#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits.
#define CAN_NWDA2_NEWDAT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
//
//*****************************************************************************
#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag.
#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number.
#define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
// it is interpreted as 0x20, or
// object 32.
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
//
//*****************************************************************************
#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read.
#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits.
#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits.
#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits.
#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data.
#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request.
#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
//
//*****************************************************************************
#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
#define CAN_IF1MSK1_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
//
//*****************************************************************************
#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier.
#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction.
#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
#define CAN_IF1MSK2_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
//
//*****************************************************************************
#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier.
#define CAN_IF1ARB1_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
//
//*****************************************************************************
#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid.
#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier.
#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction.
#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier.
#define CAN_IF1ARB2_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
//
//*****************************************************************************
#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data.
#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost.
#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending.
#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask.
#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable.
#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request.
#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer.
#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code.
#define CAN_IF1MCTL_DLC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
//
//*****************************************************************************
#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data.
#define CAN_IF1DA1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
//
//*****************************************************************************
#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data.
#define CAN_IF1DA2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
//
//*****************************************************************************
#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data.
#define CAN_IF1DB1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
//
//*****************************************************************************
#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data.
#define CAN_IF1DB2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
//
//*****************************************************************************
#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag.
#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number.
#define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
// it is interpreted as 0x20, or
// object 32.
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
//
//*****************************************************************************
#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read.
#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits.
#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits.
#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits.
#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data.
#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request.
#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
//
//*****************************************************************************
#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
#define CAN_IF2MSK1_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
//
//*****************************************************************************
#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier.
#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction.
#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
#define CAN_IF2MSK2_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
//
//*****************************************************************************
#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier.
#define CAN_IF2ARB1_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
//
//*****************************************************************************
#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid.
#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier.
#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction.
#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier.
#define CAN_IF2ARB2_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
//
//*****************************************************************************
#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data.
#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost.
#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending.
#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask.
#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable.
#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request.
#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer.
#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code.
#define CAN_IF2MCTL_DLC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
//
//*****************************************************************************
#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data.
#define CAN_IF2DA1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
//
//*****************************************************************************
#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data.
#define CAN_IF2DA2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
//
//*****************************************************************************
#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data.
#define CAN_IF2DB1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
//
//*****************************************************************************
#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data.
#define CAN_IF2DB2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG1INT register.
//
//*****************************************************************************
#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
#define CAN_MSG1INT_INTPND_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG2INT register.
//
//*****************************************************************************
#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
#define CAN_MSG2INT_INTPND_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
//
//*****************************************************************************
#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
#define CAN_MSG1VAL_MSGVAL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
//
//*****************************************************************************
#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
#define CAN_MSG2VAL_MSGVAL_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the CAN register offsets.
//
//*****************************************************************************
#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.
#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.
#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.
#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.
//*****************************************************************************
//
// The following are deprecated defines for the reset values of the can
// registers.
//
//*****************************************************************************
#define CAN_RV_IF1MSK2 0x0000FFFF
#define CAN_RV_IF1MSK1 0x0000FFFF
#define CAN_RV_IF2MSK1 0x0000FFFF
#define CAN_RV_IF2MSK2 0x0000FFFF
#define CAN_RV_BIT 0x00002301
#define CAN_RV_CTL 0x00000001
#define CAN_RV_IF1CRQ 0x00000001
#define CAN_RV_IF2CRQ 0x00000001
#define CAN_RV_TXRQ2 0x00000000
#define CAN_RV_IF2DB1 0x00000000
#define CAN_RV_INT 0x00000000
#define CAN_RV_IF1DB2 0x00000000
#define CAN_RV_BRPE 0x00000000
#define CAN_RV_IF2DA2 0x00000000
#define CAN_RV_MSGVAL2 0x00000000
#define CAN_RV_TXRQ1 0x00000000
#define CAN_RV_IF1MCTL 0x00000000
#define CAN_RV_IF1DB1 0x00000000
#define CAN_RV_STS 0x00000000
#define CAN_RV_MSGINT1 0x00000000
#define CAN_RV_IF1DA2 0x00000000
#define CAN_RV_TST 0x00000000
#define CAN_RV_IF1ARB1 0x00000000
#define CAN_RV_IF1ARB2 0x00000000
#define CAN_RV_NWDA2 0x00000000
#define CAN_RV_IF2CMSK 0x00000000
#define CAN_RV_NWDA1 0x00000000
#define CAN_RV_IF1DA1 0x00000000
#define CAN_RV_IF2DA1 0x00000000
#define CAN_RV_IF2MCTL 0x00000000
#define CAN_RV_MSGVAL1 0x00000000
#define CAN_RV_IF1CMSK 0x00000000
#define CAN_RV_ERR 0x00000000
#define CAN_RV_IF2ARB2 0x00000000
#define CAN_RV_MSGINT2 0x00000000
#define CAN_RV_IF2ARB1 0x00000000
#define CAN_RV_IF2DB2 0x00000000
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_STS
// register.
//
//*****************************************************************************
#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_ERR
// register.
//
//*****************************************************************************
#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status
#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status
#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos
#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_BIT
// register.
//
//*****************************************************************************
#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point
#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point
#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width
#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_INT
// register.
//
//*****************************************************************************
#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_TST
// register.
//
//*****************************************************************************
#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_BRPE
// register.
//
//*****************************************************************************
#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1CRQ
// and CAN_IF1CRQ registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status
#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1CMSK
// and CAN_IF2CMSK registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read
#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits
#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits
#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits
#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit
#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)
#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)
#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3
#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1MSK1
// and CAN_IF2MSK1 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1MSK2
// and CAN_IF2MSK2 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier
#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction
#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1ARB1
// and CAN_IF2ARB1 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFARB1_ID 0x0000FFFF // Identifier
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1ARB2
// and CAN_IF2ARB2 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid
#define CAN_IFARB2_XTD 0x00004000 // Extended identifier
#define CAN_IFARB2_DIR 0x00002000 // Message direction
#define CAN_IFARB2_ID 0x00001FFF // Message identifier
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1MCTL
// and CAN_IF2MCTL registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data
#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost
#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending
#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask
#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable
#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable
#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable
#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request
#define CAN_IFMCTL_EOB 0x00000080 // End of buffer
#define CAN_IFMCTL_DLC 0x0000000F // Data length code
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1DA1
// and CAN_IF2DA1 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1DA2
// and CAN_IF2DA2 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1DB1
// and CAN_IF2DB1 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1DB2
// and CAN_IF2DB2 registers.
// Note: All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_TXRQ1
// register.
//
//*****************************************************************************
#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_TXRQ2
// register.
//
//*****************************************************************************
#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_NWDA1
// register.
//
//*****************************************************************************
#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_NWDA2
// register.
//
//*****************************************************************************
#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_MSGINT1
// register.
//
//*****************************************************************************
#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_MSGINT2
// register.
//
//*****************************************************************************
#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_MSGVAL1
// register.
//
//*****************************************************************************
#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_MSGVAL2
// register.
//
//*****************************************************************************
#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits
#endif
#endif // __HW_CAN_H__

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src/platform/lm3s/hw_comp.h Executable file
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@ -0,0 +1,277 @@
//*****************************************************************************
//
// hw_comp.h - Macros used when accessing the comparator hardware.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_COMP_H__
#define __HW_COMP_H__
//*****************************************************************************
//
// The following are defines for the comparator register offsets.
//
//*****************************************************************************
#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked
// Interrupt Status
#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt
// Status
#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt
// Enable
#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference
// Voltage Control
#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register
#define COMP_O_ACCTL0 0x00000024 // Comp0 control register
#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register
#define COMP_O_ACCTL1 0x00000044 // Comp1 control register
#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register
#define COMP_O_ACCTL2 0x00000064 // Comp2 control register
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACMIS register.
//
//*****************************************************************************
#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
// Status.
#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
// Status.
#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
// Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACRIS register.
//
//*****************************************************************************
#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status.
#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status.
#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACINTEN register.
//
//*****************************************************************************
#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable.
#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable.
#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACREFCTL
// register.
//
//*****************************************************************************
#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable.
#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range.
#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref.
#define COMP_ACREFCTL_VREF_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
//
//*****************************************************************************
#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
//
//*****************************************************************************
#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable.
#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive.
#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value
#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value.
#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense.
#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value.
#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense.
#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
//
//*****************************************************************************
#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
//
//*****************************************************************************
#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable.
#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive.
#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value
#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value.
#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense.
#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value.
#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense.
#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
//
//*****************************************************************************
#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value.
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
//
//*****************************************************************************
#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable.
#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive.
#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value
#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value.
#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense.
#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value.
#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense.
#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the comparator register offsets.
//
//*****************************************************************************
#define COMP_O_MIS 0x00000000 // Interrupt status register
#define COMP_O_RIS 0x00000004 // Raw interrupt status register
#define COMP_O_INTEN 0x00000008 // Interrupt enable register
#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the COMP_MIS,
// COMP_RIS, and COMP_INTEN registers.
//
//*****************************************************************************
#define COMP_INT_2 0x00000004 // Comp2 interrupt
#define COMP_INT_1 0x00000002 // Comp1 interrupt
#define COMP_INT_0 0x00000001 // Comp0 interrupt
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the COMP_REFCTL
// register.
//
//*****************************************************************************
#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable
#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range
#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask
#define COMP_REFCTL_VREF_SHIFT 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the COMP_ACSTAT0,
// COMP_ACSTAT1, and COMP_ACSTAT2 registers.
//
//*****************************************************************************
#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the COMP_ACCTL0,
// COMP_ACCTL1, and COMP_ACCTL2 registers.
//
//*****************************************************************************
#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable
#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask
#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved
#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable
#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select
#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask
#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense
#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge
#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge
#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges
#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select
#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask
#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense
#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge
#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge
#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges
#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert
//*****************************************************************************
//
// The following are deprecated defines for the reset values for the comparator
// registers.
//
//*****************************************************************************
#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register
#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register
#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register
#define COMP_RV_RIS 0x00000000 // Raw interrupt status register
#define COMP_RV_INTEN 0x00000000 // Interrupt enable register
#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register
#define COMP_RV_MIS 0x00000000 // Interrupt status register
#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register
#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register
#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.
#endif
#endif // __HW_COMP_H__

428
src/platform/lm3s/hw_epi.h Executable file
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@ -0,0 +1,428 @@
//*****************************************************************************
//
// hw_epi.h - Macros for use in accessing the EPI registers.
//
// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_EPI_H__
#define __HW_EPI_H__
//*****************************************************************************
//
// The following are defines for the External Peripheral Interface (EPI)
//
//*****************************************************************************
#define EPI_O_CFG 0x00000000 // EPI Configuration
#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate
#define EPI_O_GPCFG 0x00000010 // EPI General Purpose
// Configuration
#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Mode Configuration
#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Mode
// Configuration
#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2
#define EPI_O_SDRAMCFG2 0x00000014 // EPI SDRAM Configuration 2
#define EPI_O_GPCFG2 0x00000014 // EPI General-Purpose
// Configuration 2
#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map
#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0
#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0
#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0
#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1
#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1
#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1
#define EPI_O_STAT 0x00000060 // EPI Status
#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count
#define EPI_O_READFIFO 0x00000070 // EPI Read FIFO
#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1
#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2
#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3
#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4
#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5
#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6
#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7
#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects
#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count
#define EPI_O_IM 0x00000210 // EPI Interrupt Mask
#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status
#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status
#define EPI_O_EISC 0x0000021C // EPI Error Interrupt Status and
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_CFG register.
//
//*****************************************************************************
#define EPI_CFG_BLKEN 0x00000010 // Block Enable.
#define EPI_CFG_MODE_M 0x0000000F // Mode Select.
#define EPI_CFG_MODE_NONE 0x00000000 // None
#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM
#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8)
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_BAUD register.
//
//*****************************************************************************
#define EPI_BAUD_COUNT_M 0x0000FFFF // Baud Rate Counter.
#define EPI_BAUD_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
//
//*****************************************************************************
#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // Frequency Range.
#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0
#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15
#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30
#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000 // 50
#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter.
#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode.
#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM.
#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64Mb (8MB)
#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128Mb (16MB)
#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256Mb (32MB)
#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512Mb (64MB)
#define EPI_SDRAMCFG_RFSH_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_GPCFG register.
//
//*****************************************************************************
#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin.
#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated.
#define EPI_GPCFG_RDYEN 0x10000000 // Ready Enable.
#define EPI_GPCFG_FRMPIN 0x08000000 // Framing Pin.
#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame.
#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count.
#define EPI_GPCFG_RW 0x00200000 // Read and Write.
#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes.
#define EPI_GPCFG_RD2CYC 0x00040000 // 2-Cycle Reads.
#define EPI_GPCFG_MAXWAIT_M 0x0000FF00 // Maximum Wait.
#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size.
#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address
#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // 4 Bits Wide (EPI24 to EPI27)
#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // 12 Bits Wide (EPI16 to EPI27).
// Cannot be used with 24-bit data
#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // 20 Bits Wide
#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus.
#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 4 Bits Wide (EPI0 to EPI7)
#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0 to EPI15)
#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0 to EPI23)
#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide. May not be used
// with clock (EPI0 to EPI31). This
// value is normally used for
// acquisition input and actuator
// control as well as other general
// purpose uses.
#define EPI_GPCFG_FRMCNT_S 22
#define EPI_GPCFG_MAXWAIT_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB8CFG register.
//
//*****************************************************************************
#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable.
#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable.
#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity.
#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity.
#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait.
#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States.
#define EPI_HB8CFG_WRWS_0 0x00000000 // No wait states
#define EPI_HB8CFG_WRWS_1 0x00000040 // 1 wait state
#define EPI_HB8CFG_WRWS_2 0x00000080 // 2 wait states
#define EPI_HB8CFG_WRWS_3 0x000000C0 // 3 wait states
#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States.
#define EPI_HB8CFG_RDWS_0 0x00000000 // No wait states
#define EPI_HB8CFG_RDWS_1 0x00000010 // 1 wait state
#define EPI_HB8CFG_RDWS_2 0x00000020 // 2 wait states
#define EPI_HB8CFG_RDWS_3 0x00000030 // 3 wait states
#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode.
#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0]
#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0]
#define EPI_HB8CFG_MODE_SRAM 0x00000002 // SRAM
#define EPI_HB8CFG_MODE_FIFO 0x00000003 // FIFO - D[7:0]
#define EPI_HB8CFG_MAXWAIT_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
//
//*****************************************************************************
#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size.
#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 0x100 (256)
#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 0x10000 (64 KB)
#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 0x1000000 (16 MB)
#define EPI_ADDRMAP_EPSZ_512MB 0x000000C0 // 0x20000000 (512 MB)
#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address.
#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped
#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA0000000
#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC0000000
#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size.
#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 0x100 (256)
#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 0x10000 (64KB)
#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 0x1000000 (16MB)
#define EPI_ADDRMAP_ERSZ_512MB 0x0000000C // 0x20000000 (512MB)
#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address.
#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped
#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x60000000
#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x80000000
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
//
//*****************************************************************************
#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size.
#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits)
#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits)
#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits)
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RADDR0 register.
//
//*****************************************************************************
#define EPI_RADDR0_ADDR_M 0x1FFFFFFF // Current Address.
#define EPI_RADDR0_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
//
//*****************************************************************************
#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count.
#define EPI_RPSTD0_POSTCNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
//
//*****************************************************************************
#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size.
#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits)
#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits)
#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits)
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RADDR1 register.
//
//*****************************************************************************
#define EPI_RADDR1_ADDR_M 0x1FFFFFFF // Current Address.
#define EPI_RADDR1_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
//
//*****************************************************************************
#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count.
#define EPI_RPSTD1_POSTCNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
//
//*****************************************************************************
#define EPI_RFIFOCNT_COUNT_M 0x00000007 // FIFO Count.
#define EPI_RFIFOCNT_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO register.
//
//*****************************************************************************
#define EPI_READFIFO_DATA_M 0xFFFFFFFF // Reads Data.
#define EPI_READFIFO_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO1
// register.
//
//*****************************************************************************
#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data.
#define EPI_READFIFO1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO2
// register.
//
//*****************************************************************************
#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data.
#define EPI_READFIFO2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO3
// register.
//
//*****************************************************************************
#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data.
#define EPI_READFIFO3_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO4
// register.
//
//*****************************************************************************
#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data.
#define EPI_READFIFO4_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO5
// register.
//
//*****************************************************************************
#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data.
#define EPI_READFIFO5_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO6
// register.
//
//*****************************************************************************
#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data.
#define EPI_READFIFO6_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO7
// register.
//
//*****************************************************************************
#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data.
#define EPI_READFIFO7_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
//
//*****************************************************************************
#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error.
#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error.
#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO.
#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Empty
#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // >= 1/4 full
#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // >= 1/2 full
#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // >= 3/4 full
#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO.
#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty
#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // <= 1/8 full
#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // <= 1/4 full
#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // <= 1/2 full
#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // <= 3/4 full
#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // <= 7/8 full
#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries
// in the NBRFIFO.
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_IM register.
//
//*****************************************************************************
#define EPI_IM_WRIM 0x00000004 // Write Interrupt Mask.
#define EPI_IM_RDIM 0x00000002 // Read Interrupt Mask.
#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RIS register.
//
//*****************************************************************************
#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status.
#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status.
#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_MIS register.
//
//*****************************************************************************
#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status.
#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status.
#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_SDRAMCFG2
// register.
//
//*****************************************************************************
#define EPI_SDRAMCFG2_RCM 0x80000000 // Read Capture Mode.
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
//
//*****************************************************************************
#define EPI_HB8CFG2_WORD 0x80000000 // Word Access Mode.
#define EPI_HB8CFG2_CSCFG 0x01000000 // Chip Select Configuration.
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_GPCFG2 register.
//
//*****************************************************************************
#define EPI_GPCFG2_WORD 0x80000000 // Word Access Mode.
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_STAT register.
//
//*****************************************************************************
#define EPI_STAT_CELOW 0x00000200 // Clock Enable Low.
#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full.
#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty.
#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence.
#define EPI_STAT_WBUSY 0x00000020 // Write Busy.
#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy.
#define EPI_STAT_ACTIVE 0x00000001 // Register Active.
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
//
//*****************************************************************************
#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions.
#define EPI_WFIFOCNT_WTAV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_EISC register.
//
//*****************************************************************************
#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error.
#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error.
#define EPI_EISC_TOUT 0x00000001 // Timeout Error.
#endif // __HW_EPI_H__

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src/platform/lm3s/hw_ethernet.h Normal file → Executable file
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@ -2,7 +2,7 @@
//
// hw_ethernet.h - Macros used when accessing the Ethernet hardware.
//
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2006-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -51,6 +51,8 @@
#define MAC_O_NP 0x00000034 // Number of Packets Register
#define MAC_O_TR 0x00000038 // Transmission Request Register
#define MAC_O_TS 0x0000003C // Timer Support Register
#define MAC_O_LED 0x00000040 // Ethernet MAC LED Encoding
#define MAC_O_MDIX 0x00000044 // MDIX Register
//*****************************************************************************
//
@ -188,6 +190,13 @@
//*****************************************************************************
#define MAC_TS_TSEN 0x00000001 // Enable Timestamp Logic
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_MDIX register.
//
//*****************************************************************************
#define MAC_MDIX_EN 0x00000001 // MDI/MDI-X Enable.
//*****************************************************************************
//
// The following are defines for the Ethernet Controller PHY registers.
@ -221,6 +230,14 @@
// 23 - LED Configuration
#define PHY_MR24 0x00000018 // Ethernet PHY Management Register
// 24 -MDI/MDIX Control
#define PHY_MR27 0x0000001B // Ethernet PHY Management Register
// 27 -Special Control/Status
#define PHY_MR29 0x0000001D // Ethernet PHY Management Register
// 29 - Interrupt Status
#define PHY_MR30 0x0000001E // Ethernet PHY Management Register
// 30 - Interrupt Mask
#define PHY_MR31 0x0000001F // Ethernet PHY Management Register
// 31 - PHY Special Control/Status
//*****************************************************************************
//
@ -351,10 +368,12 @@
#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode.
#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing.
#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode.
#define PHY_MR16_SR_M 0x000003C0 // Silicon Revision Identifier.
#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable.
#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity.
#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass.
#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control.
#define PHY_MR16_SR_S 6
//*****************************************************************************
//
@ -362,24 +381,34 @@
//
//*****************************************************************************
#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable.
#define PHY_MR17_FASTRIP 0x00004000 // 10-BASE-T Fast Mode Enable.
#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable.
#define PHY_MR17_EDPD 0x00002000 // Enable Energy Detect Power Down.
#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable.
#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
// Interrupt Enable.
#define PHY_MR17_LSQE 0x00000800 // Low Squelch Enable.
#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable.
#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
// Enable.
#define PHY_MR17_MDPB 0x00000400 // Management Data Preamble Bypass.
#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable.
#define PHY_MR17_FLPBK 0x00000200 // Far Loopback Mode.
#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
// Interrupt Enable.
#define PHY_MR17_FASTEST 0x00000100 // Auto-Negotiation Test Mode.
#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt.
#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt.
#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt.
#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
// Interrupt.
#define PHY_MR17_REFCE 0x00000010 // Reference Clock Enable.
#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt.
#define PHY_MR17_PADBP 0x00000008 // PHY Address Bypass.
#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt.
#define PHY_MR17_FGLS 0x00000004 // Force Good Link Status.
#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt.
#define PHY_MR17_ENON 0x00000002 // Energy On.
#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
// Interrupt.
@ -417,9 +446,6 @@
#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source.
#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
#define PHY_MR23_LED1_TX 0x00000020 // TX Activity
#define PHY_MR23_LED1_RX 0x00000030 // RX Activity
#define PHY_MR23_LED1_COL 0x00000040 // Collision
#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
@ -428,9 +454,6 @@
#define PHY_MR23_LED0_M 0x0000000F // LED0 Source.
#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
#define PHY_MR23_LED0_TX 0x00000002 // TX Activity
#define PHY_MR23_LED0_RX 0x00000003 // RX Activity
#define PHY_MR23_LED0_COL 0x00000004 // Collision
#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
@ -449,6 +472,78 @@
#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed.
#define PHY_MR24_MDIX_SD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR27 register.
//
//*****************************************************************************
#define PHY_MR27_XPOL 0x00000010 // Polarity State of 10 BASE-T.
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR29 register.
//
//*****************************************************************************
#define PHY_MR29_EONIS 0x00000080 // ENERGYON Interrupt.
#define PHY_MR29_ANCOMPIS 0x00000040 // Auto-Negotiation Complete
// Interrupt.
#define PHY_MR29_RFLTIS 0x00000020 // Remote Fault Interrupt.
#define PHY_MR29_LDIS 0x00000010 // Link Down Interrupt.
#define PHY_MR29_LPACKIS 0x00000008 // Auto-Negotiation LP Acknowledge.
#define PHY_MR29_PDFIS 0x00000004 // Parallel Detection Fault.
#define PHY_MR29_PRXIS 0x00000002 // Auto Negotiation Page Received.
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR30 register.
//
//*****************************************************************************
#define PHY_MR30_EONIM 0x00000080 // ENERGYON Interrupt Enabled.
#define PHY_MR30_ANCOMPIM 0x00000040 // Auto-Negotiation Complete
// Interrupt Enabled.
#define PHY_MR30_RFLTIM 0x00000020 // Remote Fault Interrupt Enabled.
#define PHY_MR30_LDIM 0x00000010 // Link Down Interrupt Enabled.
#define PHY_MR30_LPACKIM 0x00000008 // Auto-Negotiation LP Acknowledge
// Enabled.
#define PHY_MR30_PDFIM 0x00000004 // Parallel Detection Fault
// Enabled.
#define PHY_MR30_PRXIM 0x00000002 // Auto Negotiation Page Received
// Enabled.
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR31 register.
//
//*****************************************************************************
#define PHY_MR31_BPRMG 0x00008000 // Bypass Remove Glitch.
#define PHY_MR31_AUTODONE 0x00001000 // Auto Negotiation Done.
#define PHY_MR31_EN4B5B 0x00000040 // Enable 4B5B Encoding/Decoding.
#define PHY_MR31_SPEED_M 0x0000001C // HCD Speed Value.
#define PHY_MR31_SCRDIS 0x00000001 // Scramble Disable.
#define PHY_MR31_SPEED_S 2
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_LED register.
//
//*****************************************************************************
#define MAC_LED_LED1_M 0x000000F0 // LED1 Source.
#define MAC_LED_LED1_LINK 0x00000000 // Link OK
#define MAC_LED_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
#define MAC_LED_LED1_100 0x00000050 // 100BASE-TX mode
#define MAC_LED_LED1_10 0x00000060 // 10BASE-T mode
#define MAC_LED_LED1_DUPLEX 0x00000070 // Full-Duplex
#define MAC_LED_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
// Activity
#define MAC_LED_LED0_M 0x0000000F // LED0 Source.
#define MAC_LED_LED0_LINK 0x00000000 // Link OK (Default LED0)
#define MAC_LED_LED0_RXTX 0x00000001 // RX or TX Activity
#define MAC_LED_LED0_100 0x00000005 // 100BASE-TX mode
#define MAC_LED_LED0_10 0x00000006 // 10BASE-T mode
#define MAC_LED_LED0_DUPLEX 0x00000007 // Full-Duplex
#define MAC_LED_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
// Activity
//*****************************************************************************
//
// The following definitions are deprecated.
@ -570,6 +665,19 @@
//*****************************************************************************
#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the PHY_MR23
// register.
//
//*****************************************************************************
#define PHY_MR23_LED1_TX 0x00000020 // TX Activity
#define PHY_MR23_LED1_RX 0x00000030 // RX Activity
#define PHY_MR23_LED1_COL 0x00000040 // Collision
#define PHY_MR23_LED0_TX 0x00000002 // TX Activity
#define PHY_MR23_LED0_RX 0x00000003 // RX Activity
#define PHY_MR23_LED0_COL 0x00000004 // Collision
#endif
#endif // __HW_ETHERNET_H__

39
src/platform/lm3s/hw_flash.h Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// hw_flash.h - Macros used when accessing the flash controller.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -39,6 +39,9 @@
#define FLASH_FCRIS 0x400FD00C // Raw interrupt status register
#define FLASH_FCIM 0x400FD010 // Interrupt mask register
#define FLASH_FCMISC 0x400FD014 // Interrupt status register
#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2
#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
#define FLASH_FWBN 0x400FD100 // Flash Write Buffer Register n
#define FLASH_RMCTL 0x400FE0F0 // ROM Control
#define FLASH_RMVER 0x400FE0F4 // ROM Version Register
#define FLASH_FMPRE 0x400FE130 // FLASH read protect register
@ -71,6 +74,14 @@
#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word
#define FLASH_FMC_WRKEY_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMC2 register.
//
//*****************************************************************************
#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Write.
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCRIS register.
@ -213,9 +224,17 @@
//
//*****************************************************************************
#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents.
#define FLASH_RMVER_CONT_LM 0x00000000 // Boot Loader & DriverLib
#define FLASH_RMVER_CONT_LM 0x00000000 // Stellaris Boot Loader &
// DriverLib
#define FLASH_RMVER_CONT_LM_AES 0x02000000 // Stellaris Boot Loader &
// DriverLib with AES
#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \
0x03000000 // Stellaris Boot Loader &
// DriverLib with AES and SAFERTOS
#define FLASH_RMVER_SIZE_M 0x00FF0000 // ROM Size.
#define FLASH_RMVER_SIZE_11K 0x00000000 // 11KB Size
#define FLASH_RMVER_SIZE_23_75K 0x00020000 // 23.75KB Size
#define FLASH_RMVER_SIZE_28_25K 0x00030000 // 28.25KB Size
#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version.
#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision.
#define FLASH_RMVER_VER_S 8
@ -239,6 +258,20 @@
#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data.
#define FLASH_USERREG3_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FWBVAL register.
//
//*****************************************************************************
#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Write Buffer.
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FWBN register.
//
//*****************************************************************************
#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data.
//*****************************************************************************
//
// The following definitions are deprecated.

462
src/platform/lm3s/hw_gpio.h Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -54,6 +54,7 @@
#define GPIO_O_LOCK 0x00000520 // Lock register.
#define GPIO_O_CR 0x00000524 // Commit register.
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
//*****************************************************************************
//
@ -68,6 +69,463 @@
// DustDevil-class devices and
// later.
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port A.
//
//*****************************************************************************
#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask
#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0
#define GPIO_PCTL_PA0_I2C1SCL 0x00000008 // I2C1SCL on PA0
#define GPIO_PCTL_PA0_U1RX 0x00000009 // U1RX on PA0
#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 mask
#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1
#define GPIO_PCTL_PA1_I2C1SDA 0x00000080 // I2C1SDA on PA1
#define GPIO_PCTL_PA1_U1TX 0x00000090 // U1TX on PA1
#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 mask
#define GPIO_PCTL_PA2_SSI0CLK 0x00000100 // SSI0CLK on PA2
#define GPIO_PCTL_PA2_PWM4 0x00000400 // PWM4 on PA2
#define GPIO_PCTL_PA2_I2S0RXSD 0x00000900 // I2S0RXSD on PA2
#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 mask
#define GPIO_PCTL_PA3_SSI0FSS 0x00001000 // SSI0FSS on PA3
#define GPIO_PCTL_PA3_PWM5 0x00004000 // PWM5 on PA3
#define GPIO_PCTL_PA3_I2S0RXMCLK \
0x00009000 // I2S0RXMCLK on PA3
#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 mask
#define GPIO_PCTL_PA4_SSI0RX 0x00010000 // SSI0RX on PA4
#define GPIO_PCTL_PA4_PWM6 0x00040000 // PWM6 on PA4
#define GPIO_PCTL_PA4_CAN0RX 0x00050000 // CAN0RX on PA4
#define GPIO_PCTL_PA4_I2S0TXSCK 0x00090000 // I2S0TXSCK on PA4
#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 mask
#define GPIO_PCTL_PA5_SSI0TX 0x00100000 // SSI0TX on PA5
#define GPIO_PCTL_PA5_PWM7 0x00400000 // PWM7 on PA5
#define GPIO_PCTL_PA5_CAN0TX 0x00500000 // CAN0TX on PA5
#define GPIO_PCTL_PA5_I2S0TXWS 0x00900000 // I2S0TXWS on PA5
#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask
#define GPIO_PCTL_PA6_I2C1SCL 0x01000000 // I2C1SCL on PA6
#define GPIO_PCTL_PA6_CCP1 0x02000000 // CCP1 on PA6
#define GPIO_PCTL_PA6_PWM0 0x04000000 // PWM0 on PA6
#define GPIO_PCTL_PA6_PWM4 0x05000000 // PWM4 on PA6
#define GPIO_PCTL_PA6_CAN0RX 0x06000000 // CAN0RX on PA6
#define GPIO_PCTL_PA6_USB0EPEN 0x08000000 // USB0EPEN on PA6
#define GPIO_PCTL_PA6_U1CTS 0x09000000 // U1CTS on PA6
#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask
#define GPIO_PCTL_PA7_I2C1SDA 0x10000000 // I2C1SDA on PA7
#define GPIO_PCTL_PA7_CCP4 0x20000000 // CCP4 on PA7
#define GPIO_PCTL_PA7_PWM1 0x40000000 // PWM1 on PA7
#define GPIO_PCTL_PA7_PWM5 0x50000000 // PWM5 on PA7
#define GPIO_PCTL_PA7_CAN0TX 0x60000000 // CAN0TX on PA7
#define GPIO_PCTL_PA7_CCP3 0x70000000 // CCP3 on PA7
#define GPIO_PCTL_PA7_USB0PFLT 0x80000000 // USB0PFLT on PA7
#define GPIO_PCTL_PA7_U1DCD 0x90000000 // U1DCD on PA7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port B.
//
//*****************************************************************************
#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask
#define GPIO_PCTL_PB0_CCP0 0x00000001 // CCP0 on PB0
#define GPIO_PCTL_PB0_PWM2 0x00000002 // PWM2 on PB0
#define GPIO_PCTL_PB0_U1RX 0x00000005 // U1RX on PB0
#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 mask
#define GPIO_PCTL_PB1_CCP2 0x00000010 // CCP2 on PB1
#define GPIO_PCTL_PB1_PWM3 0x00000020 // PWM3 on PB1
#define GPIO_PCTL_PB1_CCP1 0x00000040 // CCP1 on PB1
#define GPIO_PCTL_PB1_U1TX 0x00000050 // U1TX on PB1
#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 mask
#define GPIO_PCTL_PB2_I2C0SCL 0x00000100 // I2C0SCL on PB2
#define GPIO_PCTL_PB2_IDX0 0x00000200 // IDX0 on PB2
#define GPIO_PCTL_PB2_CCP3 0x00000400 // CCP3 on PB2
#define GPIO_PCTL_PB2_CCP0 0x00000500 // CCP0 on PB2
#define GPIO_PCTL_PB2_USB0EPEN 0x00000800 // USB0EPEN on PB2
#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 mask
#define GPIO_PCTL_PB3_I2C0SDA 0x00001000 // I2C0SDA on PB3
#define GPIO_PCTL_PB3_FAULT0 0x00002000 // FAULT0 on PB3
#define GPIO_PCTL_PB3_FAULT3 0x00004000 // FAULT3 on PB3
#define GPIO_PCTL_PB3_USB0PFLT 0x00008000 // USB0PFLT on PB3
#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 mask
#define GPIO_PCTL_PB4_U2RX 0x00040000 // U2RX on PB4
#define GPIO_PCTL_PB4_CAN0RX 0x00050000 // CAN0RX on PB4
#define GPIO_PCTL_PB4_IDX0 0x00060000 // IDX0 on PB4
#define GPIO_PCTL_PB4_U1RX 0x00070000 // U1RX on PB4
#define GPIO_PCTL_PB4_EPI0S23 0x00080000 // EPI0S23 on PB4
#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 mask
#define GPIO_PCTL_PB5_C0O 0x00100000 // C0O on PB5
#define GPIO_PCTL_PB5_CCP5 0x00200000 // CCP5 on PB5
#define GPIO_PCTL_PB5_CCP6 0x00300000 // CCP6 on PB5
#define GPIO_PCTL_PB5_CCP0 0x00400000 // CCP0 on PB5
#define GPIO_PCTL_PB5_CAN0TX 0x00500000 // CAN0TX on PB5
#define GPIO_PCTL_PB5_CCP2 0x00600000 // CCP2 on PB5
#define GPIO_PCTL_PB5_U1TX 0x00700000 // U1TX on PB5
#define GPIO_PCTL_PB5_EPI0S22 0x00800000 // EPI0S22 on PB5
#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 mask
#define GPIO_PCTL_PB6_CCP1 0x01000000 // CCP1 on PB6
#define GPIO_PCTL_PB6_CCP7 0x02000000 // CCP7 on PB6
#define GPIO_PCTL_PB6_C0O 0x03000000 // C0O on PB6
#define GPIO_PCTL_PB6_FAULT1 0x04000000 // FAULT1 on PB6
#define GPIO_PCTL_PB6_IDX0 0x05000000 // IDX0 on PB6
#define GPIO_PCTL_PB6_CCP5 0x06000000 // CCP5 on PB6
#define GPIO_PCTL_PB6_I2S0TXSCK 0x09000000 // I2S0TXSCK on PB6
#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 mask
#define GPIO_PCTL_PB7_NMI 0x40000000 // NMI on PB7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port C.
//
//*****************************************************************************
#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask
#define GPIO_PCTL_PC0_TCK 0x00000003 // TCK on PC0
#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 mask
#define GPIO_PCTL_PC1_TMS 0x00000030 // TMS on PC1
#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 mask
#define GPIO_PCTL_PC2_TDI 0x00000300 // TDI on PC2
#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 mask
#define GPIO_PCTL_PC3_TDO 0x00003000 // TDO on PC3
#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 mask
#define GPIO_PCTL_PC4_CCP5 0x00010000 // CCP5 on PC4
#define GPIO_PCTL_PC4_PHA0 0x00020000 // PHA0 on PC4
#define GPIO_PCTL_PC4_PWM6 0x00040000 // PWM6 on PC4
#define GPIO_PCTL_PC4_CCP2 0x00050000 // CCP2 on PC4
#define GPIO_PCTL_PC4_CCP4 0x00060000 // CCP4 on PC4
#define GPIO_PCTL_PC4_EPI0S2 0x00080000 // EPI0S2 on PC4
#define GPIO_PCTL_PC4_CCP1 0x00090000 // CCP1 on PC4
#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 mask
#define GPIO_PCTL_PC5_CCP1 0x00100000 // CCP1 on PC5
#define GPIO_PCTL_PC5_C1O 0x00200000 // C1O on PC5
#define GPIO_PCTL_PC5_C0O 0x00300000 // C0O on PC5
#define GPIO_PCTL_PC5_FAULT2 0x00400000 // FAULT2 on PC5
#define GPIO_PCTL_PC5_CCP3 0x00500000 // CCP3 on PC5
#define GPIO_PCTL_PC5_USB0EPEN 0x00600000 // USB0EPEN on PC5
#define GPIO_PCTL_PC5_EPI0S3 0x00800000 // EPI0S3 on PC5
#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask
#define GPIO_PCTL_PC6_CCP3 0x01000000 // CCP3 on PC6
#define GPIO_PCTL_PC6_PHB0 0x02000000 // PHB0 on PC6
#define GPIO_PCTL_PC6_C2O 0x03000000 // C2O on PC6
#define GPIO_PCTL_PC6_PWM7 0x04000000 // PWM7 on PC6
#define GPIO_PCTL_PC6_U1RX 0x05000000 // U1RX on PC6
#define GPIO_PCTL_PC6_CCP0 0x06000000 // CCP0 on PC6
#define GPIO_PCTL_PC6_USB0PFLT 0x07000000 // USB0PFLT on PC6
#define GPIO_PCTL_PC6_EPI0S4 0x08000000 // EPI0S4 on PC6
#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask
#define GPIO_PCTL_PC7_CCP4 0x10000000 // CCP4 on PC7
#define GPIO_PCTL_PC7_PHB0 0x20000000 // PHB0 on PC7
#define GPIO_PCTL_PC7_CCP0 0x40000000 // CCP0 on PC7
#define GPIO_PCTL_PC7_U1TX 0x50000000 // U1TX on PC7
#define GPIO_PCTL_PC7_USB0PFLT 0x60000000 // USB0PFLT on PC7
#define GPIO_PCTL_PC7_C1O 0x70000000 // C1O on PC7
#define GPIO_PCTL_PC7_EPI0S5 0x80000000 // EPI0S5 on PC7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port D.
//
//*****************************************************************************
#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask
#define GPIO_PCTL_PD0_PWM0 0x00000001 // PWM0 on PD0
#define GPIO_PCTL_PD0_CAN0RX 0x00000002 // CAN0RX on PD0
#define GPIO_PCTL_PD0_IDX0 0x00000003 // IDX0 on PD0
#define GPIO_PCTL_PD0_U2RX 0x00000004 // U2RX on PD0
#define GPIO_PCTL_PD0_U1RX 0x00000005 // U1RX on PD0
#define GPIO_PCTL_PD0_CCP6 0x00000006 // CCP6 on PD0
#define GPIO_PCTL_PD0_I2S0RXSCK 0x00000008 // I2S0RXSCK on PD0
#define GPIO_PCTL_PD0_U1CTS 0x00000009 // U1CTS on PD0
#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 mask
#define GPIO_PCTL_PD1_PWM1 0x00000010 // PWM1 on PD1
#define GPIO_PCTL_PD1_CAN0TX 0x00000020 // CAN0TX on PD1
#define GPIO_PCTL_PD1_PHA0 0x00000030 // PHA0 on PD1
#define GPIO_PCTL_PD1_U2TX 0x00000040 // U2TX on PD1
#define GPIO_PCTL_PD1_U1TX 0x00000050 // U1TX on PD1
#define GPIO_PCTL_PD1_CCP7 0x00000060 // CCP7 on PD1
#define GPIO_PCTL_PD1_I2S0RXWS 0x00000080 // I2S0RXWS on PD1
#define GPIO_PCTL_PD1_U1DCD 0x00000090 // U1DCD on PD1
#define GPIO_PCTL_PD1_CCP2 0x000000A0 // CCP2 on PD1
#define GPIO_PCTL_PD1_PHB1 0x000000B0 // PHB1 on PD1
#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 mask
#define GPIO_PCTL_PD2_U1RX 0x00000100 // U1RX on PD2
#define GPIO_PCTL_PD2_CCP6 0x00000200 // CCP6 on PD2
#define GPIO_PCTL_PD2_PWM2 0x00000300 // PWM2 on PD2
#define GPIO_PCTL_PD2_CCP5 0x00000400 // CCP5 on PD2
#define GPIO_PCTL_PD2_EPI0S20 0x00000800 // EPI0S20 on PD2
#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 mask
#define GPIO_PCTL_PD3_U1TX 0x00001000 // U1TX on PD3
#define GPIO_PCTL_PD3_CCP7 0x00002000 // CCP7 on PD3
#define GPIO_PCTL_PD3_PWM3 0x00003000 // PWM3 on PD3
#define GPIO_PCTL_PD3_CCP0 0x00004000 // CCP0 on PD3
#define GPIO_PCTL_PD3_EPI0S21 0x00008000 // EPI0S21 on PD3
#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 mask
#define GPIO_PCTL_PD4_CCP0 0x00010000 // CCP0 on PD4
#define GPIO_PCTL_PD4_CCP3 0x00020000 // CCP3 on PD4
#define GPIO_PCTL_PD4_I2S0RXSD 0x00080000 // I2S0RXSD on PD4
#define GPIO_PCTL_PD4_U1RI 0x00090000 // U1RI on PD4
#define GPIO_PCTL_PD4_EPI0S19 0x000A0000 // EPI0S19 on PD4
#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 mask
#define GPIO_PCTL_PD5_CCP2 0x00100000 // CCP2 on PD5
#define GPIO_PCTL_PD5_CCP4 0x00200000 // CCP4 on PD5
#define GPIO_PCTL_PD5_I2S0RXMCLK \
0x00800000 // I2S0RXMCLK on PD5
#define GPIO_PCTL_PD5_U2RX 0x00900000 // U2RX on PD5
#define GPIO_PCTL_PD5_EPI0S28 0x00A00000 // EPI0S28 on PD5
#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask
#define GPIO_PCTL_PD6_FAULT0 0x01000000 // FAULT0 on PD6
#define GPIO_PCTL_PD6_I2S0TXSCK 0x08000000 // I2S0TXSCK on PD6
#define GPIO_PCTL_PD6_U2TX 0x09000000 // U2TX on PD6
#define GPIO_PCTL_PD6_EPI0S29 0x0A000000 // EPI0S29 on PD6
#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask
#define GPIO_PCTL_PD7_IDX0 0x10000000 // IDX0 on PD7
#define GPIO_PCTL_PD7_C0O 0x20000000 // C0O on PD7
#define GPIO_PCTL_PD7_CCP1 0x30000000 // CCP1 on PD7
#define GPIO_PCTL_PD7_I2S0TXWS 0x80000000 // I2S0TXWS on PD7
#define GPIO_PCTL_PD7_U1DTR 0x90000000 // U1DTR on PD7
#define GPIO_PCTL_PD7_EPI0S30 0xA0000000 // EPI0S30 on PD7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port E.
//
//*****************************************************************************
#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask
#define GPIO_PCTL_PE0_PWM4 0x00000001 // PWM4 on PE0
#define GPIO_PCTL_PE0_SSI1CLK 0x00000002 // SSI1CLK on PE0
#define GPIO_PCTL_PE0_CCP3 0x00000003 // CCP3 on PE0
#define GPIO_PCTL_PE0_EPI0S8 0x00000008 // EPI0S8 on PE0
#define GPIO_PCTL_PE0_USB0PFLT 0x00000009 // USB0PFLT on PE0
#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 mask
#define GPIO_PCTL_PE1_PWM5 0x00000010 // PWM5 on PE1
#define GPIO_PCTL_PE1_SSI1FSS 0x00000020 // SSI1FSS on PE1
#define GPIO_PCTL_PE1_FAULT0 0x00000030 // FAULT0 on PE1
#define GPIO_PCTL_PE1_CCP2 0x00000040 // CCP2 on PE1
#define GPIO_PCTL_PE1_CCP6 0x00000050 // CCP6 on PE1
#define GPIO_PCTL_PE1_EPI0S9 0x00000080 // EPI0S9 on PE1
#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 mask
#define GPIO_PCTL_PE2_CCP4 0x00000100 // CCP4 on PE2
#define GPIO_PCTL_PE2_SSI1RX 0x00000200 // SSI1RX on PE2
#define GPIO_PCTL_PE2_PHB1 0x00000300 // PHB1 on PE2
#define GPIO_PCTL_PE2_PHA0 0x00000400 // PHA0 on PE2
#define GPIO_PCTL_PE2_CCP2 0x00000500 // CCP2 on PE2
#define GPIO_PCTL_PE2_EPI0S24 0x00000800 // EPI0S24 on PE2
#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 mask
#define GPIO_PCTL_PE3_CCP1 0x00001000 // CCP1 on PE3
#define GPIO_PCTL_PE3_SSI1TX 0x00002000 // SSI1TX on PE3
#define GPIO_PCTL_PE3_PHA1 0x00003000 // PHA1 on PE3
#define GPIO_PCTL_PE3_PHB0 0x00004000 // PHB0 on PE3
#define GPIO_PCTL_PE3_CCP7 0x00005000 // CCP7 on PE3
#define GPIO_PCTL_PE3_EPI0S25 0x00008000 // EPI0S25 on PE3
#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 mask
#define GPIO_PCTL_PE4_CCP3 0x00010000 // CCP3 on PE4
#define GPIO_PCTL_PE4_FAULT0 0x00040000 // FAULT0 on PE4
#define GPIO_PCTL_PE4_U2TX 0x00050000 // U2TX on PE4
#define GPIO_PCTL_PE4_CCP2 0x00060000 // CCP2 on PE4
#define GPIO_PCTL_PE4_I2S0TXWS 0x00090000 // I2S0TXWS on PE4
#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 mask
#define GPIO_PCTL_PE5_CCP5 0x00100000 // CCP5 on PE5
#define GPIO_PCTL_PE5_I2S0TXSD 0x00900000 // I2S0TXSD on PE5
#define GPIO_PCTL_PE6_M 0x0F000000 // PE6 mask
#define GPIO_PCTL_PE6_PWM4 0x01000000 // PWM4 on PE6
#define GPIO_PCTL_PE6_C1O 0x02000000 // C1O on PE6
#define GPIO_PCTL_PE6_U1CTS 0x09000000 // U1CTS on PE6
#define GPIO_PCTL_PE7_M 0xF0000000 // PE7 mask
#define GPIO_PCTL_PE7_PWM5 0x10000000 // PWM5 on PE7
#define GPIO_PCTL_PE7_C2O 0x20000000 // C2O on PE7
#define GPIO_PCTL_PE7_U1DCD 0x90000000 // U1DCD on PE7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port F.
//
//*****************************************************************************
#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask
#define GPIO_PCTL_PF0_CAN1RX 0x00000001 // CAN1RX on PF0
#define GPIO_PCTL_PF0_PHB0 0x00000002 // PHB0 on PF0
#define GPIO_PCTL_PF0_PWM0 0x00000003 // PWM0 on PF0
#define GPIO_PCTL_PF0_I2S0TXSD 0x00000008 // I2S0TXSD on PF0
#define GPIO_PCTL_PF0_U1DSR 0x00000009 // U1DSR on PF0
#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 mask
#define GPIO_PCTL_PF1_CAN1TX 0x00000010 // CAN1TX on PF1
#define GPIO_PCTL_PF1_IDX1 0x00000020 // IDX1 on PF1
#define GPIO_PCTL_PF1_PWM1 0x00000030 // PWM1 on PF1
#define GPIO_PCTL_PF1_I2S0TXMCLK \
0x00000080 // I2S0TXMCLK on PF1
#define GPIO_PCTL_PF1_U1RTS 0x00000090 // U1RTS on PF1
#define GPIO_PCTL_PF1_CCP3 0x000000A0 // CCP3 on PF1
#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 mask
#define GPIO_PCTL_PF2_LED1 0x00000100 // LED1 on PF2
#define GPIO_PCTL_PF2_PWM4 0x00000200 // PWM4 on PF2
#define GPIO_PCTL_PF2_PWM2 0x00000400 // PWM2 on PF2
#define GPIO_PCTL_PF2_SSI1CLK 0x00000900 // SSI1CLK on PF2
#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 mask
#define GPIO_PCTL_PF3_LED0 0x00001000 // LED0 on PF3
#define GPIO_PCTL_PF3_PWM5 0x00002000 // PWM5 on PF3
#define GPIO_PCTL_PF3_PWM3 0x00004000 // PWM3 on PF3
#define GPIO_PCTL_PF3_SSI1FSS 0x00009000 // SSI1FSS on PF3
#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 mask
#define GPIO_PCTL_PF4_CCP0 0x00010000 // CCP0 on PF4
#define GPIO_PCTL_PF4_C0O 0x00020000 // C0O on PF4
#define GPIO_PCTL_PF4_FAULT0 0x00040000 // FAULT0 on PF4
#define GPIO_PCTL_PF4_EPI0S12 0x00080000 // EPI0S12 on PF4
#define GPIO_PCTL_PF4_SSI1RX 0x00090000 // SSI1RX on PF4
#define GPIO_PCTL_PF5_M 0x00F00000 // PF5 mask
#define GPIO_PCTL_PF5_CCP2 0x00100000 // CCP2 on PF5
#define GPIO_PCTL_PF5_C1O 0x00200000 // C1O on PF5
#define GPIO_PCTL_PF5_EPI0S15 0x00800000 // EPI0S15 on PF5
#define GPIO_PCTL_PF5_SSI1TX 0x00900000 // SSI1TX on PF5
#define GPIO_PCTL_PF6_M 0x0F000000 // PF6 mask
#define GPIO_PCTL_PF6_CCP1 0x01000000 // CCP1 on PF6
#define GPIO_PCTL_PF6_C2O 0x02000000 // C2O on PF6
#define GPIO_PCTL_PF6_PHA0 0x04000000 // PHA0 on PF6
#define GPIO_PCTL_PF6_I2S0TXMCLK \
0x09000000 // I2S0TXMCLK on PF6
#define GPIO_PCTL_PF6_U1RTS 0x0A000000 // U1RTS on PF6
#define GPIO_PCTL_PF7_M 0xF0000000 // PF7 mask
#define GPIO_PCTL_PF7_CCP4 0x10000000 // CCP4 on PF7
#define GPIO_PCTL_PF7_PHB0 0x40000000 // PHB0 on PF7
#define GPIO_PCTL_PF7_EPI0S12 0x80000000 // EPI0S12 on PF7
#define GPIO_PCTL_PF7_FAULT1 0x90000000 // FAULT1 on PF7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port G.
//
//*****************************************************************************
#define GPIO_PCTL_PG0_M 0x0000000F // PG0 mask
#define GPIO_PCTL_PG0_U2RX 0x00000001 // U2RX on PG0
#define GPIO_PCTL_PG0_PWM0 0x00000002 // PWM0 on PG0
#define GPIO_PCTL_PG0_I2C1SCL 0x00000003 // I2C1SCL on PG0
#define GPIO_PCTL_PG0_PWM4 0x00000004 // PWM4 on PG0
#define GPIO_PCTL_PG0_USB0EPEN 0x00000007 // USB0EPEN on PG0
#define GPIO_PCTL_PG0_EPI0S13 0x00000008 // EPI0S13 on PG0
#define GPIO_PCTL_PG1_M 0x000000F0 // PG1 mask
#define GPIO_PCTL_PG1_U2TX 0x00000010 // U2TX on PG1
#define GPIO_PCTL_PG1_PWM1 0x00000020 // PWM1 on PG1
#define GPIO_PCTL_PG1_I2C1SDA 0x00000030 // I2C1SDA on PG1
#define GPIO_PCTL_PG1_PWM5 0x00000040 // PWM5 on PG1
#define GPIO_PCTL_PG1_EPI0S14 0x00000080 // EPI0S14 on PG1
#define GPIO_PCTL_PG2_M 0x00000F00 // PG2 mask
#define GPIO_PCTL_PG2_PWM0 0x00000100 // PWM0 on PG2
#define GPIO_PCTL_PG2_FAULT0 0x00000400 // FAULT0 on PG2
#define GPIO_PCTL_PG2_IDX1 0x00000800 // IDX1 on PG2
#define GPIO_PCTL_PG2_I2S0RXSD 0x00000900 // I2S0RXSD on PG2
#define GPIO_PCTL_PG3_M 0x0000F000 // PG3 mask
#define GPIO_PCTL_PG3_PWM1 0x00001000 // PWM1 on PG3
#define GPIO_PCTL_PG3_FAULT2 0x00004000 // FAULT2 on PG3
#define GPIO_PCTL_PG3_FAULT0 0x00008000 // FAULT0 on PG3
#define GPIO_PCTL_PG3_I2S0RXMCLK \
0x00009000 // I2S0RXMCLK on PG3
#define GPIO_PCTL_PG4_M 0x000F0000 // PG4 mask
#define GPIO_PCTL_PG4_CCP3 0x00010000 // CCP3 on PG4
#define GPIO_PCTL_PG4_FAULT1 0x00040000 // FAULT1 on PG4
#define GPIO_PCTL_PG4_EPI0S15 0x00080000 // EPI0S15 on PG4
#define GPIO_PCTL_PG4_PWM6 0x00090000 // PWM6 on PG4
#define GPIO_PCTL_PG4_U1RI 0x000A0000 // U1RI on PG4
#define GPIO_PCTL_PG5_M 0x00F00000 // PG5 mask
#define GPIO_PCTL_PG5_CCP5 0x00100000 // CCP5 on PG5
#define GPIO_PCTL_PG5_IDX0 0x00400000 // IDX0 on PG5
#define GPIO_PCTL_PG5_FAULT1 0x00500000 // FAULT1 on PG5
#define GPIO_PCTL_PG5_PWM7 0x00800000 // PWM7 on PG5
#define GPIO_PCTL_PG5_I2S0RXSCK 0x00900000 // I2S0RXSCK on PG5
#define GPIO_PCTL_PG5_U1DTR 0x00A00000 // U1DTR on PG5
#define GPIO_PCTL_PG6_M 0x0F000000 // PG6 mask
#define GPIO_PCTL_PG6_PHA1 0x01000000 // PHA1 on PG6
#define GPIO_PCTL_PG6_PWM6 0x04000000 // PWM6 on PG6
#define GPIO_PCTL_PG6_FAULT1 0x08000000 // FAULT1 on PG6
#define GPIO_PCTL_PG6_I2S0RXWS 0x09000000 // I2S0RXWS on PG6
#define GPIO_PCTL_PG6_U1RI 0x0A000000 // U1RI on PG6
#define GPIO_PCTL_PG7_M 0xF0000000 // PG7 mask
#define GPIO_PCTL_PG7_PHB1 0x10000000 // PHB1 on PG7
#define GPIO_PCTL_PG7_PWM7 0x40000000 // PWM7 on PG7
#define GPIO_PCTL_PG7_CCP5 0x80000000 // CCP5 on PG7
#define GPIO_PCTL_PG7_EPI0S31 0x90000000 // EPI0S31 on PG7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port H.
//
//*****************************************************************************
#define GPIO_PCTL_PH0_M 0x0000000F // PH0 mask
#define GPIO_PCTL_PH0_CCP6 0x00000001 // CCP6 on PH0
#define GPIO_PCTL_PH0_PWM2 0x00000002 // PWM2 on PH0
#define GPIO_PCTL_PH0_EPI0S6 0x00000008 // EPI0S6 on PH0
#define GPIO_PCTL_PH0_PWM4 0x00000009 // PWM4 on PH0
#define GPIO_PCTL_PH1_M 0x000000F0 // PH1 mask
#define GPIO_PCTL_PH1_CCP7 0x00000010 // CCP7 on PH1
#define GPIO_PCTL_PH1_PWM3 0x00000020 // PWM3 on PH1
#define GPIO_PCTL_PH1_EPI0S7 0x00000080 // EPI0S7 on PH1
#define GPIO_PCTL_PH1_PWM5 0x00000090 // PWM5 on PH1
#define GPIO_PCTL_PH2_M 0x00000F00 // PH2 mask
#define GPIO_PCTL_PH2_IDX1 0x00000100 // IDX1 on PH2
#define GPIO_PCTL_PH2_C1O 0x00000200 // C1O on PH2
#define GPIO_PCTL_PH2_FAULT3 0x00000400 // FAULT3 on PH2
#define GPIO_PCTL_PH2_EPI0S1 0x00000800 // EPI0S1 on PH2
#define GPIO_PCTL_PH3_M 0x0000F000 // PH3 mask
#define GPIO_PCTL_PH3_PHB0 0x00001000 // PHB0 on PH3
#define GPIO_PCTL_PH3_FAULT0 0x00002000 // FAULT0 on PH3
#define GPIO_PCTL_PH3_USB0EPEN 0x00004000 // USB0EPEN on PH3
#define GPIO_PCTL_PH3_EPI0S0 0x00008000 // EPI0S0 on PH3
#define GPIO_PCTL_PH4_M 0x000F0000 // PH4 mask
#define GPIO_PCTL_PH4_USB0PFLT 0x00040000 // USB0PFLT on PH4
#define GPIO_PCTL_PH4_EPI0S10 0x00080000 // EPI0S10 on PH4
#define GPIO_PCTL_PH4_SSI1CLK 0x000B0000 // SSI1CLK on PH4
#define GPIO_PCTL_PH5_M 0x00F00000 // PH5 mask
#define GPIO_PCTL_PH5_EPI0S11 0x00800000 // EPI0S11 on PH5
#define GPIO_PCTL_PH5_FAULT2 0x00A00000 // FAULT2 on PH5
#define GPIO_PCTL_PH5_SSI1FSS 0x00B00000 // SSI1FSS on PH5
#define GPIO_PCTL_PH6_M 0x0F000000 // PH6 mask
#define GPIO_PCTL_PH6_EPI0S26 0x08000000 // EPI0S26 on PH6
#define GPIO_PCTL_PH6_PWM4 0x0A000000 // PWM4 on PH6
#define GPIO_PCTL_PH6_SSI1RX 0x0B000000 // SSI1RX on PH6
#define GPIO_PCTL_PH7_M 0xF0000000 // PH7 mask
#define GPIO_PCTL_PH7_EPI0S27 0x80000000 // EPI0S27 on PH7
#define GPIO_PCTL_PH7_PWM5 0xA0000000 // PWM5 on PH7
#define GPIO_PCTL_PH7_SSI1TX 0xB0000000 // SSI1TX on PH7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port J.
//
//*****************************************************************************
#define GPIO_PCTL_PJ0_M 0x0000000F // PJ0 mask
#define GPIO_PCTL_PJ0_EPI0S16 0x00000008 // EPI0S16 on PJ0
#define GPIO_PCTL_PJ0_PWM0 0x0000000A // PWM0 on PJ0
#define GPIO_PCTL_PJ0_I2C1SCL 0x0000000B // I2C1SCL on PJ0
#define GPIO_PCTL_PJ1_M 0x000000F0 // PJ1 mask
#define GPIO_PCTL_PJ1_EPI0S17 0x00000080 // EPI0S17 on PJ1
#define GPIO_PCTL_PJ1_USB0PFLT 0x00000090 // USB0PFLT on PJ1
#define GPIO_PCTL_PJ1_PWM1 0x000000A0 // PWM1 on PJ1
#define GPIO_PCTL_PJ1_I2C1SDA 0x000000B0 // I2C1SDA on PJ1
#define GPIO_PCTL_PJ2_M 0x00000F00 // PJ2 mask
#define GPIO_PCTL_PJ2_EPI0S18 0x00000800 // EPI0S18 on PJ2
#define GPIO_PCTL_PJ2_CCP0 0x00000900 // CCP0 on PJ2
#define GPIO_PCTL_PJ2_FAULT0 0x00000A00 // FAULT0 on PJ2
#define GPIO_PCTL_PJ3_M 0x0000F000 // PJ3 mask
#define GPIO_PCTL_PJ3_EPI0S19 0x00008000 // EPI0S19 on PJ3
#define GPIO_PCTL_PJ3_U1CTS 0x00009000 // U1CTS on PJ3
#define GPIO_PCTL_PJ3_CCP6 0x0000A000 // CCP6 on PJ3
#define GPIO_PCTL_PJ4_M 0x000F0000 // PJ4 mask
#define GPIO_PCTL_PJ4_EPI0S28 0x00080000 // EPI0S28 on PJ4
#define GPIO_PCTL_PJ4_U1DCD 0x00090000 // U1DCD on PJ4
#define GPIO_PCTL_PJ4_CCP4 0x000A0000 // CCP4 on PJ4
#define GPIO_PCTL_PJ5_M 0x00F00000 // PJ5 mask
#define GPIO_PCTL_PJ5_EPI0S29 0x00800000 // EPI0S29 on PJ5
#define GPIO_PCTL_PJ5_U1DSR 0x00900000 // U1DSR on PJ5
#define GPIO_PCTL_PJ5_CCP2 0x00A00000 // CCP2 on PJ5
#define GPIO_PCTL_PJ6_M 0x0F000000 // PJ6 mask
#define GPIO_PCTL_PJ6_EPI0S30 0x08000000 // EPI0S30 on PJ6
#define GPIO_PCTL_PJ6_U1RTS 0x09000000 // U1RTS on PJ6
#define GPIO_PCTL_PJ6_CCP1 0x0A000000 // CCP1 on PJ6
#define GPIO_PCTL_PJ7_M 0xF0000000 // PJ7 mask
#define GPIO_PCTL_PJ7_U1DTR 0x90000000 // U1DTR on PJ7
#define GPIO_PCTL_PJ7_CCP0 0xA0000000 // CCP0 on PJ7
//*****************************************************************************
//
// The following definitions are deprecated.

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//*****************************************************************************
//
// hw_hibernate.h - Defines and Macros for the Hibernation module.
//
// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_HIBERNATE_H__
#define __HW_HIBERNATE_H__
//*****************************************************************************
//
// The following are defines for the Hibernation module register addresses.
//
//*****************************************************************************
#define HIB_RTCC 0x400FC000 // Hibernate RTC counter
#define HIB_RTCM0 0x400FC004 // Hibernate RTC match 0
#define HIB_RTCM1 0x400FC008 // Hibernate RTC match 1
#define HIB_RTCLD 0x400FC00C // Hibernate RTC load
#define HIB_CTL 0x400FC010 // Hibernate RTC control
#define HIB_IM 0x400FC014 // Hibernate interrupt mask
#define HIB_RIS 0x400FC018 // Hibernate raw interrupt status
#define HIB_MIS 0x400FC01C // Hibernate masked interrupt stat
#define HIB_IC 0x400FC020 // Hibernate interrupt clear
#define HIB_RTCT 0x400FC024 // Hibernate RTC trim
#define HIB_DATA 0x400FC030 // Hibernate data area
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate RTC counter
// register.
//
//*****************************************************************************
#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter.
#define HIB_RTCC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate RTC match 0
// register.
//
//*****************************************************************************
#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0.
#define HIB_RTCM0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate RTC match 1
// register.
//
//*****************************************************************************
#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1.
#define HIB_RTCM1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate RTC load
// register.
//
//*****************************************************************************
#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load.
#define HIB_RTCLD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate control
// register
//
//*****************************************************************************
#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable.
#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered.
#define HIB_CTL_VABORT 0x00000080 // low bat abort
#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator
#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect
#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin
#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match
#define HIB_CTL_CLKSEL 0x00000004 // clock input selection
#define HIB_CTL_HIBREQ 0x00000002 // request hibernation
#define HIB_CTL_RTCEN 0x00000001 // RTC enable
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate interrupt mask
// reg.
//
//*****************************************************************************
#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt
#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt
#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt
#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate raw interrupt
// status.
//
//*****************************************************************************
#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt
#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt
#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt
#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert0 Raw Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate masked int
// status.
//
//*****************************************************************************
#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt
#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt
#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt
#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
// Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate interrupt
// clear reg.
//
//*****************************************************************************
#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt
#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt
#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt
#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate RTC trim
// register.
//
//*****************************************************************************
#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value.
#define HIB_RTCT_TRIM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the Hibernate data register.
//
//*****************************************************************************
#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV
// Registers[63:0].
#define HIB_DATA_RTD_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the Hibernation module register
// addresses.
//
//*****************************************************************************
#define HIB_DATA_END 0x400FC130 // end of data area, exclusive
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate RTC
// counter register.
//
//*****************************************************************************
#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate RTC
// match 0 register.
//
//*****************************************************************************
#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate RTC
// match 1 register.
//
//*****************************************************************************
#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate RTC
// load register.
//
//*****************************************************************************
#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate raw
// interrupt status.
//
//*****************************************************************************
#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate
// masked int status.
//
//*****************************************************************************
#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate RTC
// trim register.
//
//*****************************************************************************
#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the Hibernate
// data register.
//
//*****************************************************************************
#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask
#endif
#endif // __HW_HIBERNATE_H__

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//*****************************************************************************
//
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
//*****************************************************************************
//
// The following are defines for the offsets between the I2C master and slave
// registers.
//
//*****************************************************************************
#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address
#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status
#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
#define I2C_O_SDR 0x00000008 // I2C Slave Data
#define I2C_O_MDR 0x00000008 // I2C Master Data
#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask
#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status
#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt
// Status
#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear
#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
// Status
#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
#define I2C_O_MCR 0x00000020 // I2C Master Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MSA register.
//
//*****************************************************************************
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address.
#define I2C_MSA_RS 0x00000001 // Receive not Send
#define I2C_MSA_SA_S 1
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR register.
//
//*****************************************************************************
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address.
#define I2C_SOAR_OAR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SCSR register.
//
//*****************************************************************************
#define I2C_SCSR_FBR 0x00000004 // First Byte Received.
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request.
#define I2C_SCSR_DA 0x00000001 // Device Active.
#define I2C_SCSR_RREQ 0x00000001 // Receive Request.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCS register.
//
//*****************************************************************************
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy.
#define I2C_MCS_IDLE 0x00000020 // I2C Idle.
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost.
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable.
#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data.
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address.
#define I2C_MCS_STOP 0x00000004 // Generate STOP.
#define I2C_MCS_START 0x00000002 // Generate START.
#define I2C_MCS_ERROR 0x00000002 // Error.
#define I2C_MCS_RUN 0x00000001 // I2C Master Enable.
#define I2C_MCS_BUSY 0x00000001 // I2C Busy.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SDR register.
//
//*****************************************************************************
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer.
#define I2C_SDR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MDR register.
//
//*****************************************************************************
#define I2C_MDR_DATA_M 0x000000FF // Data Transferred.
#define I2C_MDR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MTPR register.
//
//*****************************************************************************
#define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period.
#define I2C_MTPR_TPR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SIMR register.
//
//*****************************************************************************
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask.
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask.
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SRIS register.
//
//*****************************************************************************
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
// Status.
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
// Status.
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MIMR register.
//
//*****************************************************************************
#define I2C_MIMR_IM 0x00000001 // Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MRIS register.
//
//*****************************************************************************
#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SMIS register.
//
//*****************************************************************************
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
// Status.
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
// Status.
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SICR register.
//
//*****************************************************************************
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear.
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear.
#define I2C_SICR_DATAIC 0x00000001 // Data Clear Interrupt.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MMIS register.
//
//*****************************************************************************
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MICR register.
//
//*****************************************************************************
#define I2C_MICR_IC 0x00000001 // Interrupt Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCR register.
//
//*****************************************************************************
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable.
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable.
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the offsets between the I2C master
// and slave registers.
//
//*****************************************************************************
#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
//*****************************************************************************
//
// The following are deprecated defines for the I2C master register offsets.
//
//*****************************************************************************
#define I2C_MASTER_O_SA 0x00000000 // Slave address register
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
#define I2C_MASTER_O_DR 0x00000008 // Data register
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register
#define I2C_MASTER_O_CR 0x00000020 // Configuration register
//*****************************************************************************
//
// The following are deprecated defines for the I2C slave register offsets.
//
//*****************************************************************************
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
#define I2C_SLAVE_O_DR 0x00000008 // Data register
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C master
// slave address register.
//
//*****************************************************************************
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
#define I2C_MASTER_SA_SA_SHIFT 1
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Control and Status register.
//
//*****************************************************************************
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
#define I2C_MASTER_CS_STOP 0x00000004 // Stop
#define I2C_MASTER_CS_START 0x00000002 // Start
#define I2C_MASTER_CS_RUN 0x00000001 // Run
//*****************************************************************************
//
// The following are deprecated defines for the values used in determining the
// contents of the I2C Master Timer Period register.
//
//*****************************************************************************
#define I2C_SCL_FAST 400000 // SCL fast frequency
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Interrupt Mask register.
//
//*****************************************************************************
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Raw Interrupt Status register.
//
//*****************************************************************************
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Masked Interrupt Status register.
//
//*****************************************************************************
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Interrupt Clear register.
//
//*****************************************************************************
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Configuration register.
//
//*****************************************************************************
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave Own
// Address register.
//
//*****************************************************************************
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Control/Status register.
//
//*****************************************************************************
#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Interrupt Mask register.
//
//*****************************************************************************
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave Raw
// Interrupt Status register.
//
//*****************************************************************************
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Masked Interrupt Status register.
//
//*****************************************************************************
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Interrupt Clear register.
//
//*****************************************************************************
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SIMR
// register.
//
//*****************************************************************************
#define I2C_SIMR_IM 0x00000001 // Interrupt Mask.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SRIS
// register.
//
//*****************************************************************************
#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SMIS
// register.
//
//*****************************************************************************
#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SICR
// register.
//
//*****************************************************************************
#define I2C_SICR_IC 0x00000001 // Clear Interrupt.
#endif
#endif // __HW_I2C_H__

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src/platform/lm3s/hw_i2s.h Executable file
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@ -0,0 +1,233 @@
//*****************************************************************************
//
// hw_i2s.h - Macros for use in accessing the I2S registers.
//
// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_I2S_H__
#define __HW_I2S_H__
//*****************************************************************************
//
// The following are defines for the Inter-Integrated Circuit Sound (I2S)
// Interface
//
//*****************************************************************************
#define I2S_O_TXFIFO 0x00000000 // I2S Transmit FIFO Data
#define I2S_O_TXFIFOCFG 0x00000004 // I2S Transmit FIFO Configuration
#define I2S_O_TXCFG 0x00000008 // I2S Transmit Module
// Configuration
#define I2S_O_TXLIMIT 0x0000000C // I2S Transmit FIFO Limit
#define I2S_O_TXISM 0x00000010 // I2S Transmit Interrupt Status
// and Mask
#define I2S_O_TXLEV 0x00000018 // I2S Transmit FIFO Level
#define I2S_O_RXFIFO 0x00000800 // I2S Receive FIFO Data
#define I2S_O_RXFIFOCFG 0x00000804 // I2S Receive FIFO Configuration
#define I2S_O_RXCFG 0x00000808 // I2S Receive Module Configuration
#define I2S_O_RXLIMIT 0x0000080C // I2S Receive FIFO Limit
#define I2S_O_RXISM 0x00000810 // I2S Receive Interrupt Status and
// Mask
#define I2S_O_RXLEV 0x00000818 // I2S Receive FIFO Level
#define I2S_O_CFG 0x00000C00 // I2S Module Configuration
#define I2S_O_IM 0x00000C10 // I2S Interrupt Mask
#define I2S_O_RIS 0x00000C14 // I2S Raw Interrupt Status
#define I2S_O_MIS 0x00000C18 // I2S Masked Interrupt Status
#define I2S_O_IC 0x00000C1C // I2S Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXFIFO register.
//
//*****************************************************************************
#define I2S_TXFIFO_M 0xFFFFFFFF // TX Data.
#define I2S_TXFIFO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXFIFOCFG
// register.
//
//*****************************************************************************
#define I2S_TXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size.
#define I2S_TXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXCFG register.
//
//*****************************************************************************
#define I2S_TXCFG_JST 0x20000000 // Justification of Output Data.
#define I2S_TXCFG_DLY 0x10000000 // Data Delay.
#define I2S_TXCFG_SCP 0x08000000 // SCLK Polarity.
#define I2S_TXCFG_LRP 0x04000000 // Left/Right Clock Polarity.
#define I2S_TXCFG_WM_M 0x03000000 // Write Mode.
#define I2S_TXCFG_WM_DUAL 0x00000000 // Stereo mode
#define I2S_TXCFG_WM_COMPACT 0x01000000 // Compact Stereo mode
#define I2S_TXCFG_WM_MONO 0x02000000 // Mono mode
#define I2S_TXCFG_FMT 0x00800000 // FIFO Empty.
#define I2S_TXCFG_MSL 0x00400000 // SCLK Master/Slave.
#define I2S_TXCFG_SSZ_M 0x0000FC00 // Sample Size.
#define I2S_TXCFG_SDSZ_M 0x000003F0 // System Data Size.
#define I2S_TXCFG_SSZ_S 10
#define I2S_TXCFG_SDSZ_S 4
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXLIMIT register.
//
//*****************************************************************************
#define I2S_TXLIMIT_LIMIT_M 0x0000001F // FIFO Limit.
#define I2S_TXLIMIT_LIMIT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXISM register.
//
//*****************************************************************************
#define I2S_TXISM_FFI 0x00010000 // Transmit FIFO Service Request
// Interrupt.
#define I2S_TXISM_FFM 0x00000001 // FIFO Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXLEV register.
//
//*****************************************************************************
#define I2S_TXLEV_LEVEL_M 0x0000001F // Number of Audio Samples.
#define I2S_TXLEV_LEVEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXFIFO register.
//
//*****************************************************************************
#define I2S_RXFIFO_M 0xFFFFFFFF // RX Data.
#define I2S_RXFIFO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXFIFOCFG
// register.
//
//*****************************************************************************
#define I2S_RXFIFOCFG_FMM 0x00000004 // FIFO Mono Mode.
#define I2S_RXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size.
#define I2S_RXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXCFG register.
//
//*****************************************************************************
#define I2S_RXCFG_JST 0x20000000 // Justification of Input Data.
#define I2S_RXCFG_DLY 0x10000000 // Data Delay.
#define I2S_RXCFG_SCP 0x08000000 // SCLK Polarity.
#define I2S_RXCFG_LRP 0x04000000 // Left/Right Clock Polarity.
#define I2S_RXCFG_RM 0x01000000 // Read Mode.
#define I2S_RXCFG_MSL 0x00400000 // SCLK Master/Slave.
#define I2S_RXCFG_SSZ_M 0x0000FC00 // Sample Size.
#define I2S_RXCFG_SDSZ_M 0x000003F0 // System Data Size.
#define I2S_RXCFG_SSZ_S 10
#define I2S_RXCFG_SDSZ_S 4
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXLIMIT register.
//
//*****************************************************************************
#define I2S_RXLIMIT_LIMIT_M 0x0000001F // FIFO Limit.
#define I2S_RXLIMIT_LIMIT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXISM register.
//
//*****************************************************************************
#define I2S_RXISM_FFI 0x00010000 // Receive FIFO Service Request
// Interrupt.
#define I2S_RXISM_FFM 0x00000001 // FIFO Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXLEV register.
//
//*****************************************************************************
#define I2S_RXLEV_LEVEL_M 0x0000001F // Number of Audio Samples.
#define I2S_RXLEV_LEVEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_CFG register.
//
//*****************************************************************************
#define I2S_CFG_RXSLV 0x00000020 // When clear, this bit configures
// the receiver to use the
// externally driven I2S0RXMCLK
// signal.
#define I2S_CFG_TXSLV 0x00000010 // When clear, this bit configures
// the transmitter to use the
// externally driven I2S0TXMCLK
// signal.
#define I2S_CFG_RXEN 0x00000002 // Serial Receive Engine Enable.
#define I2S_CFG_TXEN 0x00000001 // Serial Transmit Engine Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_IM register.
//
//*****************************************************************************
#define I2S_IM_RXRE 0x00000020 // Receive FIFO Read Error.
#define I2S_IM_RXFSR 0x00000010 // Receive FIFO Service Request.
#define I2S_IM_TXWE 0x00000002 // Transmit FIFO Write Error.
#define I2S_IM_TXFSR 0x00000001 // Transmit FIFO Service Request.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RIS register.
//
//*****************************************************************************
#define I2S_RIS_RXRE 0x00000020 // Receive FIFO Read Error.
#define I2S_RIS_RXFSR 0x00000010 // Receive FIFO Service Request.
#define I2S_RIS_TXWE 0x00000002 // Transmit FIFO Write Error.
#define I2S_RIS_TXFSR 0x00000001 // Transmit FIFO Service Request.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_MIS register.
//
//*****************************************************************************
#define I2S_MIS_RXRE 0x00000020 // Receive FIFO Read Error.
#define I2S_MIS_RXFSR 0x00000010 // Receive FIFO Service Request.
#define I2S_MIS_TXWE 0x00000002 // Transmit FIFO Write Error.
#define I2S_MIS_TXFSR 0x00000001 // Transmit FIFO Service Request.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_IC register.
//
//*****************************************************************************
#define I2S_IC_RXRE 0x00000020 // Receive FIFO Read Error.
#define I2S_IC_TXWE 0x00000002 // Transmit FIFO Write Error.
#endif // __HW_I2S_H__

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src/platform/lm3s/hw_ints.h Normal file → Executable file
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@ -2,7 +2,7 @@
//
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -11,7 +11,7 @@
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -96,13 +96,20 @@
#define INT_PWM3 61 // PWM Generator 3
#define INT_UDMA 62 // uDMA controller
#define INT_UDMAERR 63 // uDMA Error
#define INT_ADC1SS0 64 // ADC1 Sequence 0
#define INT_ADC1SS1 65 // ADC1 Sequence 1
#define INT_ADC1SS2 66 // ADC1 Sequence 2
#define INT_ADC1SS3 67 // ADC1 Sequence 3
#define INT_I2S0 68 // I2S0
#define INT_EPI0 69 // EPI0
#define INT_GPIOJ 70 // GPIO Port J
//*****************************************************************************
//
// The following are defines for the total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS 64
#define NUM_INTERRUPTS 70
//*****************************************************************************
//

16
src/platform/lm3s/hw_memmap.h Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// hw_memmap.h - Macros defining the memory map of Stellaris.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -36,7 +36,8 @@
//*****************************************************************************
#define FLASH_BASE 0x00000000 // FLASH memory
#define SRAM_BASE 0x20000000 // SRAM memory
#define WATCHDOG_BASE 0x40000000 // Watchdog
#define WATCHDOG0_BASE 0x40000000 // Watchdog0
#define WATCHDOG1_BASE 0x40001000 // Watchdog1
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
@ -61,14 +62,17 @@
#define TIMER1_BASE 0x40031000 // Timer1
#define TIMER2_BASE 0x40032000 // Timer2
#define TIMER3_BASE 0x40033000 // Timer3
#define ADC_BASE 0x40038000 // ADC
#define ADC0_BASE 0x40038000 // ADC0
#define ADC1_BASE 0x40039000 // ADC1
#define COMP_BASE 0x4003C000 // Analog comparators
#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
#define CAN0_BASE 0x40040000 // CAN0
#define CAN1_BASE 0x40041000 // CAN1
#define CAN2_BASE 0x40042000 // CAN2
#define ETH_BASE 0x40048000 // Ethernet
#define MAC_BASE 0x40048000 // Ethernet
#define USB0_BASE 0x40050000 // USB 0 Controller
#define I2S0_BASE 0x40054000 // I2S0
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
@ -77,6 +81,8 @@
#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
#define EPI0_BASE 0x400D0000 // EPI0
#define HIB_BASE 0x400FC000 // Hibernation Module
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
#define SYSCTL_BASE 0x400FE000 // System Control
@ -100,10 +106,12 @@
// and peripherals.
//
//*****************************************************************************
#define WATCHDOG_BASE 0x40000000 // Watchdog
#define SSI_BASE 0x40008000 // SSI
#define I2C_MASTER_BASE 0x40020000 // I2C Master
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
#define QEI_BASE 0x4002C000 // QEI
#define ADC_BASE 0x40038000 // ADC
#endif

6
src/platform/lm3s/hw_nvic.h Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// hw_nvic.h - Macros used when accessing the NVIC hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -60,6 +60,8 @@
#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register
#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register
#define NVIC_PRI11 0xE000E42C // IRQ 44 to 47 Priority Register
#define NVIC_PRI12 0xE000E430 // IRQ 48 to 51 Priority Register
#define NVIC_PRI13 0xE000E434 // IRQ 52 to 55 Priority Register
#define NVIC_CPUID 0xE000ED00 // CPUID Base Register
#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register
#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register

44
src/platform/lm3s/hw_pwm.h Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -59,6 +59,7 @@
#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band
// Falling-Edge-Delay
#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0
#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1
#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period
#define PWM_O_1_CTL 0x00000080 // PWM1 Control
#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt Enable
@ -75,6 +76,7 @@
#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band
// Falling-Edge-Delay
#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0
#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1
#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period
#define PWM_O_2_CTL 0x000000C0 // PWM2 Control
#define PWM_O_2_INTEN 0x000000C4 // PWM2 InterruptEnable
@ -91,6 +93,7 @@
#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band
// Falling-Edge-Delay
#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0
#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1
#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period
#define PWM_O_3_CTL 0x00000100 // PWM3 Control
#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger
@ -108,15 +111,20 @@
#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band
// Falling-Edge-Delay
#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0
#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1
#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period
#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense
#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0
#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1
#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense
#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0
#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1
#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense
#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0
#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1
#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense
#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0
#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1
//*****************************************************************************
//
@ -212,6 +220,7 @@
#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition
#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition
#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension
#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
@ -261,6 +270,7 @@
//*****************************************************************************
#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense
#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status
#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status
#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base
#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base
#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base
@ -553,6 +563,36 @@
#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1.
#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
// register.
//
//*****************************************************************************
#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7.
#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6.
#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5.
#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4.
#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3.
#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2.
#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1.
#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0.
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
// register.
//
//*****************************************************************************
#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger.
#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger.
#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger.
#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger.
#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger.
#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger.
#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger.
#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger.
//*****************************************************************************
//
// The following definitions are deprecated.

201
src/platform/lm3s/hw_qei.h Executable file
View File

@ -0,0 +1,201 @@
//*****************************************************************************
//
// hw_qei.h - Macros used when accessing the QEI hardware.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_QEI_H__
#define __HW_QEI_H__
//*****************************************************************************
//
// The following are defines for the QEI register offsets.
//
//*****************************************************************************
#define QEI_O_CTL 0x00000000 // Configuration and control reg.
#define QEI_O_STAT 0x00000004 // Status register
#define QEI_O_POS 0x00000008 // Current position register
#define QEI_O_MAXPOS 0x0000000C // Maximum position register
#define QEI_O_LOAD 0x00000010 // Velocity timer load register
#define QEI_O_TIME 0x00000014 // Velocity timer register
#define QEI_O_COUNT 0x00000018 // Velocity pulse count register
#define QEI_O_SPEED 0x0000001C // Velocity speed register
#define QEI_O_INTEN 0x00000020 // Interrupt enable register
#define QEI_O_RIS 0x00000024 // Raw interrupt status register
#define QEI_O_ISC 0x00000028 // Interrupt status register
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_CTL register.
//
//*****************************************************************************
#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Pre-Scale Count.
#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter.
#define QEI_CTL_STALLEN 0x00001000 // Stall enable
#define QEI_CTL_INVI 0x00000800 // Invert Index input
#define QEI_CTL_INVB 0x00000400 // Invert PhB input
#define QEI_CTL_INVA 0x00000200 // Invert PhA input
#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask
#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128
#define QEI_CTL_VELEN 0x00000020 // Velocity enable
#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode
#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode
#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode
#define QEI_CTL_SWAP 0x00000002 // Swap input signals
#define QEI_CTL_ENABLE 0x00000001 // QEI enable
#define QEI_CTL_FILTCNT_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_STAT register.
//
//*****************************************************************************
#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation
#define QEI_STAT_ERROR 0x00000001 // Signalling error detected
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_POS register.
//
//*****************************************************************************
#define QEI_POS_M 0xFFFFFFFF // Current encoder position
#define QEI_POS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_MAXPOS register.
//
//*****************************************************************************
#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position
#define QEI_MAXPOS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_LOAD register.
//
//*****************************************************************************
#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value
#define QEI_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_TIME register.
//
//*****************************************************************************
#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value
#define QEI_TIME_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_COUNT register.
//
//*****************************************************************************
#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count
#define QEI_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_SPEED register.
//
//*****************************************************************************
#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count
#define QEI_SPEED_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_INTEN register.
//
//*****************************************************************************
#define QEI_INTEN_ERROR 0x00000008 // Phase error detected
#define QEI_INTEN_DIR 0x00000004 // Direction change
#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired
#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_RIS register.
//
//*****************************************************************************
#define QEI_RIS_ERROR 0x00000008 // Phase error detected
#define QEI_RIS_DIR 0x00000004 // Direction change
#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired
#define QEI_RIS_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_ISC register.
//
//*****************************************************************************
#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt.
#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt.
#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired
// Interrupt.
#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the QEI_ISC
// register.
//
//*****************************************************************************
#define QEI_INT_ERROR 0x00000008 // Phase error detected
#define QEI_INT_DIR 0x00000004 // Direction change
#define QEI_INT_TIMER 0x00000002 // Velocity timer expired
#define QEI_INT_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following are deprecated defines for the reset values for the QEI
// registers.
//
//*****************************************************************************
#define QEI_RV_POS 0x00000000 // Current position register
#define QEI_RV_LOAD 0x00000000 // Velocity timer load register
#define QEI_RV_CTL 0x00000000 // Configuration and control reg.
#define QEI_RV_RIS 0x00000000 // Raw interrupt status register
#define QEI_RV_ISC 0x00000000 // Interrupt status register
#define QEI_RV_SPEED 0x00000000 // Velocity speed register
#define QEI_RV_INTEN 0x00000000 // Interrupt enable register
#define QEI_RV_STAT 0x00000000 // Status register
#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register
#define QEI_RV_MAXPOS 0x00000000 // Maximum position register
#define QEI_RV_TIME 0x00000000 // Velocity timer register
#endif
#endif // __HW_QEI_H__

5
src/platform/lm3s/hw_ssi.h Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// hw_ssi.h - Macros used when accessing the SSI hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -77,6 +77,7 @@
// The following are defines for the bit fields in the SSI Control register 1.
//
//*****************************************************************************
#define SSI_CR1_EOT 0x00000010 // End of Transmission.
#define SSI_CR1_SOD 0x00000008 // Slave mode output disable
#define SSI_CR1_MS 0x00000004 // Master or slave mode select
#define SSI_CR1_SSE 0x00000002 // Sync serial port enable

350
src/platform/lm3s/hw_sysctl.h Normal file → Executable file
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@ -2,7 +2,7 @@
//
// hw_sysctl.h - Macros used when accessing the system control hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -43,6 +43,7 @@
#define SYSCTL_DC5 0x400FE020 // Device capabilities register 5
#define SYSCTL_DC6 0x400FE024 // Device capabilities register 6
#define SYSCTL_DC7 0x400FE028 // Device capabilities register 7
#define SYSCTL_DC8 0x400FE02C // Device capabilities register 8
#define SYSCTL_PBORCTL 0x400FE030 // POR/BOR reset control register
#define SYSCTL_LDOPCTL 0x400FE034 // LDO power control register
#define SYSCTL_SRCR0 0x400FE040 // Software reset control reg 0
@ -55,8 +56,11 @@
#define SYSCTL_RCC 0x400FE060 // Run-mode clock config register
#define SYSCTL_PLLCFG 0x400FE064 // PLL configuration register
#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High Speed Control
#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO Host-Bus Control
#define SYSCTL_RCC2 0x400FE070 // Run-mode clock config register 2
#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control
#define SYSCTL_PIOSCCTL 0x400FE088 // Precision internal oscillator
// control register
#define SYSCTL_RCGC0 0x400FE100 // Run-mode clock gating register 0
#define SYSCTL_RCGC1 0x400FE104 // Run-mode clock gating register 1
#define SYSCTL_RCGC2 0x400FE108 // Run-mode clock gating register 2
@ -67,8 +71,16 @@
#define SYSCTL_DCGC1 0x400FE124 // Deep Sleep-mode clock gate reg 1
#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep-mode clock gate reg 2
#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep-mode clock config reg
#define SYSCTL_DSFLASHCFG 0x400FE14C // Deep Sleep Flash Configuration
#define SYSCTL_CLKVCLR 0x400FE150 // Clock verifcation clear register
#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator
// Calibration
#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator
// Statistics
#define SYSCTL_LDOARST 0x400FE160 // LDO reset control register
#define SYSCTL_I2SMCLKCFG 0x400FE170 // I2S MCLK Configuration
#define SYSCTL_DC9 0x400FE190 // Device capabilities register 9
#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volitile Memory Information
//*****************************************************************************
//
@ -84,6 +96,8 @@
#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Fury-class Device
#define SYSCTL_DID0_CLASS_DUSTDEVIL \
0x00030000 // DustDevil-class Device
#define SYSCTL_DID0_CLASS_TEMPEST \
0x00040000 // Tempest-class Device
#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major revision mask
#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
@ -117,6 +131,12 @@
// devices with external part
// numbers starting with LM3S.
#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part number mask
#define SYSCTL_DID1_PRTNO_2B93 0x006C0000 // LM3S2B93
#define SYSCTL_DID1_PRTNO_5B91 0x00680000 // LM3S5B91
#define SYSCTL_DID1_PRTNO_9B95 0x006E0000 // LM3S9B95
#define SYSCTL_DID1_PRTNO_9B92 0x006A0000 // LM3S9B92
#define SYSCTL_DID1_PRTNO_9B96 0x006F0000 // LM3S9B96
#define SYSCTL_DID1_PRTNO_9B90 0x00660000 // LM3S9B90
#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
#define SYSCTL_DID1_PRTNO_300 0x00190000 // LM3S300
@ -194,6 +214,7 @@
#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730
#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739
#define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776
#define SYSCTL_DID1_PRTNO_2793 0x006D0000 // LM3S2793
#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911
#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918
#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939
@ -204,8 +225,6 @@
#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739
#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748
#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749
#define SYSCTL_DID1_PRTNO_3759 0x00460000 // LM3S3759
#define SYSCTL_DID1_PRTNO_3768 0x00480000 // LM3S3768
#define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632
#define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652
#define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662
@ -215,11 +234,8 @@
#define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747
#define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749
#define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752
#define SYSCTL_DID1_PRTNO_5757 0x009B0000 // LM3S5757
#define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762
#define SYSCTL_DID1_PRTNO_5767 0x009D0000 // LM3S5767
#define SYSCTL_DID1_PRTNO_5768 0x00A90000 // LM3S5768
#define SYSCTL_DID1_PRTNO_5769 0x00A80000 // LM3S5769
#define SYSCTL_DID1_PRTNO_5791 0x00690000 // LM3S5791
#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100
#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110
#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420
@ -251,6 +267,8 @@
#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962
#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970
#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971
#define SYSCTL_DID1_PRTNO_9790 0x00670000 // LM3S9790
#define SYSCTL_DID1_PRTNO_9792 0x006B0000 // LM3S9792
#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count.
#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package
#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48 pin package
@ -284,6 +302,7 @@
#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_96KB 0x017F0000 // 96 KB of SRAM
#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash size mask
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash
@ -300,14 +319,21 @@
// The following are defines for the bit fields in the SYSCTL_DC1 register.
//
//*****************************************************************************
#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present.
#define SYSCTL_DC1_CAN2 0x04000000 // CAN2 module present
#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present
#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present
#define SYSCTL_DC1_PWM 0x00100000 // PWM module present
#define SYSCTL_DC1_ADC 0x00010000 // ADC module present
#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present.
#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present.
#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider.
#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
// with a PLL divider of 4.
#define SYSCTL_DC1_MINSYSDIV_100 \
0x00001000 // Specifies a 100-MHz clock with a
// PLL divider of 2.
#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Specifies a 66-MHz clock with a
// PLL divider of 3.
#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz clock with a
// PLL divider of 4.
#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
// PLL divider of 8.
#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
@ -317,11 +343,15 @@
#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC
#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC
#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC
#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed.
#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed.
#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present
#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present
#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present
#define SYSCTL_DC1_PLL 0x00000010 // PLL present
#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present.
#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present.
#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present
#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present
#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present
@ -331,6 +361,8 @@
// The following are defines for the bit fields in the SYSCTL_DC2 register.
//
//*****************************************************************************
#define SYSCTL_DC2_EPI0 0x40000000 // EPI0 Present.
#define SYSCTL_DC2_I2S0 0x10000000 // I2S 0 Present.
#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present
#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present
#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present
@ -360,14 +392,14 @@
#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present
#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present
#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present
#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present
#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present
#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present
#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present
#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present
#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present
#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present
#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present
#define SYSCTL_DC3_ADC0AIN7 0x00800000 // AIN7 Pin Present.
#define SYSCTL_DC3_ADC0AIN6 0x00400000 // AIN6 Pin Present.
#define SYSCTL_DC3_ADC0AIN5 0x00200000 // AIN5 Pin Present.
#define SYSCTL_DC3_ADC0AIN4 0x00100000 // AIN4 Pin Present.
#define SYSCTL_DC3_ADC0AIN3 0x00080000 // AIN3 Pin Present.
#define SYSCTL_DC3_ADC0AIN2 0x00040000 // AIN2 Pin Present.
#define SYSCTL_DC3_ADC0AIN1 0x00020000 // AIN1 Pin Present.
#define SYSCTL_DC3_ADC0AIN0 0x00010000 // AIN0 Pin Present.
#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present.
#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present
#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present
@ -394,10 +426,13 @@
#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY0 Present.
#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC0 Present.
#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable.
#define SYSCTL_DC4_PICAL 0x00040000 // When set, indicates that the
// USER can calibrate the PIOSC
#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present.
#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present.
#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA is present.
#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM is present.
#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present.
#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present
#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present
#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present
@ -442,8 +477,9 @@
//*****************************************************************************
#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset.
#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset
#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset.
#define SYSCTL_RESC_SW 0x00000010 // Software reset
#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset.
#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset.
#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset
#define SYSCTL_RESC_POR 0x00000002 // Power on reset
#define SYSCTL_RESC_EXT 0x00000001 // External reset
@ -541,6 +577,7 @@
//
//*****************************************************************************
#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
#define SYSCTL_RCC2_USEFRACT 0x40000000 // Use fractional divider
#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System clock divider
#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
@ -605,6 +642,7 @@
#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
#define SYSCTL_RCC2_FRACT 0x00400000 // Fractional divide
#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL.
#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down
#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass
@ -613,6 +651,7 @@
#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator
#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4
#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.
#define SYSCTL_RCC2_OSCSRC2_419 0x00000060 // Use the 4.19 MHz external osc.
#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.
#define SYSCTL_RCC2_SYSDIV2_S 23 // Shift to the SYSDIV2 field
@ -713,19 +752,23 @@
// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
//
//*****************************************************************************
#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control.
#define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control.
#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control.
#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control.
#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control.
#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control.
#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control.
#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control.
#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control.
#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control.
#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
//
//*****************************************************************************
#define SYSCTL_SRCR1_EPI0 0x40000000 // EPI0 Reset Control.
#define SYSCTL_SRCR1_I2S0 0x10000000 // I2S 0 Reset Control.
#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control.
#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control.
#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control.
@ -752,6 +795,7 @@
#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control.
#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control.
#define SYSCTL_SRCR2_UDMA 0x00002000 // UDMA Reset Control.
#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control.
#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control.
#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control.
#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control.
@ -827,24 +871,32 @@
// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
//
//*****************************************************************************
#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control.
#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control.
#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control.
#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second
#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second
#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second
#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second
#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed.
#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed.
#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control.
#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control.
#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
//
//*****************************************************************************
#define SYSCTL_RCGC1_EPI0 0x40000000 // EPI0 Clock Gating.
#define SYSCTL_RCGC1_I2S0 0x10000000 // I2S0 Clock Gating Control.
#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
// Gating.
#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
@ -874,6 +926,7 @@
#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
#define SYSCTL_RCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.
#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control.
#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
@ -888,24 +941,32 @@
// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
//
//*****************************************************************************
#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control.
#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control.
#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control.
#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second
#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second
#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second
#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second
#define SYSCTL_SCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed.
#define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
#define SYSCTL_SCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed.
#define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control.
#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control.
#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
//
//*****************************************************************************
#define SYSCTL_SCGC1_EPI0 0x40000000 // EPI0 Clock Gating.
#define SYSCTL_SCGC1_I2S0 0x10000000 // I2S 0 Clock Gating.
#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
// Gating.
#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
@ -935,6 +996,7 @@
#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
#define SYSCTL_SCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.
#define SYSCTL_SCGC2_GPIOJ 0x00000100 // GPIO Port J Present.
#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
@ -949,24 +1011,32 @@
// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
//
//*****************************************************************************
#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control.
#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control.
#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control.
#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_DCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
#define SYSCTL_DCGC0_ADCSPD125K 0x00000000 // 125K samples/second
#define SYSCTL_DCGC0_ADCSPD250K 0x00000100 // 250K samples/second
#define SYSCTL_DCGC0_ADCSPD500K 0x00000200 // 500K samples/second
#define SYSCTL_DCGC0_ADCSPD1M 0x00000300 // 1M samples/second
#define SYSCTL_DCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed.
#define SYSCTL_DCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
#define SYSCTL_DCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed.
#define SYSCTL_DCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control.
#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control.
#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
//
//*****************************************************************************
#define SYSCTL_DCGC1_EPI0 0x40000000 // EPI0 Clock Gating.
#define SYSCTL_DCGC1_I2S0 0x10000000 // I2S 0 Clock Gating.
#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
// Gating.
#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
@ -996,6 +1066,7 @@
#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control.
#define SYSCTL_DCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.
#define SYSCTL_DCGC2_GPIOJ 0x00000100 // GPIO Port J Present.
#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
@ -1032,6 +1103,8 @@
// The following are defines for the bit fields in the SYSCTL_DC6 register.
//
//*****************************************************************************
#define SYSCTL_DC6_USB0PHY 0x00000010 // This specifies that USB0 PHY is
// present.
#define SYSCTL_DC6_USB0_M 0x00000003 // This specifies that USB0 is
// present and its capability.
#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is DEVICE or HOST
@ -1064,21 +1137,193 @@
// The following are defines for the bit fields in the SYSCTL_DC7 register.
//
//*****************************************************************************
#define SYSCTL_DC7_DMACH30 0x40000000 // SW.
#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX.
#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX.
#define SYSCTL_DC7_DMACH27 0x08000000 // ADC1_SS3.
#define SYSCTL_DC7_DMACH26 0x04000000 // ADC1_SS2.
#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1.
#define SYSCTL_DC7_SSI1_TX 0x02000000 // SSI1 TX on uDMA Ch25.
#define SYSCTL_DC7_SSI1_RX 0x01000000 // SSI1 RX on uDMA Ch24.
#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0.
#define SYSCTL_DC7_UART1_TX 0x00800000 // UART1 TX on uDMA Ch23.
#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX.
#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX.
#define SYSCTL_DC7_UART1_RX 0x00400000 // UART1 RX on uDMA Ch22.
#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_TX.
#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_RX.
#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B.
#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A.
#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3.
#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2.
#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B.
#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A.
#define SYSCTL_DC7_DMACH13 0x00002000 // UART2_TX.
#define SYSCTL_DC7_DMACH12 0x00001000 // UART2_RX.
#define SYSCTL_DC7_SSI0_TX 0x00000800 // SSI0 TX on uDMA Ch11.
#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / UART1_TX.
#define SYSCTL_DC7_SSI0_RX 0x00000400 // SSI0 RX on uDMA Ch10.
#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / UART1_RX.
#define SYSCTL_DC7_UART0_TX 0x00000200 // UART0 TX on uDMA Ch9.
#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / SSI1_TX.
#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / SSI1_RX.
#define SYSCTL_DC7_UART0_RX 0x00000100 // UART0 RX on uDMA Ch8.
#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B.
#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A.
#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B.
#define SYSCTL_DC7_USB_EP3_TX 0x00000020 // USB EP3 TX on uDMA Ch5.
#define SYSCTL_DC7_USB_EP3_RX 0x00000010 // USB EP3 RX on uDMA Ch4.
#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A.
#define SYSCTL_DC7_USB_EP2_TX 0x00000008 // USB EP2 TX on uDMA Ch3.
#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B.
#define SYSCTL_DC7_USB_EP2_RX 0x00000004 // USB EP2 RX on uDMA Ch2.
#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A.
#define SYSCTL_DC7_USB_EP1_TX 0x00000002 // USB EP1 TX on uDMA Ch1.
#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX.
#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX.
#define SYSCTL_DC7_USB_EP1_RX 0x00000001 // USB EP1 RX on uDMA Ch0.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC8 register.
//
//*****************************************************************************
#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present.
#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present.
#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present.
#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present.
#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC1 11 Pin Present.
#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC1 10 Pin Present.
#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC1 9 Pin Present.
#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC1 8 Pin Present.
#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC1 7 Pin Present.
#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC1 6 Pin Present.
#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC1 5 Pin Present.
#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC1 4 Pin Present.
#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC1 3 Pin Present.
#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC1 2 Pin Present.
#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC1 1 Pin Present.
#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC1 0 Pin Present.
#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present.
#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present.
#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present.
#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present.
#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC0 11 Pin Present.
#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC0 10 Pin Present.
#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC0 9 Pin Present.
#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC0 8 Pin Present.
#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC0 7 Pin Present.
#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC0 6 Pin Present.
#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC0 5 Pin Present.
#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC0 4 Pin Present.
#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC0 3 Pin Present.
#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC0 2 Pin Present.
#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC0 1 Pin Present.
#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC0 0 Pin Present.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
// register.
//
//*****************************************************************************
#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value.
#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration.
#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim.
#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value.
#define SYSCTL_PIOSCCAL_UT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
// register.
//
//*****************************************************************************
#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value.
#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result.
#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been
// attempted.
#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation
// completed to meet 1% accuracy.
#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation
// failed to meet 1% accuracy.
#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value.
#define SYSCTL_PIOSCSTAT_DT_S 16
#define SYSCTL_PIOSCSTAT_CT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_I2SMCLKCFG
// register.
//
//*****************************************************************************
#define SYSCTL_I2SMCLKCFG_RXEN 0x80000000 // RX Clock Enable.
#define SYSCTL_I2SMCLKCFG_RXI_M 0x0FF00000 // RX Clock Integer Input.
#define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000 // RX Clock Fractional Input.
#define SYSCTL_I2SMCLKCFG_TXEN 0x00008000 // TX Clock Enable.
#define SYSCTL_I2SMCLKCFG_TXI_M 0x00000FF0 // TX Clock Integer Input.
#define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F // TX Clock Fractional Input.
#define SYSCTL_I2SMCLKCFG_RXI_S 20
#define SYSCTL_I2SMCLKCFG_RXF_S 16
#define SYSCTL_I2SMCLKCFG_TXI_S 4
#define SYSCTL_I2SMCLKCFG_TXF_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DC9 register.
//
//*****************************************************************************
#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 7 Dig Cmp Present.
#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 6 Dig Cmp Present.
#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 5 Dig Cmp Present.
#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 4 Dig Cmp Present.
#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 3 Dig Cmp Present.
#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 2 Dig Cmp Present.
#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 1 Dig Cmp Present.
#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 0 Dig Cmp Present.
#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 7 Dig Cmp Present.
#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 6 Dig Cmp Present.
#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 5 Dig Cmp Present.
#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 4 Dig Cmp Present.
#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 3 Dig Cmp Present.
#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 2 Dig Cmp Present.
#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 1 Dig Cmp Present.
#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 0 Dig Cmp Present.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
//
//*****************************************************************************
#define SYSCTL_NVMSTAT_TPSW 0x00000010 // 1: Indicates 3rd party software
// in ROM.
#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word flash write buffer
// function available.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DSFLASHCFG
// register.
//
//*****************************************************************************
#define SYSCTL_DSFLASHCFG_SHDWN 0x00000001 // Flash Shutdown.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
// register.
//
//*****************************************************************************
#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced Host Bus.
#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced Host Bus.
#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced Host Bus.
#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced Host Bus.
#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced Host Bus.
#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced Host Bus.
#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced Host Bus.
#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced Host Bus.
#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced Host Bus.
//*****************************************************************************
//
// The following definitions are deprecated.
@ -1140,9 +1385,11 @@
// register.
//
//*****************************************************************************
#define SYSCTL_DC1_ADC 0x00010000 // ADC module present
#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present.
//*****************************************************************************
//
@ -1160,6 +1407,14 @@
// register.
//
//*****************************************************************************
#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present
#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present
#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present
#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present
#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present
#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present
#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present
#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present
#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present
//*****************************************************************************
@ -1261,6 +1516,7 @@
//
//*****************************************************************************
#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset.
//*****************************************************************************
//
@ -1328,6 +1584,42 @@
//*****************************************************************************
#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0
// register.
//
//*****************************************************************************
#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control.
#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_RCGC0
// register.
//
//*****************************************************************************
#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_SCGC0
// register.
//
//*****************************************************************************
#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SYSCTL_DCGC0
// register.
//
//*****************************************************************************
#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control.
#endif
#endif // __HW_SYSCTL_H__

50
src/platform/lm3s/hw_timer.h Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -51,6 +51,8 @@
#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register
#define TIMER_O_TAR 0x00000048 // TimerA register
#define TIMER_O_TBR 0x0000004C // TimerB register
#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
//*****************************************************************************
//
@ -90,9 +92,13 @@
// The following are defines for the bit fields in the TIMER_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match
// Interrupt Mask.
#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask
#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask
#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask
#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match
// Interrupt Mask.
#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask
#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask
#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask
@ -103,9 +109,13 @@
// The following are defines for the bit fields in the TIMER_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw
// Interrupt.
#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status
#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status
#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status
#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw
// Interrupt.
#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status
#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status
#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status
@ -116,9 +126,13 @@
// The following are defines for the bit fields in the TIMER_ICR register.
//
//*****************************************************************************
#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match
// Interrupt Clear.
#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear
#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear
#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear
#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match
// Interrupt Clear.
#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear
#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear
#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear
@ -186,6 +200,11 @@
// The following are defines for the bit fields in the TIMER_O_TAMR register.
//
//*****************************************************************************
#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode.
#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger.
#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
// Enable.
#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction.
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode
// Select.
#define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode.
@ -199,6 +218,11 @@
// The following are defines for the bit fields in the TIMER_O_TBMR register.
//
//*****************************************************************************
#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode.
#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger.
#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
// Enable.
#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction.
#define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode
// Select.
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode.
@ -212,12 +236,16 @@
// The following are defines for the bit fields in the TIMER_O_MIS register.
//
//*****************************************************************************
#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked
// Interrupt.
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked
// Interrupt.
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked
// Interrupt.
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked
// Interrupt.
#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked
// Interrupt.
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt.
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked
// Interrupt.
@ -258,6 +286,24 @@
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match.
#define TIMER_TBPMR_TBPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAV register.
//
//*****************************************************************************
#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High.
#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low.
#define TIMER_TAV_TAVH_S 16
#define TIMER_TAV_TAVL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBV register.
//
//*****************************************************************************
#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register.
#define TIMER_TBV_TBVL_S 0
//*****************************************************************************
//
// The following definitions are deprecated.

22
src/platform/lm3s/hw_types.h Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// hw_types.h - Common types and macros.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -112,6 +112,12 @@ typedef unsigned char tBoolean;
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))
#endif
#ifndef CLASS_IS_TEMPEST
#define CLASS_IS_TEMPEST \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST))
#endif
#ifndef REVISION_IS_A0
#define REVISION_IS_A0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
@ -130,6 +136,18 @@ typedef unsigned char tBoolean;
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
#endif
#ifndef REVISION_IS_B0
#define REVISION_IS_B0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_B1
#define REVISION_IS_B1 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
#endif
#ifndef REVISION_IS_C1
#define REVISION_IS_C1 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \

100
src/platform/lm3s/hw_uart.h Normal file → Executable file
View File

@ -2,7 +2,7 @@
//
// hw_uart.h - Macros and defines used when accessing the UART hardware
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Firmware Development Package.
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -48,6 +48,9 @@
#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register
#define UART_O_ICR 0x00000044 // Interrupt Clear Register
#define UART_O_DMACTL 0x00000048 // UART DMA Control
#define UART_O_LCTL 0x00000090 // UART LIN Control
#define UART_O_LSS 0x00000094 // UART LIN Snap Shot
#define UART_O_LTIM 0x00000098 // UART LIN Timer
//*****************************************************************************
//
@ -76,11 +79,15 @@
// The following are defines for the Flag Register bits
//
//*****************************************************************************
#define UART_FR_RI 0x00000100 // Ring Indicator.
#define UART_FR_TXFE 0x00000080 // TX FIFO Empty
#define UART_FR_RXFF 0x00000040 // RX FIFO Full
#define UART_FR_TXFF 0x00000020 // TX FIFO Full
#define UART_FR_RXFE 0x00000010 // RX FIFO Empty
#define UART_FR_BUSY 0x00000008 // UART Busy
#define UART_FR_DCD 0x00000004 // Data Carrier Detect.
#define UART_FR_DSR 0x00000002 // Data Set Ready.
#define UART_FR_CTS 0x00000001 // Clear To Send.
//*****************************************************************************
//
@ -103,9 +110,17 @@
// The following are defines for the Control Register bits
//
//*****************************************************************************
#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send.
#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send.
#define UART_CTL_RTS 0x00000800 // Request to Send.
#define UART_CTL_DTR 0x00000400 // Data Terminal Ready.
#define UART_CTL_RXE 0x00000200 // Receive Enable
#define UART_CTL_TXE 0x00000100 // Transmit Enable
#define UART_CTL_LBE 0x00000080 // Loopback Enable
#define UART_CTL_LIN 0x00000040 // LIN Mode Enable.
#define UART_CTL_HSE 0x00000020 // High-Speed Enable.
#define UART_CTL_EOT 0x00000010 // End of Transmission.
#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support.
#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable
#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable
#define UART_CTL_UARTEN 0x00000001 // UART Enable
@ -133,6 +148,10 @@
// The following are defines for the Interrupt Mask Set/Clear Register bits
//
//*****************************************************************************
#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask.
#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask.
#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
// Mask.
#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask
#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask
#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask
@ -140,12 +159,26 @@
#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask
#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask
#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask
#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
// Interrupt Mask.
#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Mask.
#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
// Interrupt Mask.
#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
// Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the Raw Interrupt Status Register
//
//*****************************************************************************
#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
// Status.
#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
// Status.
#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
// Interrupt Status.
#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status
#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status
#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status
@ -153,12 +186,26 @@
#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status
#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status
#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status
#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
// Interrupt Status.
#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect odem
// Raw Interrupt Status.
#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
// Interrupt Status.
#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
// Interrupt Status.
//*****************************************************************************
//
// The following are defines for the Masked Interrupt Status Register
//
//*****************************************************************************
#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
// Status.
#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
// Status.
#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
// Interrupt Status.
#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status
#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status
@ -166,12 +213,24 @@
#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status
#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status
#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status
#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
// Interrupt Status.
#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect odem
// Masked Interrupt Status.
#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
// Interrupt Status.
#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
// Interrupt Status.
//*****************************************************************************
//
// The following are defines for the Interrupt Clear Register bits
//
//*****************************************************************************
#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear.
#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear.
#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear.
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
@ -179,6 +238,14 @@
#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
// Interrupt Clear.
#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect odem
// Interrupt Clear.
#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
// Interrupt Clear.
#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
// Interrupt Clear.
//*****************************************************************************
//
@ -222,6 +289,35 @@
#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.
#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCTL register.
//
//*****************************************************************************
#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length.
#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits
// (default)
#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits
#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits
#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits
#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LSS register.
//
//*****************************************************************************
#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot.
#define UART_LSS_TSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LTIM register.
//
//*****************************************************************************
#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value.
#define UART_LTIM_TIMER_S 0
//*****************************************************************************
//
// The following definitions are deprecated.

320
src/platform/lm3s/hw_udma.h Executable file
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@ -0,0 +1,320 @@
//*****************************************************************************
//
// hw_udma.h - Macros for use in accessing the UDMA registers.
//
// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_UDMA_H__
#define __HW_UDMA_H__
//*****************************************************************************
//
// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
//
//*****************************************************************************
#define UDMA_STAT 0x400FF000 // DMA Status
#define UDMA_CFG 0x400FF004 // DMA Configuration
#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer
#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control
// Base Pointer
#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait on Request
// Status
#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request
#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set
#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear
#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set
#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear
#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set
#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear
#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate
// Set
#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate
// Clear
#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
#define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select
#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status
//*****************************************************************************
//
// Micro Direct Memory Access (uDMA) offsets.
//
//*****************************************************************************
#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
// Pointer
#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
// End Pointer
#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
//
//*****************************************************************************
#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer.
#define UDMA_SRCENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_STAT register.
//
//*****************************************************************************
#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available DMA Channels Minus 1.
#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine State.
#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
#define UDMA_STAT_STATE_RD_SRCENDP \
0x00000020 // Reading source end pointer
#define UDMA_STAT_STATE_RD_DSTENDP \
0x00000030 // Reading destination end pointer
#define UDMA_STAT_STATE_RD_SRCDAT \
0x00000040 // Reading source data
#define UDMA_STAT_STATE_WR_DSTDAT \
0x00000050 // Writing destination data
#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for DMA request to clear
#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
#define UDMA_STAT_STATE_DONE 0x00000090 // Done
#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
#define UDMA_STAT_MASTEN 0x00000001 // Master Enable.
#define UDMA_STAT_DMACHANS_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
//
//*****************************************************************************
#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer.
#define UDMA_DSTENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CFG register.
//
//*****************************************************************************
#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CTLBASE register.
//
//*****************************************************************************
#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address.
#define UDMA_CTLBASE_ADDR_S 10
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHCTL register.
//
//*****************************************************************************
#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment.
#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size.
#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment.
#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size.
#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size.
#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1).
#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst.
#define UDMA_CHCTL_XFERMODE_M 0x00000007 // DMA Transfer Mode.
#define UDMA_CHCTL_XFERMODE_STOP \
0x00000000 // Stop
#define UDMA_CHCTL_XFERMODE_BASIC \
0x00000001 // Basic
#define UDMA_CHCTL_XFERMODE_AUTO \
0x00000002 // Auto-Request
#define UDMA_CHCTL_XFERMODE_PINGPONG \
0x00000003 // Ping-Pong
#define UDMA_CHCTL_XFERMODE_MEM_SG \
0x00000004 // Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_MEM_SGA \
0x00000005 // Alternate Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SG \
0x00000006 // Peripheral Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SGA \
0x00000007 // Alternate Peripheral
// Scatter-Gather
#define UDMA_CHCTL_XFERSIZE_S 4
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTBASE register.
//
//*****************************************************************************
#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
// Pointer.
#define UDMA_ALTBASE_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_WAITSTAT register.
//
//*****************************************************************************
#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_SWREQ register.
//
//*****************************************************************************
#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_USEBURSTSET
// register.
//
//*****************************************************************************
#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_USEBURSTCLR
// register.
//
//*****************************************************************************
#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_REQMASKSET
// register.
//
//*****************************************************************************
#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_REQMASKCLR
// register.
//
//*****************************************************************************
#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ENASET register.
//
//*****************************************************************************
#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ENACLR register.
//
//*****************************************************************************
#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTSET register.
//
//*****************************************************************************
#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTCLR register.
//
//*****************************************************************************
#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_PRIOSET register.
//
//*****************************************************************************
#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_PRIOCLR register.
//
//*****************************************************************************
#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ERRCLR register.
//
//*****************************************************************************
#define UDMA_ERRCLR_ERRCLR 0x00000001 // DMA Bus Error Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHALT register.
//
//*****************************************************************************
#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment
// Select.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHIS register.
//
//*****************************************************************************
#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UDMA_ENASET
// register.
//
//*****************************************************************************
#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set.
#endif
#endif // __HW_UDMA_H__

4638
src/platform/lm3s/hw_usb.h Executable file
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File diff suppressed because it is too large Load Diff

178
src/platform/lm3s/hw_watchdog.h Executable file
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@ -0,0 +1,178 @@
//*****************************************************************************
//
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4781 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_WATCHDOG_H__
#define __HW_WATCHDOG_H__
//*****************************************************************************
//
// The following are defines for the Watchdog Timer register offsets.
//
//*****************************************************************************
#define WDT_O_LOAD 0x00000000 // Load register
#define WDT_O_VALUE 0x00000004 // Current value register
#define WDT_O_CTL 0x00000008 // Control register
#define WDT_O_ICR 0x0000000C // Interrupt clear register
#define WDT_O_RIS 0x00000010 // Raw interrupt status register
#define WDT_O_MIS 0x00000014 // Masked interrupt status register
#define WDT_O_TEST 0x00000418 // Test register
#define WDT_O_LOCK 0x00000C00 // Lock register
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_CTL register.
//
//*****************************************************************************
#define WDT_CTL_RESEN 0x00000002 // Enable reset output
#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
// WDT_MIS registers.
//
//*****************************************************************************
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_TEST register.
//
//*****************************************************************************
#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_LOCK register.
//
//*****************************************************************************
#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock.
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked
#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOAD register.
//
//*****************************************************************************
#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value.
#define WDT_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_VALUE register.
//
//*****************************************************************************
#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value.
#define WDT_VALUE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_ICR register.
//
//*****************************************************************************
#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear.
#define WDT_ICR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_RIS register.
//
//*****************************************************************************
#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_MIS register.
//
//*****************************************************************************
#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt
// Status.
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the Watchdog Timer register
// offsets.
//
//*****************************************************************************
#define WDT_O_PeriphID4 0x00000FD0
#define WDT_O_PeriphID5 0x00000FD4
#define WDT_O_PeriphID6 0x00000FD8
#define WDT_O_PeriphID7 0x00000FDC
#define WDT_O_PeriphID0 0x00000FE0
#define WDT_O_PeriphID1 0x00000FE4
#define WDT_O_PeriphID2 0x00000FE8
#define WDT_O_PeriphID3 0x00000FEC
#define WDT_O_PCellID0 0x00000FF0
#define WDT_O_PCellID1 0x00000FF4
#define WDT_O_PCellID2 0x00000FF8
#define WDT_O_PCellID3 0x00000FFC
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the WDT_TEST
// register.
//
//*****************************************************************************
#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
//*****************************************************************************
//
// The following are deprecated defines for the reset values for the WDT
// registers.
//
//*****************************************************************************
#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
#define WDT_RV_LOAD 0xFFFFFFFF // Load register
#define WDT_RV_PCellID1 0x000000F0
#define WDT_RV_PCellID3 0x000000B1
#define WDT_RV_PeriphID1 0x00000018
#define WDT_RV_PeriphID2 0x00000018
#define WDT_RV_PCellID0 0x0000000D
#define WDT_RV_PCellID2 0x00000005
#define WDT_RV_PeriphID0 0x00000005
#define WDT_RV_PeriphID3 0x00000001
#define WDT_RV_PeriphID5 0x00000000
#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
#define WDT_RV_CTL 0x00000000 // Control register
#define WDT_RV_PeriphID4 0x00000000
#define WDT_RV_PeriphID6 0x00000000
#define WDT_RV_PeriphID7 0x00000000
#define WDT_RV_LOCK 0x00000000 // Lock register
#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
#endif
#endif // __HW_WATCHDOG_H__

6
src/platform/lm3s/interrupt.c Normal file → Executable file
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@ -2,7 +2,7 @@
//
// interrupt.c - Driver for the NVIC Interrupt Controller.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -62,7 +62,7 @@ static const unsigned long g_pulRegs[] =
{
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13
};
//*****************************************************************************

4
src/platform/lm3s/interrupt.h Normal file → Executable file
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@ -2,7 +2,7 @@
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

4036
src/platform/lm3s/lm3s6918.h Executable file
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4565
src/platform/lm3s/lm3s6965.h Executable file
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4880
src/platform/lm3s/lm3s8962.h Executable file
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11836
src/platform/lm3s/lm3s9b92.h Executable file
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51
src/platform/lm3s/platform.c
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@ -43,6 +43,16 @@
#include "disp.h"
#include "adc.h"
#ifdef FORLM3S9B92
#include "lm3s9b92.h"
#elif FORLM3S8962
#include "lm3s8962.h"
#elif FORLM3S6965
#include "lm3s6965.h"
#elif FORLM3S6918
#include "lm3s6918.h"
#endif
// UIP sys tick data
// NOTE: when using virtual timers, SYSTICKHZ and VTMR_FREQ_HZ should have the
// same value, as they're served by the same timer (the systick)
@ -107,11 +117,27 @@ int platform_init()
// ****************************************************************************
// PIO
// Same configuration on LM3S8962, LM3S6965, LM3S6918 (8 ports)
// 9B92 has 9 ports (Port J in addition to A-H)
#ifdef FORLM3S9B92
static const u32 pio_base[] = { GPIO_PORTA_BASE, GPIO_PORTB_BASE, GPIO_PORTC_BASE, GPIO_PORTD_BASE,
GPIO_PORTE_BASE, GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTH_BASE,
GPIO_PORTJ_BASE };
static const u32 pio_sysctl[] = { SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD,
SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH,
SYSCTL_PERIPH_GPIOJ };
#else
static const u32 pio_base[] = { GPIO_PORTA_BASE, GPIO_PORTB_BASE, GPIO_PORTC_BASE, GPIO_PORTD_BASE,
GPIO_PORTE_BASE, GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTH_BASE };
static const u32 pio_sysctl[] = { SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD,
SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH };
#endif
static const u32 pio_base[] = { GPIO_PORTA_BASE, GPIO_PORTB_BASE, GPIO_PORTC_BASE, GPIO_PORTD_BASE,
GPIO_PORTE_BASE, GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTH_BASE };
static const u32 pio_sysctl[] = { SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD,
SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_GPIOG, SYSCTL_PERIPH_GPIOH };
static void pios_init()
{
@ -177,7 +203,7 @@ pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
// ****************************************************************************
// SPI
// Same configuration on LM3S8962, LM3S6965 and LM3S6918 (2 SPI ports)
// Same configuration on LM3S8962, LM3S6965, LM3S6918 and LM3S9B92 (2 SPI ports)
// All possible LM3S SPIs defs
// FIXME this anticipates support for a platform with 2 SPI port
@ -235,7 +261,7 @@ void platform_spi_select( unsigned id, int is_select )
// ****************************************************************************
// UART
// Different configurations for LM3S8962, LM3S6918 (2 UARTs) and LM3S6965 (3 UARTs)
// Different configurations for LM3S8962, LM3S6918 (2 UARTs) and LM3S6965, LM3S9B92 (3 UARTs)
// All possible LM3S uarts defs
static const u32 uart_base[] = { UART0_BASE, UART1_BASE, UART2_BASE };
@ -334,7 +360,7 @@ int platform_s_uart_recv( unsigned id, s32 timeout )
// ****************************************************************************
// Timers
// Same on LM3S8962, LM3S6965 and LM3S6918 (4 timers)
// Same on LM3S8962, LM3S6965, LM3S6918 and LM3S9B92 (4 timers)
// All possible LM3S timers defs
static const u32 timer_base[] = { TIMER0_BASE, TIMER1_BASE, TIMER2_BASE, TIMER3_BASE };
@ -408,12 +434,21 @@ const static u8 pwm_div_data[] = { 1, 2, 4, 8, 16, 32, 64 };
// Port/pin information for all channels
#ifdef FORLM3S6965
const static u32 pwm_ports[] = { GPIO_PORTF_BASE, GPIO_PORTD_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE };
#elif FORLM3S9B92
const static u32 pwm_ports[] = { GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE };
// GPIOPCTL probably needs modification to do PWM for 2&3, Digital Function 2
#else
const static u32 pwm_ports[] = { GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE };
#endif
const static u8 pwm_pins[] = { GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1 };
// PWM generators
const static u16 pwm_gens[] = { PWM_GEN_0, PWM_GEN_1, PWM_GEN_2 };
#ifdef FORLM3S9B92
const static u16 pwm_gens[] = { PWM_GEN_0, PWM_GEN_1, PWM_GEN_2, PWM_GEN_3 };
#else
const static u16 pwm_gens[] = { PWM_GEN_0, PWM_GEN_1, PWM_GEN_2 };
#endif
// PWM outputs
const static u16 pwm_outs[] = { PWM_OUT_0, PWM_OUT_1, PWM_OUT_2, PWM_OUT_3, PWM_OUT_4, PWM_OUT_5 };

6
src/platform/lm3s/platform_conf.h
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@ -105,7 +105,11 @@ LUALIB_API int ( luaopen_disp )( lua_State* L );
#define VTMR_FREQ_HZ 4
// Number of resources (0 if not available/not implemented)
#define NUM_PIO 7
#ifdef FORLM3S9B92
#define NUM_PIO 8
#else
#define NUM_PIO 7
#endif
#define NUM_SPI 1
#ifdef FORLM3S6965
#define NUM_UART 3

53
src/platform/lm3s/pwm.c Normal file → Executable file
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@ -2,7 +2,7 @@
//
// pwm.c - API for the PWM modules
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -1544,14 +1544,23 @@ PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
ASSERT(ulBase == PWM_BASE);
ASSERT(PWMGenValid(ulGen));
ASSERT(ulGroup == PWM_FAULT_GROUP_0);
ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);
//
// Write the fault triggers to the appropriate register.
//
HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0) = ulFaultTriggers;
if(ulGroup == PWM_FAULT_GROUP_0)
{
HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0) =
ulFaultTriggers;
}
else
{
HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC1) =
ulFaultTriggers;
}
}
//*****************************************************************************
@ -1588,12 +1597,19 @@ PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen,
ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
ASSERT(ulBase == PWM_BASE);
ASSERT(PWMGenValid(ulGen));
ASSERT(ulGroup == PWM_FAULT_GROUP_0);
ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
//
// Return the current fault triggers.
//
return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0));
if(ulGroup == PWM_FAULT_GROUP_0)
{
return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0));
}
else
{
return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC1));
}
}
//*****************************************************************************
@ -1637,12 +1653,19 @@ PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen,
ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
ASSERT(ulBase == PWM_BASE);
ASSERT(PWMGenValid(ulGen));
ASSERT(ulGroup == PWM_FAULT_GROUP_0);
ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
//
// Return the current fault status.
//
return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0));
if(ulGroup == PWM_FAULT_GROUP_0)
{
return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0));
}
else
{
return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT1));
}
}
//*****************************************************************************
@ -1678,15 +1701,23 @@ PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
ASSERT(ulBase == PWM_BASE);
ASSERT(PWMGenValid(ulGen));
ASSERT(ulGroup == PWM_FAULT_GROUP_0);
ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);
//
// Clear the given faults.
//
HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0) =
ulFaultTriggers;
if(ulGroup == PWM_FAULT_GROUP_0)
{
HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0) =
ulFaultTriggers;
}
else
{
HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT1) =
ulFaultTriggers;
}
}
//*****************************************************************************

14
src/platform/lm3s/pwm.h Normal file → Executable file
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@ -2,7 +2,7 @@
//
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -163,7 +163,7 @@ extern "C"
//*****************************************************************************
//
// Defines to identify each of the possible fault trigger conditions in
// PWM_FAULT_GROUP_0
// PWM_FAULT_GROUP_0.
//
//*****************************************************************************
#define PWM_FAULT_GROUP_0 0
@ -176,6 +176,14 @@ extern "C"
#define PWM_FAULT_ACMP1 0x00020000
#define PWM_FAULT_ACMP2 0x00040000
//*****************************************************************************
//
// Defines to identify each of the possible fault trigger conditions in
// PWM_FAULT_GROUP_1.
//
//*****************************************************************************
#define PWM_FAULT_GROUP_1 1
//*****************************************************************************
//
// Defines to identify the sense of each of the external FAULTn signals

2252
src/platform/lm3s/rom.h Executable file
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2763
src/platform/lm3s/rom_map.h Executable file
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5
src/platform/lm3s/ssi.c Normal file → Executable file
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@ -2,7 +2,7 @@
//
// ssi.c - Driver for Synchronous Serial Interface.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -39,7 +39,6 @@
#include "debug.h"
#include "interrupt.h"
#include "ssi.h"
#include "sysctl.h"
//*****************************************************************************
//

4
src/platform/lm3s/ssi.h Normal file → Executable file
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@ -2,7 +2,7 @@
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

274
src/platform/lm3s/sysctl.c Normal file → Executable file
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@ -2,7 +2,7 @@
//
// sysctl.c - Driver for the system controller.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -33,7 +33,6 @@
//*****************************************************************************
#include "hw_ints.h"
#include "hw_memmap.h"
#include "hw_nvic.h"
#include "hw_sysctl.h"
#include "hw_types.h"
@ -176,13 +175,15 @@ static const unsigned long g_pulXtals[] =
static tBoolean
SysCtlPeripheralValid(unsigned long ulPeripheral)
{
return((ulPeripheral == SYSCTL_PERIPH_ADC) ||
return((ulPeripheral == SYSCTL_PERIPH_ADC0) ||
(ulPeripheral == SYSCTL_PERIPH_ADC1) ||
(ulPeripheral == SYSCTL_PERIPH_CAN0) ||
(ulPeripheral == SYSCTL_PERIPH_CAN1) ||
(ulPeripheral == SYSCTL_PERIPH_CAN2) ||
(ulPeripheral == SYSCTL_PERIPH_COMP0) ||
(ulPeripheral == SYSCTL_PERIPH_COMP1) ||
(ulPeripheral == SYSCTL_PERIPH_COMP2) ||
(ulPeripheral == SYSCTL_PERIPH_EPI0) ||
(ulPeripheral == SYSCTL_PERIPH_ETH) ||
(ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
(ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
@ -192,9 +193,11 @@ SysCtlPeripheralValid(unsigned long ulPeripheral)
(ulPeripheral == SYSCTL_PERIPH_GPIOF) ||
(ulPeripheral == SYSCTL_PERIPH_GPIOG) ||
(ulPeripheral == SYSCTL_PERIPH_GPIOH) ||
(ulPeripheral == SYSCTL_PERIPH_GPIOJ) ||
(ulPeripheral == SYSCTL_PERIPH_HIBERNATE) ||
(ulPeripheral == SYSCTL_PERIPH_I2C0) ||
(ulPeripheral == SYSCTL_PERIPH_I2C1) ||
(ulPeripheral == SYSCTL_PERIPH_I2S0) ||
(ulPeripheral == SYSCTL_PERIPH_IEEE1588) ||
(ulPeripheral == SYSCTL_PERIPH_MPU) ||
(ulPeripheral == SYSCTL_PERIPH_PLL) ||
@ -213,7 +216,8 @@ SysCtlPeripheralValid(unsigned long ulPeripheral)
(ulPeripheral == SYSCTL_PERIPH_UART2) ||
(ulPeripheral == SYSCTL_PERIPH_UDMA) ||
(ulPeripheral == SYSCTL_PERIPH_USB0) ||
(ulPeripheral == SYSCTL_PERIPH_WDOG));
(ulPeripheral == SYSCTL_PERIPH_WDOG0) ||
(ulPeripheral == SYSCTL_PERIPH_WDOG1));
}
#endif
@ -372,8 +376,22 @@ SysCtlPeripheralPresent(unsigned long ulPeripheral)
//
// Read the correct DC register and determine if this peripheral exists.
//
if(HWREG(g_pulDCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &
SYSCTL_PERIPH_MASK(ulPeripheral))
if(ulPeripheral == SYSCTL_PERIPH_USB0)
{
//
// USB is a special case since the DC bit is missing for USB0.
//
if(HWREG(SYSCTL_DC6) && SYSCTL_DC6_USB0_M)
{
return(true);
}
else
{
return(false);
}
}
else if(HWREG(g_pulDCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &
SYSCTL_PERIPH_MASK(ulPeripheral))
{
return(true);
}
@ -1451,6 +1469,16 @@ SysCtlClockSet(unsigned long ulConfig)
SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
ulRCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M);
ulRCC2 |= ulConfig & SYSCTL_RCC2_SYSDIV2_M;
if(ulConfig & SYSCTL_RCC2_USEFRACT)
{
ulRCC |= SYSCTL_RCC_USESYSDIV;
ulRCC2 &= ~(SYSCTL_RCC_USESYSDIV);
ulRCC2 |= ulConfig & (SYSCTL_RCC2_USEFRACT | SYSCTL_RCC2_FRACT);
}
else
{
ulRCC2 &= ~(SYSCTL_RCC2_USEFRACT);
}
//
// See if the PLL output is being used to clock the system.
@ -1551,13 +1579,21 @@ SysCtlClockGet(void)
//
ulClk = 15000000;
}
else if((CLASS_IS_FURY && REVISION_IS_A2) ||
(CLASS_IS_DUSTDEVIL && REVISION_IS_A0))
{
//
// The internal oscillator on a rev A2 Fury-class device and a
// rev A0 Dustdevil-class device is 12 MHz +/- 30%.
//
ulClk = 12000000;
}
else
{
//
// The internal oscillator on a Fury-class device is 12 MHz
// +/- 30%.
// The internal oscillator on all other devices is 16 MHz.
//
ulClk = 12000000;
ulClk = 16000000;
}
break;
}
@ -1578,13 +1614,21 @@ SysCtlClockGet(void)
//
ulClk = 15000000 / 4;
}
else if((CLASS_IS_FURY && REVISION_IS_A2) ||
(CLASS_IS_DUSTDEVIL && REVISION_IS_A0))
{
//
// The internal oscillator on a rev A2 Fury-class device and a
// rev A0 Dustdevil-class device is 12 MHz +/- 30%.
//
ulClk = 12000000 / 4;
}
else
{
//
// The internal oscillator on a Fury-class device is 12 MHz
// +/- 30%.
// The internal oscillator on a Tempest-class device is 16 MHz.
//
ulClk = 12000000 / 4;
ulClk = 16000000 / 4;
}
break;
}
@ -1601,6 +1645,15 @@ SysCtlClockGet(void)
break;
}
//
// The 4.19 MHz clock from the hibernate module is the clock source.
//
case SYSCTL_RCC2_OSCSRC2_419:
{
ulClk = 4194304;
break;
}
//
// The 32 KHz clock from the hibernate module is the source clock.
//
@ -1674,6 +1727,12 @@ SysCtlClockGet(void)
{
ulClk /= 4;
}
//
// Force the system divider to be enabled. It is always used when
// using the PLL, but in some cases it will not read as being enabled.
//
ulRCC |= SYSCTL_RCC_USESYSDIV;
}
//
@ -1686,8 +1745,22 @@ SysCtlClockGet(void)
//
if(ulRCC2 & SYSCTL_RCC2_USERCC2)
{
ulClk /= (((ulRCC2 & SYSCTL_RCC2_SYSDIV2_M) >>
SYSCTL_RCC2_SYSDIV2_S) + 1);
if((ulRCC2 & SYSCTL_RCC2_USEFRACT) &&
(((ulRCC2 & SYSCTL_RCC2_USERCC2) &&
!(ulRCC2 & SYSCTL_RCC2_BYPASS2)) ||
(!(ulRCC2 & SYSCTL_RCC2_USERCC2) &&
!(ulRCC & SYSCTL_RCC_BYPASS))))
{
ulClk = ((ulClk * 2) / (((ulRCC2 & (SYSCTL_RCC2_SYSDIV2_M |
SYSCTL_RCC2_FRACT)) >>
(SYSCTL_RCC2_SYSDIV2_S - 1)) + 1));
}
else
{
ulClk /= (((ulRCC2 & SYSCTL_RCC2_SYSDIV2_M) >>
SYSCTL_RCC2_SYSDIV2_S) + 1);
}
}
else
{
@ -1820,7 +1893,7 @@ SysCtlADCSpeedSet(unsigned long ulSpeed)
//
// Check that there is an ADC block on this part.
//
ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC);
ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC0);
//
// Set the ADC speed in run, sleep, and deep-sleep mode.
@ -1850,7 +1923,7 @@ SysCtlADCSpeedGet(void)
//
// Check that there is an ADC block on this part.
//
ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC);
ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC0);
//
// Return the current ADC speed.
@ -1998,16 +2071,16 @@ SysCtlClkVerificationClear(void)
//*****************************************************************************
//
//! Enables a GPIO peripheral for access from the high speed bus.
//! Enables a GPIO peripheral for access from the AHB.
//!
//! \param ulGPIOPeripheral is the GPIO peripheral to enable.
//!
//! This function is used to enable the specified GPIO peripherals to be
//! accessed from the high speed bus instead of the peripheral bus. When
//! a GPIO peripheral is enabled for high speed access, the \b _AHB_BASE
//! form of the base address should be used for GPIO functions. For example,
//! instead of using \b GPIO_PORTA_BASE as the base address for GPIO functions,
//! use \b GPIO_PORTA_AHB_BASE instead.
//! This function is used to enable the specified GPIO peripheral to be
//! accessed from the Advanced Host Bus (AHB) instead of the legacy Advanced
//! Peripheral Bus (APB). When a GPIO peripheral is enabled for AHB access,
//! the \b _AHB_BASE form of the base address should be used for GPIO
//! functions. For example, instead of using \b GPIO_PORTA_BASE as the base
//! address for GPIO functions, use \b GPIO_PORTA_AHB_BASE instead.
//!
//! The \e ulGPIOPeripheral argument must be only one of the following values:
//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
@ -2030,7 +2103,8 @@ SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral)
(ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
(ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
(ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
(ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH));
(ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
(ulGPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
//
// Enable this GPIO for AHB access.
@ -2040,13 +2114,13 @@ SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral)
//*****************************************************************************
//
//! Disables a GPIO peripheral for access from the high speed bus.
//! Disables a GPIO peripheral for access from the AHB.
//!
//! \param ulGPIOPeripheral is the GPIO peripheral to disable.
//!
//! This function will disable the specified GPIO peripherals for access
//! from the high speed bus. Once disabled, the GPIO peripheral is accessed
//! from the peripheral bus.
//! This function disables the specified GPIO peripheral for access from the
//! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed
//! from the legacy Advanced Peripheral Bus (AHB).
//!
//! The \b ulGPIOPeripheral argument must be only one of the following values:
//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
@ -2069,7 +2143,8 @@ SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral)
(ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
(ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
(ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
(ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH));
(ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
(ulGPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
//
// Disable this GPIO for AHB access.
@ -2117,6 +2192,145 @@ SysCtlUSBPLLDisable(void)
HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN;
}
//*****************************************************************************
//
//! Sets the MCLK frequency provided to the I2S module.
//!
//! \param ulInputClock is the input clock to the MCLK divider. If this is
//! zero, the value is computed from the current PLL configuration.
//! \param ulMClk is the desired MCLK frequency. If this is zero, MCLK output
//! is disabled.
//!
//! This function sets the dividers to provide MCLK to the I2S module. A MCLK
//! divider will be chosen that produces the MCLK frequency that is the closest
//! possible to the requested frequency, which may be above or below the
//! requested frequency.
//!
//! The actual MCLK frequency will be returned. It is the responsibility of
//! the application to determine if the selected MCLK is acceptable; in general
//! the human ear can not discern the frequency difference if it is within 0.3%
//! of the desired frequency (though there is a very small percentage of the
//! population that can discern lower frequency deviations).
//!
//! \return Returns the actual MCLK frequency.
//
//*****************************************************************************
unsigned long
SysCtlI2SMClkSet(unsigned long ulInputClock, unsigned long ulMClk)
{
unsigned long ulDivInt, ulDivFrac, ulPLL;
//
// See if the I2S MCLK should be disabled.
//
if(ulMClk == 0)
{
//
// Disable the I2S MCLK and return.
//
HWREG(SYSCTL_I2SMCLKCFG) = 0;
return(0);
}
//
// See if the input clock was specified.
//
if(ulInputClock == 0)
{
//
// The input clock was not specified, so compute the output frequency
// of the PLL. Get the current PLL configuration.
//
ulPLL = HWREG(SYSCTL_PLLCFG);
//
// Get the frequency of the crystal in use.
//
ulInputClock = g_pulXtals[(HWREG(SYSCTL_RCC) & SYSCTL_RCC_XTAL_M) >>
SYSCTL_RCC_XTAL_S];
//
// Calculate the PLL output frequency.
//
ulInputClock = ((ulInputClock * ((ulPLL & SYSCTL_PLLCFG_F_M) >>
SYSCTL_PLLCFG_F_S)) /
((((ulPLL & SYSCTL_PLLCFG_R_M) >>
SYSCTL_PLLCFG_R_S) + 1)));
//
// See if the optional output divide by 2 is being used.
//
if(ulPLL & SYSCTL_PLLCFG_OD_2)
{
ulInputClock /= 2;
}
//
// See if the optional output divide by 4 is being used.
//
if(ulPLL & SYSCTL_PLLCFG_OD_4)
{
ulInputClock /= 4;
}
}
//
// Verify that the requested MCLK frequency is attainable.
//
ASSERT(ulMClk < ulInputClock);
//
// Add a rounding factor to the input clock, so that the MCLK frequency
// that is closest to the desire value is selected.
//
ulInputClock += (ulMClk / 32) - 1;
//
// Compute the integer portion of the MCLK divider.
//
ulDivInt = ulInputClock / ulMClk;
//
// If the divisor is too large, then simply use the maximum divisor.
//
if(CLASS_IS_TEMPEST && REVISION_IS_B1 && (ulDivInt > 255))
{
ulDivInt = 255;
ulDivFrac = 15;
}
else if(ulDivInt > 1023)
{
ulDivInt = 1023;
ulDivFrac = 15;
}
else
{
//
// Compute the fractional portion of the MCLK divider.
//
ulDivFrac = ((ulInputClock - (ulDivInt * ulMClk)) * 16) / ulMClk;
}
//
// Set the divisor for the Tx and Rx MCLK generators and enable the clocks.
//
HWREG(SYSCTL_I2SMCLKCFG) = (SYSCTL_I2SMCLKCFG_RXEN |
(ulDivInt << SYSCTL_I2SMCLKCFG_RXI_S) |
(ulDivFrac << SYSCTL_I2SMCLKCFG_RXF_S) |
SYSCTL_I2SMCLKCFG_TXEN |
(ulDivInt << SYSCTL_I2SMCLKCFG_TXI_S) |
(ulDivFrac << SYSCTL_I2SMCLKCFG_TXF_S));
//
// Return the actual MCLK frequency.
//
ulInputClock -= (ulMClk / 32) - 1;
ulDivInt = (ulDivInt * 16) + ulDivFrac;
ulMClk = (ulInputClock / ulDivInt) * 16;
ulMClk += ((ulInputClock - ((ulMClk / 16) * ulDivInt)) * 16) / ulDivInt;
return(ulMClk);
}
//*****************************************************************************
//
// Close the Doxygen group.

81
src/platform/lm3s/sysctl.h Normal file → Executable file
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@ -2,7 +2,7 @@
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -48,13 +48,21 @@ extern "C"
// is 3) can only be used with the SysCtlPeripheralPresent() API.
//
//*****************************************************************************
#ifndef DEPRECATED
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
#endif
#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0
#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
#ifndef DEPRECATED
#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
#endif
#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
@ -80,6 +88,8 @@ extern "C"
#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0
#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
@ -88,6 +98,7 @@ extern "C"
#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J
#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
#define SYSCTL_PERIPH_ETH 0x20105000 // ETH
@ -298,6 +309,68 @@ extern "C"
#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
@ -327,7 +400,9 @@ extern "C"
#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
#define SYSCTL_INT_PIOSC_DIS 0x00000004 // Disable interal precision osc.
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
@ -379,6 +454,8 @@ extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
extern void SysCtlUSBPLLEnable(void);
extern void SysCtlUSBPLLDisable(void);
extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock,
unsigned long ulMClk);
//*****************************************************************************
//

4
src/platform/lm3s/systick.c Normal file → Executable file
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@ -2,7 +2,7 @@
//
// systick.c - Driver for the SysTick timer in NVIC.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

4
src/platform/lm3s/systick.h Normal file → Executable file
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@ -2,7 +2,7 @@
//
// systick.h - Prototypes for the SysTick driver.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

4
src/platform/lm3s/timer.c Normal file → Executable file
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@ -2,7 +2,7 @@
//
// timer.c - Driver for the timer module.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

4
src/platform/lm3s/timer.h Normal file → Executable file
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@ -2,7 +2,7 @@
//
// timer.h - Prototypes for the timer module
//
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
@ -21,7 +21,7 @@
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 3740 of the Stellaris Peripheral Driver Library.
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

1621
src/platform/lm3s/uart.c Executable file
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File diff suppressed because it is too large Load Diff

246
src/platform/lm3s/uart.h Executable file
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@ -0,0 +1,246 @@
//*****************************************************************************
//
// uart.h - Defines and Macros for the UART.
//
// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws. All rights are reserved. You may not combine
// this software with "viral" open-source software in order to form a larger
// program. Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __UART_H__
#define __UART_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
#define UART_INT_RX 0x010 // Receive Interrupt Mask
#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask
#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask
#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
#define UART_INT_RI 0x001 // RI Modem Interrupt Mask
//*****************************************************************************
//
// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
// and returned by UARTConfigGetExpClk in the pulConfig parameter.
// Additionally, the UART_CONFIG_PAR_* subset can be passed to
// UARTParityModeSet as the ulParity parameter, and are returned by
// UARTParityModeGet.
//
//*****************************************************************************
#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
// returned by UARTFIFOLevelGet in the pulTxLevel.
//
//*****************************************************************************
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
// returned by UARTFIFOLevelGet in the pulRxLevel.
//
//*****************************************************************************
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
//
//*****************************************************************************
#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
#define UART_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Values returned from UARTRxErrorGet().
//
//*****************************************************************************
#define UART_RXERROR_OVERRUN 0x00000008
#define UART_RXERROR_BREAK 0x00000004
#define UART_RXERROR_PARITY 0x00000002
#define UART_RXERROR_FRAMING 0x00000001
//*****************************************************************************
//
// Values that can be passed to UARTHandshakeOutputsSet() or returned from
// UARTHandshakeOutputGet().
//
//*****************************************************************************
#define UART_OUTPUT_RTS 0x00000800
#define UART_OUTPUT_DTR 0x00000400
//*****************************************************************************
//
// Values that can be returned from UARTHandshakeInputsGet().
//
//*****************************************************************************
#define UART_INPUT_RI 0x00000100
#define UART_INPUT_DCD 0x00000004
#define UART_INPUT_DSR 0x00000002
#define UART_INPUT_CTS 0x00000001
//*****************************************************************************
//
// Values that can be passed to UARTFlowControl() or returned from
// UARTFlowControlGet().
//
//*****************************************************************************
#define UART_FLOWCONTROL_TX 0x00008000
#define UART_FLOWCONTROL_RX 0x00004000
#define UART_FLOWCONTROL_NONE 0x00000000
//*****************************************************************************
//
// Values that can be passed to UARTTxIntModeSet() or returned from
// UARTTxIntModeGet().
//
//*****************************************************************************
#define UART_TXINT_MODE_FIFO 0x00000000
#define UART_TXINT_MODE_EOT 0x00000010
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
extern unsigned long UARTParityModeGet(unsigned long ulBase);
extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulRxLevel);
extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
unsigned long *pulRxLevel);
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long ulBaud, unsigned long ulConfig);
extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long *pulBaud,
unsigned long *pulConfig);
extern void UARTEnable(unsigned long ulBase);
extern void UARTDisable(unsigned long ulBase);
extern void UARTFIFOEnable(unsigned long ulBase);
extern void UARTFIFODisable(unsigned long ulBase);
extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
extern void UARTDisableSIR(unsigned long ulBase);
extern tBoolean UARTCharsAvail(unsigned long ulBase);
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
extern long UARTCharGetNonBlocking(unsigned long ulBase);
extern long UARTCharGet(unsigned long ulBase);
extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
unsigned char ucData);
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
extern tBoolean UARTBusy(unsigned long ulBase);
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void UARTIntUnregister(unsigned long ulBase);
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
extern unsigned long UARTRxErrorGet(unsigned long ulBase);
extern void UARTRxErrorClear(unsigned long ulBase);
extern void UARTSmartCardEnable(unsigned long ulBase);
extern void UARTSmartCardDisable(unsigned long ulBase);
extern void UARTModemControlSet(unsigned long ulBase,
unsigned long ulControl);
extern void UARTModemControlClear(unsigned long ulBase,
unsigned long ulControl);
extern unsigned long UARTModemControlGet(unsigned long ulBase);
extern unsigned long UARTModemStatusGet(unsigned long ulBase);
extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTFlowControlGet(unsigned long ulBase);
extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
//*****************************************************************************
//
// Several UART APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "sysctl.h"
#define UARTConfigSet(a, b, c) \
UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
#define UARTConfigGet(a, b, c) \
UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
#define UARTCharNonBlockingGet(a) \
UARTCharGetNonBlocking(a)
#define UARTCharNonBlockingPut(a, b) \
UARTCharPutNonBlocking(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __UART_H__